Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
760285e7 DH |
26 | #include <drm/drmP.h> |
27 | #include <drm/drm_edid.h> | |
28 | #include <drm/drm_crtc_helper.h> | |
29 | #include <drm/drm_fb_helper.h> | |
30 | #include <drm/radeon_drm.h> | |
771fe6b9 | 31 | #include "radeon.h" |
923f6848 | 32 | #include "atom.h" |
771fe6b9 | 33 | |
10ebc0bc DA |
34 | #include <linux/pm_runtime.h> |
35 | ||
d4877cf2 AD |
36 | void radeon_connector_hotplug(struct drm_connector *connector) |
37 | { | |
38 | struct drm_device *dev = connector->dev; | |
39 | struct radeon_device *rdev = dev->dev_private; | |
40 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
41 | ||
cbac9543 AD |
42 | /* bail if the connector does not have hpd pin, e.g., |
43 | * VGA, TV, etc. | |
44 | */ | |
45 | if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) | |
46 | return; | |
47 | ||
1e85e1d0 | 48 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
d4877cf2 | 49 | |
73104b5c | 50 | /* if the connector is already off, don't turn it back on */ |
6e9f798d | 51 | /* FIXME: This access isn't protected by any locks. */ |
73104b5c AD |
52 | if (connector->dpms != DRM_MODE_DPMS_ON) |
53 | return; | |
54 | ||
d5811e87 AD |
55 | /* just deal with DP (not eDP) here. */ |
56 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { | |
266dcba5 JG |
57 | struct radeon_connector_atom_dig *dig_connector = |
58 | radeon_connector->con_priv; | |
7c3ed0fd | 59 | |
266dcba5 JG |
60 | /* if existing sink type was not DP no need to retrain */ |
61 | if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) | |
62 | return; | |
63 | ||
64 | /* first get sink type as it may be reset after (un)plug */ | |
65 | dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector); | |
66 | /* don't do anything if sink is not display port, i.e., | |
67 | * passive dp->(dvi|hdmi) adaptor | |
68 | */ | |
69 | if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { | |
70 | int saved_dpms = connector->dpms; | |
71 | /* Only turn off the display if it's physically disconnected */ | |
ca2ccde5 | 72 | if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) { |
266dcba5 | 73 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); |
ca2ccde5 JG |
74 | } else if (radeon_dp_needs_link_train(radeon_connector)) { |
75 | /* set it to OFF so that drm_helper_connector_dpms() | |
76 | * won't return immediately since the current state | |
77 | * is ON at this point. | |
78 | */ | |
79 | connector->dpms = DRM_MODE_DPMS_OFF; | |
266dcba5 | 80 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); |
ca2ccde5 | 81 | } |
266dcba5 JG |
82 | connector->dpms = saved_dpms; |
83 | } | |
d4877cf2 | 84 | } |
d4877cf2 AD |
85 | } |
86 | ||
445282db DA |
87 | static void radeon_property_change_mode(struct drm_encoder *encoder) |
88 | { | |
89 | struct drm_crtc *crtc = encoder->crtc; | |
90 | ||
91 | if (crtc && crtc->enabled) { | |
92 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
f4510a27 | 93 | crtc->x, crtc->y, crtc->primary->fb); |
445282db DA |
94 | } |
95 | } | |
eccea792 AD |
96 | |
97 | int radeon_get_monitor_bpc(struct drm_connector *connector) | |
98 | { | |
99 | struct drm_device *dev = connector->dev; | |
100 | struct radeon_device *rdev = dev->dev_private; | |
101 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
102 | struct radeon_connector_atom_dig *dig_connector; | |
103 | int bpc = 8; | |
ea292861 | 104 | int mode_clock, max_tmds_clock; |
eccea792 AD |
105 | |
106 | switch (connector->connector_type) { | |
107 | case DRM_MODE_CONNECTOR_DVII: | |
108 | case DRM_MODE_CONNECTOR_HDMIB: | |
109 | if (radeon_connector->use_digital) { | |
377bd8a9 | 110 | if (drm_detect_hdmi_monitor(radeon_connector_edid(connector))) { |
eccea792 AD |
111 | if (connector->display_info.bpc) |
112 | bpc = connector->display_info.bpc; | |
113 | } | |
114 | } | |
115 | break; | |
116 | case DRM_MODE_CONNECTOR_DVID: | |
117 | case DRM_MODE_CONNECTOR_HDMIA: | |
377bd8a9 | 118 | if (drm_detect_hdmi_monitor(radeon_connector_edid(connector))) { |
eccea792 AD |
119 | if (connector->display_info.bpc) |
120 | bpc = connector->display_info.bpc; | |
121 | } | |
122 | break; | |
123 | case DRM_MODE_CONNECTOR_DisplayPort: | |
124 | dig_connector = radeon_connector->con_priv; | |
125 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || | |
126 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || | |
377bd8a9 | 127 | drm_detect_hdmi_monitor(radeon_connector_edid(connector))) { |
eccea792 AD |
128 | if (connector->display_info.bpc) |
129 | bpc = connector->display_info.bpc; | |
130 | } | |
131 | break; | |
132 | case DRM_MODE_CONNECTOR_eDP: | |
133 | case DRM_MODE_CONNECTOR_LVDS: | |
134 | if (connector->display_info.bpc) | |
135 | bpc = connector->display_info.bpc; | |
136 | else if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { | |
137 | struct drm_connector_helper_funcs *connector_funcs = | |
138 | connector->helper_private; | |
139 | struct drm_encoder *encoder = connector_funcs->best_encoder(connector); | |
140 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
141 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
142 | ||
143 | if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) | |
144 | bpc = 6; | |
145 | else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) | |
146 | bpc = 8; | |
147 | } | |
148 | break; | |
149 | } | |
89b92339 | 150 | |
377bd8a9 | 151 | if (drm_detect_hdmi_monitor(radeon_connector_edid(connector))) { |
89b92339 MK |
152 | /* hdmi deep color only implemented on DCE4+ */ |
153 | if ((bpc > 8) && !ASIC_IS_DCE4(rdev)) { | |
154 | DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 8 bpc.\n", | |
72082093 | 155 | connector->name, bpc); |
89b92339 MK |
156 | bpc = 8; |
157 | } | |
158 | ||
159 | /* | |
160 | * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make | |
161 | * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at | |
162 | * 12 bpc is always supported on hdmi deep color sinks, as this is | |
163 | * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. | |
164 | */ | |
165 | if (bpc > 12) { | |
166 | DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", | |
72082093 | 167 | connector->name, bpc); |
89b92339 MK |
168 | bpc = 12; |
169 | } | |
ea292861 MK |
170 | |
171 | /* Any defined maximum tmds clock limit we must not exceed? */ | |
172 | if (connector->max_tmds_clock > 0) { | |
173 | /* mode_clock is clock in kHz for mode to be modeset on this connector */ | |
174 | mode_clock = radeon_connector->pixelclock_for_modeset; | |
175 | ||
176 | /* Maximum allowable input clock in kHz */ | |
177 | max_tmds_clock = connector->max_tmds_clock * 1000; | |
178 | ||
179 | DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", | |
180 | connector->name, mode_clock, max_tmds_clock); | |
181 | ||
182 | /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ | |
183 | if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { | |
184 | if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && | |
185 | (mode_clock * 5/4 <= max_tmds_clock)) | |
186 | bpc = 10; | |
187 | else | |
188 | bpc = 8; | |
189 | ||
190 | DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", | |
191 | connector->name, bpc); | |
192 | } | |
193 | ||
194 | if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { | |
195 | bpc = 8; | |
196 | DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", | |
197 | connector->name, bpc); | |
198 | } | |
199 | } | |
9f51e2e0 MK |
200 | else if (bpc > 8) { |
201 | /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ | |
202 | DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", | |
203 | connector->name); | |
204 | bpc = 8; | |
205 | } | |
89b92339 MK |
206 | } |
207 | ||
9f51e2e0 MK |
208 | if ((radeon_deep_color == 0) && (bpc > 8)) { |
209 | DRM_DEBUG("%s: Deep color disabled. Set radeon module param deep_color=1 to enable.\n", | |
210 | connector->name); | |
a624f429 | 211 | bpc = 8; |
9f51e2e0 | 212 | } |
a624f429 | 213 | |
89b92339 | 214 | DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", |
72082093 | 215 | connector->name, connector->display_info.bpc, bpc); |
89b92339 | 216 | |
eccea792 AD |
217 | return bpc; |
218 | } | |
219 | ||
771fe6b9 JG |
220 | static void |
221 | radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_connector_status status) | |
222 | { | |
223 | struct drm_device *dev = connector->dev; | |
224 | struct radeon_device *rdev = dev->dev_private; | |
225 | struct drm_encoder *best_encoder = NULL; | |
226 | struct drm_encoder *encoder = NULL; | |
227 | struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; | |
771fe6b9 JG |
228 | bool connected; |
229 | int i; | |
230 | ||
231 | best_encoder = connector_funcs->best_encoder(connector); | |
232 | ||
233 | for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { | |
234 | if (connector->encoder_ids[i] == 0) | |
235 | break; | |
236 | ||
b957f457 RC |
237 | encoder = drm_encoder_find(connector->dev, |
238 | connector->encoder_ids[i]); | |
239 | if (!encoder) | |
771fe6b9 JG |
240 | continue; |
241 | ||
771fe6b9 JG |
242 | if ((encoder == best_encoder) && (status == connector_status_connected)) |
243 | connected = true; | |
244 | else | |
245 | connected = false; | |
246 | ||
247 | if (rdev->is_atom_bios) | |
248 | radeon_atombios_connected_scratch_regs(connector, encoder, connected); | |
249 | else | |
250 | radeon_combios_connected_scratch_regs(connector, encoder, connected); | |
251 | ||
252 | } | |
253 | } | |
254 | ||
1109ca09 | 255 | static struct drm_encoder *radeon_find_encoder(struct drm_connector *connector, int encoder_type) |
445282db | 256 | { |
445282db DA |
257 | struct drm_encoder *encoder; |
258 | int i; | |
259 | ||
260 | for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { | |
261 | if (connector->encoder_ids[i] == 0) | |
262 | break; | |
263 | ||
b957f457 RC |
264 | encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); |
265 | if (!encoder) | |
445282db DA |
266 | continue; |
267 | ||
445282db DA |
268 | if (encoder->encoder_type == encoder_type) |
269 | return encoder; | |
270 | } | |
271 | return NULL; | |
272 | } | |
273 | ||
377bd8a9 AD |
274 | struct edid *radeon_connector_edid(struct drm_connector *connector) |
275 | { | |
276 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
277 | struct drm_property_blob *edid_blob = connector->edid_blob_ptr; | |
278 | ||
279 | if (radeon_connector->edid) { | |
280 | return radeon_connector->edid; | |
281 | } else if (edid_blob) { | |
282 | struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); | |
283 | if (edid) | |
284 | radeon_connector->edid = edid; | |
285 | } | |
286 | return radeon_connector->edid; | |
287 | } | |
288 | ||
72a5c970 AD |
289 | static void radeon_connector_get_edid(struct drm_connector *connector) |
290 | { | |
291 | struct drm_device *dev = connector->dev; | |
292 | struct radeon_device *rdev = dev->dev_private; | |
293 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
294 | ||
295 | if (radeon_connector->edid) | |
296 | return; | |
297 | ||
298 | /* on hw with routers, select right port */ | |
299 | if (radeon_connector->router.ddc_valid) | |
300 | radeon_router_select_ddc_port(radeon_connector); | |
301 | ||
302 | if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) != | |
303 | ENCODER_OBJECT_ID_NONE) && | |
304 | radeon_connector->ddc_bus->has_aux) { | |
305 | radeon_connector->edid = drm_get_edid(connector, | |
306 | &radeon_connector->ddc_bus->aux.ddc); | |
307 | } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || | |
308 | (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { | |
309 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; | |
310 | ||
311 | if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || | |
312 | dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && | |
313 | radeon_connector->ddc_bus->has_aux) | |
314 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, | |
315 | &radeon_connector->ddc_bus->aux.ddc); | |
316 | else if (radeon_connector->ddc_bus) | |
317 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, | |
318 | &radeon_connector->ddc_bus->adapter); | |
319 | } else if (radeon_connector->ddc_bus) { | |
320 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, | |
321 | &radeon_connector->ddc_bus->adapter); | |
322 | } | |
323 | ||
324 | if (!radeon_connector->edid) { | |
13485794 AD |
325 | /* don't fetch the edid from the vbios if ddc fails and runpm is |
326 | * enabled so we report disconnected. | |
327 | */ | |
328 | if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0)) | |
329 | return; | |
330 | ||
72a5c970 AD |
331 | if (rdev->is_atom_bios) { |
332 | /* some laptops provide a hardcoded edid in rom for LCDs */ | |
333 | if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || | |
334 | (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) | |
335 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); | |
336 | } else { | |
337 | /* some servers provide a hardcoded edid in rom for KVMs */ | |
338 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); | |
339 | } | |
340 | } | |
341 | } | |
342 | ||
343 | static void radeon_connector_free_edid(struct drm_connector *connector) | |
344 | { | |
345 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
346 | ||
347 | if (radeon_connector->edid) { | |
348 | kfree(radeon_connector->edid); | |
349 | radeon_connector->edid = NULL; | |
350 | } | |
351 | } | |
352 | ||
353 | static int radeon_ddc_get_modes(struct drm_connector *connector) | |
354 | { | |
355 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
356 | int ret; | |
357 | ||
358 | if (radeon_connector->edid) { | |
359 | drm_mode_connector_update_edid_property(connector, radeon_connector->edid); | |
360 | ret = drm_add_edid_modes(connector, radeon_connector->edid); | |
361 | drm_edid_to_eld(connector, radeon_connector->edid); | |
362 | return ret; | |
363 | } | |
364 | drm_mode_connector_update_edid_property(connector, NULL); | |
365 | return 0; | |
366 | } | |
367 | ||
1109ca09 | 368 | static struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector) |
771fe6b9 JG |
369 | { |
370 | int enc_id = connector->encoder_ids[0]; | |
771fe6b9 | 371 | /* pick the encoder ids */ |
b957f457 RC |
372 | if (enc_id) |
373 | return drm_encoder_find(connector->dev, enc_id); | |
771fe6b9 JG |
374 | return NULL; |
375 | } | |
376 | ||
da997620 AD |
377 | static void radeon_get_native_mode(struct drm_connector *connector) |
378 | { | |
379 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); | |
380 | struct radeon_encoder *radeon_encoder; | |
381 | ||
382 | if (encoder == NULL) | |
383 | return; | |
384 | ||
385 | radeon_encoder = to_radeon_encoder(encoder); | |
386 | ||
387 | if (!list_empty(&connector->probed_modes)) { | |
388 | struct drm_display_mode *preferred_mode = | |
389 | list_first_entry(&connector->probed_modes, | |
390 | struct drm_display_mode, head); | |
391 | ||
392 | radeon_encoder->native_mode = *preferred_mode; | |
393 | } else { | |
394 | radeon_encoder->native_mode.clock = 0; | |
395 | } | |
396 | } | |
397 | ||
4ce001ab DA |
398 | /* |
399 | * radeon_connector_analog_encoder_conflict_solve | |
400 | * - search for other connectors sharing this encoder | |
401 | * if priority is true, then set them disconnected if this is connected | |
402 | * if priority is false, set us disconnected if they are connected | |
403 | */ | |
404 | static enum drm_connector_status | |
405 | radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector, | |
406 | struct drm_encoder *encoder, | |
407 | enum drm_connector_status current_status, | |
408 | bool priority) | |
409 | { | |
410 | struct drm_device *dev = connector->dev; | |
411 | struct drm_connector *conflict; | |
08d07511 | 412 | struct radeon_connector *radeon_conflict; |
4ce001ab DA |
413 | int i; |
414 | ||
415 | list_for_each_entry(conflict, &dev->mode_config.connector_list, head) { | |
416 | if (conflict == connector) | |
417 | continue; | |
418 | ||
08d07511 | 419 | radeon_conflict = to_radeon_connector(conflict); |
4ce001ab DA |
420 | for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { |
421 | if (conflict->encoder_ids[i] == 0) | |
422 | break; | |
423 | ||
424 | /* if the IDs match */ | |
425 | if (conflict->encoder_ids[i] == encoder->base.id) { | |
426 | if (conflict->status != connector_status_connected) | |
427 | continue; | |
08d07511 AD |
428 | |
429 | if (radeon_conflict->use_digital) | |
430 | continue; | |
4ce001ab DA |
431 | |
432 | if (priority == true) { | |
72082093 JN |
433 | DRM_DEBUG_KMS("1: conflicting encoders switching off %s\n", |
434 | conflict->name); | |
435 | DRM_DEBUG_KMS("in favor of %s\n", | |
436 | connector->name); | |
4ce001ab DA |
437 | conflict->status = connector_status_disconnected; |
438 | radeon_connector_update_scratch_regs(conflict, connector_status_disconnected); | |
439 | } else { | |
72082093 JN |
440 | DRM_DEBUG_KMS("2: conflicting encoders switching off %s\n", |
441 | connector->name); | |
442 | DRM_DEBUG_KMS("in favor of %s\n", | |
443 | conflict->name); | |
4ce001ab DA |
444 | current_status = connector_status_disconnected; |
445 | } | |
446 | break; | |
447 | } | |
448 | } | |
449 | } | |
450 | return current_status; | |
451 | ||
452 | } | |
453 | ||
771fe6b9 JG |
454 | static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encoder) |
455 | { | |
456 | struct drm_device *dev = encoder->dev; | |
457 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
458 | struct drm_display_mode *mode = NULL; | |
de2103e4 | 459 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
771fe6b9 | 460 | |
de2103e4 AD |
461 | if (native_mode->hdisplay != 0 && |
462 | native_mode->vdisplay != 0 && | |
463 | native_mode->clock != 0) { | |
fb06ca8f | 464 | mode = drm_mode_duplicate(dev, native_mode); |
771fe6b9 JG |
465 | mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; |
466 | drm_mode_set_name(mode); | |
467 | ||
d9fdaafb | 468 | DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); |
d2efdf6d AD |
469 | } else if (native_mode->hdisplay != 0 && |
470 | native_mode->vdisplay != 0) { | |
471 | /* mac laptops without an edid */ | |
472 | /* Note that this is not necessarily the exact panel mode, | |
473 | * but an approximation based on the cvt formula. For these | |
474 | * systems we should ideally read the mode info out of the | |
475 | * registers or add a mode table, but this works and is much | |
476 | * simpler. | |
477 | */ | |
478 | mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); | |
479 | mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; | |
d9fdaafb | 480 | DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); |
771fe6b9 JG |
481 | } |
482 | return mode; | |
483 | } | |
484 | ||
923f6848 AD |
485 | static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_connector *connector) |
486 | { | |
487 | struct drm_device *dev = encoder->dev; | |
488 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
489 | struct drm_display_mode *mode = NULL; | |
de2103e4 | 490 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
923f6848 AD |
491 | int i; |
492 | struct mode_size { | |
493 | int w; | |
494 | int h; | |
495 | } common_modes[17] = { | |
496 | { 640, 480}, | |
497 | { 720, 480}, | |
498 | { 800, 600}, | |
499 | { 848, 480}, | |
500 | {1024, 768}, | |
501 | {1152, 768}, | |
502 | {1280, 720}, | |
503 | {1280, 800}, | |
504 | {1280, 854}, | |
505 | {1280, 960}, | |
506 | {1280, 1024}, | |
507 | {1440, 900}, | |
508 | {1400, 1050}, | |
509 | {1680, 1050}, | |
510 | {1600, 1200}, | |
511 | {1920, 1080}, | |
512 | {1920, 1200} | |
513 | }; | |
514 | ||
515 | for (i = 0; i < 17; i++) { | |
dfdd6467 AD |
516 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { |
517 | if (common_modes[i].w > 1024 || | |
518 | common_modes[i].h > 768) | |
519 | continue; | |
520 | } | |
923f6848 | 521 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
de2103e4 AD |
522 | if (common_modes[i].w > native_mode->hdisplay || |
523 | common_modes[i].h > native_mode->vdisplay || | |
524 | (common_modes[i].w == native_mode->hdisplay && | |
525 | common_modes[i].h == native_mode->vdisplay)) | |
923f6848 AD |
526 | continue; |
527 | } | |
528 | if (common_modes[i].w < 320 || common_modes[i].h < 200) | |
529 | continue; | |
530 | ||
d50ba256 | 531 | mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); |
923f6848 AD |
532 | drm_mode_probed_add(connector, mode); |
533 | } | |
534 | } | |
535 | ||
1109ca09 | 536 | static int radeon_connector_set_property(struct drm_connector *connector, struct drm_property *property, |
771fe6b9 JG |
537 | uint64_t val) |
538 | { | |
445282db DA |
539 | struct drm_device *dev = connector->dev; |
540 | struct radeon_device *rdev = dev->dev_private; | |
541 | struct drm_encoder *encoder; | |
542 | struct radeon_encoder *radeon_encoder; | |
543 | ||
544 | if (property == rdev->mode_info.coherent_mode_property) { | |
545 | struct radeon_encoder_atom_dig *dig; | |
ce227c41 | 546 | bool new_coherent_mode; |
445282db DA |
547 | |
548 | /* need to find digital encoder on connector */ | |
549 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); | |
550 | if (!encoder) | |
551 | return 0; | |
552 | ||
553 | radeon_encoder = to_radeon_encoder(encoder); | |
554 | ||
555 | if (!radeon_encoder->enc_priv) | |
556 | return 0; | |
557 | ||
558 | dig = radeon_encoder->enc_priv; | |
ce227c41 DA |
559 | new_coherent_mode = val ? true : false; |
560 | if (dig->coherent_mode != new_coherent_mode) { | |
561 | dig->coherent_mode = new_coherent_mode; | |
562 | radeon_property_change_mode(&radeon_encoder->base); | |
563 | } | |
445282db DA |
564 | } |
565 | ||
8666c076 AD |
566 | if (property == rdev->mode_info.audio_property) { |
567 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
568 | /* need to find digital encoder on connector */ | |
569 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); | |
570 | if (!encoder) | |
571 | return 0; | |
572 | ||
573 | radeon_encoder = to_radeon_encoder(encoder); | |
574 | ||
575 | if (radeon_connector->audio != val) { | |
576 | radeon_connector->audio = val; | |
577 | radeon_property_change_mode(&radeon_encoder->base); | |
578 | } | |
579 | } | |
580 | ||
6214bb74 AD |
581 | if (property == rdev->mode_info.dither_property) { |
582 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
583 | /* need to find digital encoder on connector */ | |
584 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); | |
585 | if (!encoder) | |
586 | return 0; | |
587 | ||
588 | radeon_encoder = to_radeon_encoder(encoder); | |
589 | ||
590 | if (radeon_connector->dither != val) { | |
591 | radeon_connector->dither = val; | |
592 | radeon_property_change_mode(&radeon_encoder->base); | |
593 | } | |
594 | } | |
595 | ||
5b1714d3 AD |
596 | if (property == rdev->mode_info.underscan_property) { |
597 | /* need to find digital encoder on connector */ | |
598 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); | |
599 | if (!encoder) | |
600 | return 0; | |
601 | ||
602 | radeon_encoder = to_radeon_encoder(encoder); | |
603 | ||
604 | if (radeon_encoder->underscan_type != val) { | |
605 | radeon_encoder->underscan_type = val; | |
606 | radeon_property_change_mode(&radeon_encoder->base); | |
607 | } | |
608 | } | |
609 | ||
5bccf5e3 MG |
610 | if (property == rdev->mode_info.underscan_hborder_property) { |
611 | /* need to find digital encoder on connector */ | |
612 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); | |
613 | if (!encoder) | |
614 | return 0; | |
615 | ||
616 | radeon_encoder = to_radeon_encoder(encoder); | |
617 | ||
618 | if (radeon_encoder->underscan_hborder != val) { | |
619 | radeon_encoder->underscan_hborder = val; | |
620 | radeon_property_change_mode(&radeon_encoder->base); | |
621 | } | |
622 | } | |
623 | ||
624 | if (property == rdev->mode_info.underscan_vborder_property) { | |
625 | /* need to find digital encoder on connector */ | |
626 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); | |
627 | if (!encoder) | |
628 | return 0; | |
629 | ||
630 | radeon_encoder = to_radeon_encoder(encoder); | |
631 | ||
632 | if (radeon_encoder->underscan_vborder != val) { | |
633 | radeon_encoder->underscan_vborder = val; | |
634 | radeon_property_change_mode(&radeon_encoder->base); | |
635 | } | |
636 | } | |
637 | ||
445282db DA |
638 | if (property == rdev->mode_info.tv_std_property) { |
639 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TVDAC); | |
640 | if (!encoder) { | |
641 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_DAC); | |
642 | } | |
643 | ||
644 | if (!encoder) | |
645 | return 0; | |
646 | ||
647 | radeon_encoder = to_radeon_encoder(encoder); | |
648 | if (!radeon_encoder->enc_priv) | |
649 | return 0; | |
643acacf | 650 | if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) { |
445282db DA |
651 | struct radeon_encoder_atom_dac *dac_int; |
652 | dac_int = radeon_encoder->enc_priv; | |
653 | dac_int->tv_std = val; | |
654 | } else { | |
655 | struct radeon_encoder_tv_dac *dac_int; | |
656 | dac_int = radeon_encoder->enc_priv; | |
657 | dac_int->tv_std = val; | |
658 | } | |
659 | radeon_property_change_mode(&radeon_encoder->base); | |
660 | } | |
661 | ||
662 | if (property == rdev->mode_info.load_detect_property) { | |
663 | struct radeon_connector *radeon_connector = | |
664 | to_radeon_connector(connector); | |
665 | ||
666 | if (val == 0) | |
667 | radeon_connector->dac_load_detect = false; | |
668 | else | |
669 | radeon_connector->dac_load_detect = true; | |
670 | } | |
671 | ||
672 | if (property == rdev->mode_info.tmds_pll_property) { | |
673 | struct radeon_encoder_int_tmds *tmds = NULL; | |
674 | bool ret = false; | |
675 | /* need to find digital encoder on connector */ | |
676 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); | |
677 | if (!encoder) | |
678 | return 0; | |
679 | ||
680 | radeon_encoder = to_radeon_encoder(encoder); | |
681 | ||
682 | tmds = radeon_encoder->enc_priv; | |
683 | if (!tmds) | |
684 | return 0; | |
685 | ||
686 | if (val == 0) { | |
687 | if (rdev->is_atom_bios) | |
688 | ret = radeon_atombios_get_tmds_info(radeon_encoder, tmds); | |
689 | else | |
690 | ret = radeon_legacy_get_tmds_info_from_combios(radeon_encoder, tmds); | |
691 | } | |
692 | if (val == 1 || ret == false) { | |
693 | radeon_legacy_get_tmds_info_from_table(radeon_encoder, tmds); | |
694 | } | |
695 | radeon_property_change_mode(&radeon_encoder->base); | |
696 | } | |
697 | ||
da997620 AD |
698 | if (property == dev->mode_config.scaling_mode_property) { |
699 | enum radeon_rmx_type rmx_type; | |
700 | ||
701 | if (connector->encoder) | |
702 | radeon_encoder = to_radeon_encoder(connector->encoder); | |
703 | else { | |
704 | struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; | |
705 | radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector)); | |
706 | } | |
707 | ||
708 | switch (val) { | |
709 | default: | |
710 | case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; | |
711 | case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; | |
712 | case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; | |
713 | case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; | |
714 | } | |
715 | if (radeon_encoder->rmx_type == rmx_type) | |
716 | return 0; | |
717 | ||
718 | if ((rmx_type != DRM_MODE_SCALE_NONE) && | |
719 | (radeon_encoder->native_mode.clock == 0)) | |
720 | return 0; | |
721 | ||
722 | radeon_encoder->rmx_type = rmx_type; | |
723 | ||
724 | radeon_property_change_mode(&radeon_encoder->base); | |
725 | } | |
726 | ||
771fe6b9 JG |
727 | return 0; |
728 | } | |
729 | ||
8dfaa8a7 MD |
730 | static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder, |
731 | struct drm_connector *connector) | |
732 | { | |
733 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
de2103e4 | 734 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
13bb9430 MG |
735 | struct drm_display_mode *t, *mode; |
736 | ||
737 | /* If the EDID preferred mode doesn't match the native mode, use it */ | |
738 | list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { | |
739 | if (mode->type & DRM_MODE_TYPE_PREFERRED) { | |
740 | if (mode->hdisplay != native_mode->hdisplay || | |
741 | mode->vdisplay != native_mode->vdisplay) | |
742 | memcpy(native_mode, mode, sizeof(*mode)); | |
743 | } | |
744 | } | |
8dfaa8a7 MD |
745 | |
746 | /* Try to get native mode details from EDID if necessary */ | |
de2103e4 | 747 | if (!native_mode->clock) { |
8dfaa8a7 | 748 | list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { |
de2103e4 AD |
749 | if (mode->hdisplay == native_mode->hdisplay && |
750 | mode->vdisplay == native_mode->vdisplay) { | |
751 | *native_mode = *mode; | |
752 | drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); | |
c5d46b4e | 753 | DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); |
8dfaa8a7 MD |
754 | break; |
755 | } | |
756 | } | |
757 | } | |
13bb9430 | 758 | |
de2103e4 | 759 | if (!native_mode->clock) { |
c5d46b4e | 760 | DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); |
8dfaa8a7 MD |
761 | radeon_encoder->rmx_type = RMX_OFF; |
762 | } | |
763 | } | |
771fe6b9 JG |
764 | |
765 | static int radeon_lvds_get_modes(struct drm_connector *connector) | |
766 | { | |
771fe6b9 JG |
767 | struct drm_encoder *encoder; |
768 | int ret = 0; | |
769 | struct drm_display_mode *mode; | |
770 | ||
72a5c970 AD |
771 | radeon_connector_get_edid(connector); |
772 | ret = radeon_ddc_get_modes(connector); | |
773 | if (ret > 0) { | |
774 | encoder = radeon_best_single_encoder(connector); | |
775 | if (encoder) { | |
776 | radeon_fixup_lvds_native_mode(encoder, connector); | |
777 | /* add scaled modes */ | |
778 | radeon_add_common_modes(encoder, connector); | |
771fe6b9 | 779 | } |
72a5c970 | 780 | return ret; |
771fe6b9 JG |
781 | } |
782 | ||
783 | encoder = radeon_best_single_encoder(connector); | |
784 | if (!encoder) | |
785 | return 0; | |
786 | ||
787 | /* we have no EDID modes */ | |
788 | mode = radeon_fp_native_mode(encoder); | |
789 | if (mode) { | |
790 | ret = 1; | |
791 | drm_mode_probed_add(connector, mode); | |
7a868e18 AD |
792 | /* add the width/height from vbios tables if available */ |
793 | connector->display_info.width_mm = mode->width_mm; | |
794 | connector->display_info.height_mm = mode->height_mm; | |
7747b713 AD |
795 | /* add scaled modes */ |
796 | radeon_add_common_modes(encoder, connector); | |
771fe6b9 | 797 | } |
923f6848 | 798 | |
771fe6b9 JG |
799 | return ret; |
800 | } | |
801 | ||
802 | static int radeon_lvds_mode_valid(struct drm_connector *connector, | |
803 | struct drm_display_mode *mode) | |
804 | { | |
a3fa6320 AD |
805 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); |
806 | ||
807 | if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) | |
808 | return MODE_PANEL; | |
809 | ||
810 | if (encoder) { | |
811 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
812 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; | |
813 | ||
814 | /* AVIVO hardware supports downscaling modes larger than the panel | |
815 | * to the panel size, but I'm not sure this is desirable. | |
816 | */ | |
817 | if ((mode->hdisplay > native_mode->hdisplay) || | |
818 | (mode->vdisplay > native_mode->vdisplay)) | |
819 | return MODE_PANEL; | |
820 | ||
821 | /* if scaling is disabled, block non-native modes */ | |
822 | if (radeon_encoder->rmx_type == RMX_OFF) { | |
823 | if ((mode->hdisplay != native_mode->hdisplay) || | |
824 | (mode->vdisplay != native_mode->vdisplay)) | |
825 | return MODE_PANEL; | |
826 | } | |
827 | } | |
828 | ||
771fe6b9 JG |
829 | return MODE_OK; |
830 | } | |
831 | ||
7b334fcb | 832 | static enum drm_connector_status |
930a9e28 | 833 | radeon_lvds_detect(struct drm_connector *connector, bool force) |
771fe6b9 | 834 | { |
13485794 AD |
835 | struct drm_device *dev = connector->dev; |
836 | struct radeon_device *rdev = dev->dev_private; | |
0549a061 | 837 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
2ffb8429 | 838 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); |
0549a061 | 839 | enum drm_connector_status ret = connector_status_disconnected; |
10ebc0bc DA |
840 | int r; |
841 | ||
842 | r = pm_runtime_get_sync(connector->dev->dev); | |
843 | if (r < 0) | |
844 | return connector_status_disconnected; | |
2ffb8429 AD |
845 | |
846 | if (encoder) { | |
847 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
de2103e4 | 848 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
2ffb8429 AD |
849 | |
850 | /* check if panel is valid */ | |
de2103e4 | 851 | if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) |
2ffb8429 | 852 | ret = connector_status_connected; |
13485794 AD |
853 | /* don't fetch the edid from the vbios if ddc fails and runpm is |
854 | * enabled so we report disconnected. | |
855 | */ | |
856 | if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0)) | |
857 | ret = connector_status_disconnected; | |
2ffb8429 | 858 | } |
0549a061 AD |
859 | |
860 | /* check for edid as well */ | |
72a5c970 | 861 | radeon_connector_get_edid(connector); |
0294cf4f AD |
862 | if (radeon_connector->edid) |
863 | ret = connector_status_connected; | |
771fe6b9 | 864 | /* check acpi lid status ??? */ |
2ffb8429 | 865 | |
771fe6b9 | 866 | radeon_connector_update_scratch_regs(connector, ret); |
10ebc0bc DA |
867 | pm_runtime_mark_last_busy(connector->dev->dev); |
868 | pm_runtime_put_autosuspend(connector->dev->dev); | |
771fe6b9 JG |
869 | return ret; |
870 | } | |
871 | ||
872 | static void radeon_connector_destroy(struct drm_connector *connector) | |
873 | { | |
874 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
875 | ||
72a5c970 | 876 | radeon_connector_free_edid(connector); |
771fe6b9 | 877 | kfree(radeon_connector->con_priv); |
34ea3d38 | 878 | drm_connector_unregister(connector); |
771fe6b9 JG |
879 | drm_connector_cleanup(connector); |
880 | kfree(connector); | |
881 | } | |
882 | ||
445282db DA |
883 | static int radeon_lvds_set_property(struct drm_connector *connector, |
884 | struct drm_property *property, | |
885 | uint64_t value) | |
886 | { | |
887 | struct drm_device *dev = connector->dev; | |
888 | struct radeon_encoder *radeon_encoder; | |
889 | enum radeon_rmx_type rmx_type; | |
890 | ||
d9fdaafb | 891 | DRM_DEBUG_KMS("\n"); |
445282db DA |
892 | if (property != dev->mode_config.scaling_mode_property) |
893 | return 0; | |
894 | ||
895 | if (connector->encoder) | |
896 | radeon_encoder = to_radeon_encoder(connector->encoder); | |
897 | else { | |
898 | struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; | |
899 | radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector)); | |
900 | } | |
901 | ||
902 | switch (value) { | |
903 | case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; | |
904 | case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; | |
905 | case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; | |
906 | default: | |
907 | case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; | |
908 | } | |
909 | if (radeon_encoder->rmx_type == rmx_type) | |
910 | return 0; | |
911 | ||
912 | radeon_encoder->rmx_type = rmx_type; | |
913 | ||
914 | radeon_property_change_mode(&radeon_encoder->base); | |
915 | return 0; | |
916 | } | |
917 | ||
918 | ||
1109ca09 | 919 | static const struct drm_connector_helper_funcs radeon_lvds_connector_helper_funcs = { |
771fe6b9 JG |
920 | .get_modes = radeon_lvds_get_modes, |
921 | .mode_valid = radeon_lvds_mode_valid, | |
922 | .best_encoder = radeon_best_single_encoder, | |
923 | }; | |
924 | ||
1109ca09 | 925 | static const struct drm_connector_funcs radeon_lvds_connector_funcs = { |
771fe6b9 JG |
926 | .dpms = drm_helper_connector_dpms, |
927 | .detect = radeon_lvds_detect, | |
928 | .fill_modes = drm_helper_probe_single_connector_modes, | |
929 | .destroy = radeon_connector_destroy, | |
445282db | 930 | .set_property = radeon_lvds_set_property, |
771fe6b9 JG |
931 | }; |
932 | ||
933 | static int radeon_vga_get_modes(struct drm_connector *connector) | |
934 | { | |
771fe6b9 JG |
935 | int ret; |
936 | ||
72a5c970 AD |
937 | radeon_connector_get_edid(connector); |
938 | ret = radeon_ddc_get_modes(connector); | |
771fe6b9 | 939 | |
da997620 AD |
940 | radeon_get_native_mode(connector); |
941 | ||
771fe6b9 JG |
942 | return ret; |
943 | } | |
944 | ||
945 | static int radeon_vga_mode_valid(struct drm_connector *connector, | |
946 | struct drm_display_mode *mode) | |
947 | { | |
b20f9bef AD |
948 | struct drm_device *dev = connector->dev; |
949 | struct radeon_device *rdev = dev->dev_private; | |
950 | ||
a3fa6320 | 951 | /* XXX check mode bandwidth */ |
b20f9bef AD |
952 | |
953 | if ((mode->clock / 10) > rdev->clock.max_pixel_clock) | |
954 | return MODE_CLOCK_HIGH; | |
955 | ||
771fe6b9 JG |
956 | return MODE_OK; |
957 | } | |
958 | ||
7b334fcb | 959 | static enum drm_connector_status |
930a9e28 | 960 | radeon_vga_detect(struct drm_connector *connector, bool force) |
771fe6b9 | 961 | { |
fafcf94e AD |
962 | struct drm_device *dev = connector->dev; |
963 | struct radeon_device *rdev = dev->dev_private; | |
771fe6b9 JG |
964 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
965 | struct drm_encoder *encoder; | |
966 | struct drm_encoder_helper_funcs *encoder_funcs; | |
4b9d2a21 | 967 | bool dret = false; |
771fe6b9 | 968 | enum drm_connector_status ret = connector_status_disconnected; |
10ebc0bc DA |
969 | int r; |
970 | ||
971 | r = pm_runtime_get_sync(connector->dev->dev); | |
972 | if (r < 0) | |
973 | return connector_status_disconnected; | |
771fe6b9 | 974 | |
4ce001ab DA |
975 | encoder = radeon_best_single_encoder(connector); |
976 | if (!encoder) | |
977 | ret = connector_status_disconnected; | |
978 | ||
eb6b6d7c | 979 | if (radeon_connector->ddc_bus) |
0a9069d3 | 980 | dret = radeon_ddc_probe(radeon_connector, false); |
0294cf4f | 981 | if (dret) { |
d0d0a225 | 982 | radeon_connector->detected_by_load = false; |
72a5c970 AD |
983 | radeon_connector_free_edid(connector); |
984 | radeon_connector_get_edid(connector); | |
0294cf4f AD |
985 | |
986 | if (!radeon_connector->edid) { | |
f82f5f3a | 987 | DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", |
72082093 | 988 | connector->name); |
f82f5f3a | 989 | ret = connector_status_connected; |
0294cf4f | 990 | } else { |
72a5c970 AD |
991 | radeon_connector->use_digital = |
992 | !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); | |
0294cf4f AD |
993 | |
994 | /* some oems have boards with separate digital and analog connectors | |
995 | * with a shared ddc line (often vga + hdmi) | |
996 | */ | |
997 | if (radeon_connector->use_digital && radeon_connector->shared_ddc) { | |
72a5c970 | 998 | radeon_connector_free_edid(connector); |
0294cf4f | 999 | ret = connector_status_disconnected; |
72a5c970 | 1000 | } else { |
0294cf4f | 1001 | ret = connector_status_connected; |
72a5c970 | 1002 | } |
0294cf4f AD |
1003 | } |
1004 | } else { | |
c3cceedd DA |
1005 | |
1006 | /* if we aren't forcing don't do destructive polling */ | |
d0d0a225 AD |
1007 | if (!force) { |
1008 | /* only return the previous status if we last | |
1009 | * detected a monitor via load. | |
1010 | */ | |
1011 | if (radeon_connector->detected_by_load) | |
10ebc0bc DA |
1012 | ret = connector->status; |
1013 | goto out; | |
d0d0a225 | 1014 | } |
c3cceedd | 1015 | |
d8a7f792 | 1016 | if (radeon_connector->dac_load_detect && encoder) { |
445282db DA |
1017 | encoder_funcs = encoder->helper_private; |
1018 | ret = encoder_funcs->detect(encoder, connector); | |
34076446 | 1019 | if (ret != connector_status_disconnected) |
d0d0a225 | 1020 | radeon_connector->detected_by_load = true; |
445282db | 1021 | } |
771fe6b9 JG |
1022 | } |
1023 | ||
4ce001ab DA |
1024 | if (ret == connector_status_connected) |
1025 | ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true); | |
fafcf94e AD |
1026 | |
1027 | /* RN50 and some RV100 asics in servers often have a hardcoded EDID in the | |
1028 | * vbios to deal with KVMs. If we have one and are not able to detect a monitor | |
1029 | * by other means, assume the CRT is connected and use that EDID. | |
1030 | */ | |
1031 | if ((!rdev->is_atom_bios) && | |
1032 | (ret == connector_status_disconnected) && | |
1033 | rdev->mode_info.bios_hardcoded_edid_size) { | |
1034 | ret = connector_status_connected; | |
1035 | } | |
1036 | ||
771fe6b9 | 1037 | radeon_connector_update_scratch_regs(connector, ret); |
10ebc0bc DA |
1038 | |
1039 | out: | |
1040 | pm_runtime_mark_last_busy(connector->dev->dev); | |
1041 | pm_runtime_put_autosuspend(connector->dev->dev); | |
1042 | ||
771fe6b9 JG |
1043 | return ret; |
1044 | } | |
1045 | ||
1109ca09 | 1046 | static const struct drm_connector_helper_funcs radeon_vga_connector_helper_funcs = { |
771fe6b9 JG |
1047 | .get_modes = radeon_vga_get_modes, |
1048 | .mode_valid = radeon_vga_mode_valid, | |
1049 | .best_encoder = radeon_best_single_encoder, | |
1050 | }; | |
1051 | ||
1109ca09 | 1052 | static const struct drm_connector_funcs radeon_vga_connector_funcs = { |
771fe6b9 JG |
1053 | .dpms = drm_helper_connector_dpms, |
1054 | .detect = radeon_vga_detect, | |
1055 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1056 | .destroy = radeon_connector_destroy, | |
1057 | .set_property = radeon_connector_set_property, | |
1058 | }; | |
1059 | ||
4ce001ab DA |
1060 | static int radeon_tv_get_modes(struct drm_connector *connector) |
1061 | { | |
1062 | struct drm_device *dev = connector->dev; | |
923f6848 | 1063 | struct radeon_device *rdev = dev->dev_private; |
4ce001ab | 1064 | struct drm_display_mode *tv_mode; |
923f6848 | 1065 | struct drm_encoder *encoder; |
4ce001ab | 1066 | |
923f6848 AD |
1067 | encoder = radeon_best_single_encoder(connector); |
1068 | if (!encoder) | |
1069 | return 0; | |
4ce001ab | 1070 | |
923f6848 AD |
1071 | /* avivo chips can scale any mode */ |
1072 | if (rdev->family >= CHIP_RS600) | |
1073 | /* add scaled modes */ | |
1074 | radeon_add_common_modes(encoder, connector); | |
1075 | else { | |
1076 | /* only 800x600 is supported right now on pre-avivo chips */ | |
d50ba256 | 1077 | tv_mode = drm_cvt_mode(dev, 800, 600, 60, false, false, false); |
923f6848 AD |
1078 | tv_mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; |
1079 | drm_mode_probed_add(connector, tv_mode); | |
1080 | } | |
4ce001ab DA |
1081 | return 1; |
1082 | } | |
1083 | ||
1084 | static int radeon_tv_mode_valid(struct drm_connector *connector, | |
1085 | struct drm_display_mode *mode) | |
1086 | { | |
a3fa6320 AD |
1087 | if ((mode->hdisplay > 1024) || (mode->vdisplay > 768)) |
1088 | return MODE_CLOCK_RANGE; | |
4ce001ab DA |
1089 | return MODE_OK; |
1090 | } | |
1091 | ||
7b334fcb | 1092 | static enum drm_connector_status |
930a9e28 | 1093 | radeon_tv_detect(struct drm_connector *connector, bool force) |
4ce001ab DA |
1094 | { |
1095 | struct drm_encoder *encoder; | |
1096 | struct drm_encoder_helper_funcs *encoder_funcs; | |
445282db DA |
1097 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1098 | enum drm_connector_status ret = connector_status_disconnected; | |
10ebc0bc | 1099 | int r; |
445282db DA |
1100 | |
1101 | if (!radeon_connector->dac_load_detect) | |
1102 | return ret; | |
4ce001ab | 1103 | |
10ebc0bc DA |
1104 | r = pm_runtime_get_sync(connector->dev->dev); |
1105 | if (r < 0) | |
1106 | return connector_status_disconnected; | |
1107 | ||
4ce001ab DA |
1108 | encoder = radeon_best_single_encoder(connector); |
1109 | if (!encoder) | |
1110 | ret = connector_status_disconnected; | |
1111 | else { | |
1112 | encoder_funcs = encoder->helper_private; | |
1113 | ret = encoder_funcs->detect(encoder, connector); | |
1114 | } | |
1115 | if (ret == connector_status_connected) | |
1116 | ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, false); | |
1117 | radeon_connector_update_scratch_regs(connector, ret); | |
10ebc0bc DA |
1118 | pm_runtime_mark_last_busy(connector->dev->dev); |
1119 | pm_runtime_put_autosuspend(connector->dev->dev); | |
4ce001ab DA |
1120 | return ret; |
1121 | } | |
1122 | ||
1109ca09 | 1123 | static const struct drm_connector_helper_funcs radeon_tv_connector_helper_funcs = { |
4ce001ab DA |
1124 | .get_modes = radeon_tv_get_modes, |
1125 | .mode_valid = radeon_tv_mode_valid, | |
1126 | .best_encoder = radeon_best_single_encoder, | |
1127 | }; | |
1128 | ||
1109ca09 | 1129 | static const struct drm_connector_funcs radeon_tv_connector_funcs = { |
4ce001ab DA |
1130 | .dpms = drm_helper_connector_dpms, |
1131 | .detect = radeon_tv_detect, | |
1132 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1133 | .destroy = radeon_connector_destroy, | |
1134 | .set_property = radeon_connector_set_property, | |
1135 | }; | |
1136 | ||
11fe1266 TU |
1137 | static bool radeon_check_hpd_status_unchanged(struct drm_connector *connector) |
1138 | { | |
1139 | struct drm_device *dev = connector->dev; | |
1140 | struct radeon_device *rdev = dev->dev_private; | |
1141 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
1142 | enum drm_connector_status status; | |
1143 | ||
1144 | /* We only trust HPD on R600 and newer ASICS. */ | |
1145 | if (rdev->family >= CHIP_R600 | |
1146 | && radeon_connector->hpd.hpd != RADEON_HPD_NONE) { | |
1147 | if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) | |
1148 | status = connector_status_connected; | |
1149 | else | |
1150 | status = connector_status_disconnected; | |
1151 | if (connector->status == status) | |
1152 | return true; | |
1153 | } | |
1154 | ||
1155 | return false; | |
1156 | } | |
1157 | ||
4ce001ab DA |
1158 | /* |
1159 | * DVI is complicated | |
1160 | * Do a DDC probe, if DDC probe passes, get the full EDID so | |
1161 | * we can do analog/digital monitor detection at this point. | |
1162 | * If the monitor is an analog monitor or we got no DDC, | |
1163 | * we need to find the DAC encoder object for this connector. | |
1164 | * If we got no DDC, we do load detection on the DAC encoder object. | |
1165 | * If we got analog DDC or load detection passes on the DAC encoder | |
1166 | * we have to check if this analog encoder is shared with anyone else (TV) | |
1167 | * if its shared we have to set the other connector to disconnected. | |
1168 | */ | |
7b334fcb | 1169 | static enum drm_connector_status |
930a9e28 | 1170 | radeon_dvi_detect(struct drm_connector *connector, bool force) |
771fe6b9 | 1171 | { |
fafcf94e AD |
1172 | struct drm_device *dev = connector->dev; |
1173 | struct radeon_device *rdev = dev->dev_private; | |
771fe6b9 | 1174 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
4ce001ab | 1175 | struct drm_encoder *encoder = NULL; |
771fe6b9 | 1176 | struct drm_encoder_helper_funcs *encoder_funcs; |
10ebc0bc | 1177 | int i, r; |
771fe6b9 | 1178 | enum drm_connector_status ret = connector_status_disconnected; |
fc87f13b | 1179 | bool dret = false, broken_edid = false; |
771fe6b9 | 1180 | |
10ebc0bc DA |
1181 | r = pm_runtime_get_sync(connector->dev->dev); |
1182 | if (r < 0) | |
1183 | return connector_status_disconnected; | |
1184 | ||
1185 | if (!force && radeon_check_hpd_status_unchanged(connector)) { | |
1186 | ret = connector->status; | |
1187 | goto exit; | |
1188 | } | |
11fe1266 | 1189 | |
eb6b6d7c | 1190 | if (radeon_connector->ddc_bus) |
0a9069d3 | 1191 | dret = radeon_ddc_probe(radeon_connector, false); |
4ce001ab | 1192 | if (dret) { |
d0d0a225 | 1193 | radeon_connector->detected_by_load = false; |
72a5c970 AD |
1194 | radeon_connector_free_edid(connector); |
1195 | radeon_connector_get_edid(connector); | |
4ce001ab DA |
1196 | |
1197 | if (!radeon_connector->edid) { | |
f82f5f3a | 1198 | DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", |
72082093 | 1199 | connector->name); |
4a9a8b71 DA |
1200 | /* rs690 seems to have a problem with connectors not existing and always |
1201 | * return a block of 0's. If we see this just stop polling on this output */ | |
72a5c970 AD |
1202 | if ((rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) && |
1203 | radeon_connector->base.null_edid_counter) { | |
4a9a8b71 | 1204 | ret = connector_status_disconnected; |
72082093 JN |
1205 | DRM_ERROR("%s: detected RS690 floating bus bug, stopping ddc detect\n", |
1206 | connector->name); | |
4a9a8b71 | 1207 | radeon_connector->ddc_bus = NULL; |
fc87f13b EE |
1208 | } else { |
1209 | ret = connector_status_connected; | |
1210 | broken_edid = true; /* defer use_digital to later */ | |
4a9a8b71 | 1211 | } |
4ce001ab | 1212 | } else { |
72a5c970 AD |
1213 | radeon_connector->use_digital = |
1214 | !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); | |
4ce001ab | 1215 | |
0294cf4f AD |
1216 | /* some oems have boards with separate digital and analog connectors |
1217 | * with a shared ddc line (often vga + hdmi) | |
1218 | */ | |
1219 | if ((!radeon_connector->use_digital) && radeon_connector->shared_ddc) { | |
72a5c970 | 1220 | radeon_connector_free_edid(connector); |
0294cf4f | 1221 | ret = connector_status_disconnected; |
72a5c970 | 1222 | } else { |
0294cf4f | 1223 | ret = connector_status_connected; |
72a5c970 | 1224 | } |
42f14c4b AD |
1225 | /* This gets complicated. We have boards with VGA + HDMI with a |
1226 | * shared DDC line and we have boards with DVI-D + HDMI with a shared | |
1227 | * DDC line. The latter is more complex because with DVI<->HDMI adapters | |
1228 | * you don't really know what's connected to which port as both are digital. | |
71407c46 | 1229 | */ |
d3932d6c | 1230 | if (radeon_connector->shared_ddc && (ret == connector_status_connected)) { |
71407c46 AD |
1231 | struct drm_connector *list_connector; |
1232 | struct radeon_connector *list_radeon_connector; | |
1233 | list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) { | |
1234 | if (connector == list_connector) | |
1235 | continue; | |
1236 | list_radeon_connector = to_radeon_connector(list_connector); | |
b2ea4aa6 AD |
1237 | if (list_radeon_connector->shared_ddc && |
1238 | (list_radeon_connector->ddc_bus->rec.i2c_id == | |
1239 | radeon_connector->ddc_bus->rec.i2c_id)) { | |
42f14c4b AD |
1240 | /* cases where both connectors are digital */ |
1241 | if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { | |
1242 | /* hpd is our only option in this case */ | |
1243 | if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) { | |
72a5c970 | 1244 | radeon_connector_free_edid(connector); |
71407c46 AD |
1245 | ret = connector_status_disconnected; |
1246 | } | |
1247 | } | |
1248 | } | |
1249 | } | |
1250 | } | |
4ce001ab DA |
1251 | } |
1252 | } | |
1253 | ||
1254 | if ((ret == connector_status_connected) && (radeon_connector->use_digital == true)) | |
1255 | goto out; | |
1256 | ||
5f0a2612 AD |
1257 | /* DVI-D and HDMI-A are digital only */ |
1258 | if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || | |
1259 | (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) | |
1260 | goto out; | |
1261 | ||
d0d0a225 | 1262 | /* if we aren't forcing don't do destructive polling */ |
c3cceedd | 1263 | if (!force) { |
d0d0a225 AD |
1264 | /* only return the previous status if we last |
1265 | * detected a monitor via load. | |
1266 | */ | |
1267 | if (radeon_connector->detected_by_load) | |
1268 | ret = connector->status; | |
c3cceedd DA |
1269 | goto out; |
1270 | } | |
1271 | ||
4ce001ab | 1272 | /* find analog encoder */ |
445282db DA |
1273 | if (radeon_connector->dac_load_detect) { |
1274 | for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { | |
1275 | if (connector->encoder_ids[i] == 0) | |
1276 | break; | |
771fe6b9 | 1277 | |
b957f457 RC |
1278 | encoder = drm_encoder_find(connector->dev, |
1279 | connector->encoder_ids[i]); | |
1280 | if (!encoder) | |
445282db | 1281 | continue; |
771fe6b9 | 1282 | |
e3632507 | 1283 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && |
e00e8b5e AD |
1284 | encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) |
1285 | continue; | |
1286 | ||
445282db DA |
1287 | encoder_funcs = encoder->helper_private; |
1288 | if (encoder_funcs->detect) { | |
fc87f13b EE |
1289 | if (!broken_edid) { |
1290 | if (ret != connector_status_connected) { | |
1291 | /* deal with analog monitors without DDC */ | |
1292 | ret = encoder_funcs->detect(encoder, connector); | |
1293 | if (ret == connector_status_connected) { | |
1294 | radeon_connector->use_digital = false; | |
1295 | } | |
1296 | if (ret != connector_status_disconnected) | |
1297 | radeon_connector->detected_by_load = true; | |
445282db | 1298 | } |
fc87f13b EE |
1299 | } else { |
1300 | enum drm_connector_status lret; | |
1301 | /* assume digital unless load detected otherwise */ | |
1302 | radeon_connector->use_digital = true; | |
1303 | lret = encoder_funcs->detect(encoder, connector); | |
1304 | DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); | |
1305 | if (lret == connector_status_connected) | |
1306 | radeon_connector->use_digital = false; | |
771fe6b9 | 1307 | } |
445282db | 1308 | break; |
771fe6b9 JG |
1309 | } |
1310 | } | |
1311 | } | |
1312 | ||
4ce001ab DA |
1313 | if ((ret == connector_status_connected) && (radeon_connector->use_digital == false) && |
1314 | encoder) { | |
1315 | ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true); | |
1316 | } | |
1317 | ||
fafcf94e AD |
1318 | /* RN50 and some RV100 asics in servers often have a hardcoded EDID in the |
1319 | * vbios to deal with KVMs. If we have one and are not able to detect a monitor | |
1320 | * by other means, assume the DFP is connected and use that EDID. In most | |
1321 | * cases the DVI port is actually a virtual KVM port connected to the service | |
1322 | * processor. | |
1323 | */ | |
a09d431f | 1324 | out: |
fafcf94e AD |
1325 | if ((!rdev->is_atom_bios) && |
1326 | (ret == connector_status_disconnected) && | |
1327 | rdev->mode_info.bios_hardcoded_edid_size) { | |
1328 | radeon_connector->use_digital = true; | |
1329 | ret = connector_status_connected; | |
1330 | } | |
1331 | ||
771fe6b9 JG |
1332 | /* updated in get modes as well since we need to know if it's analog or digital */ |
1333 | radeon_connector_update_scratch_regs(connector, ret); | |
10ebc0bc DA |
1334 | |
1335 | exit: | |
1336 | pm_runtime_mark_last_busy(connector->dev->dev); | |
1337 | pm_runtime_put_autosuspend(connector->dev->dev); | |
1338 | ||
771fe6b9 JG |
1339 | return ret; |
1340 | } | |
1341 | ||
1342 | /* okay need to be smart in here about which encoder to pick */ | |
1109ca09 | 1343 | static struct drm_encoder *radeon_dvi_encoder(struct drm_connector *connector) |
771fe6b9 JG |
1344 | { |
1345 | int enc_id = connector->encoder_ids[0]; | |
1346 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
771fe6b9 JG |
1347 | struct drm_encoder *encoder; |
1348 | int i; | |
1349 | for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { | |
1350 | if (connector->encoder_ids[i] == 0) | |
1351 | break; | |
1352 | ||
b957f457 RC |
1353 | encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); |
1354 | if (!encoder) | |
771fe6b9 JG |
1355 | continue; |
1356 | ||
4ce001ab | 1357 | if (radeon_connector->use_digital == true) { |
771fe6b9 JG |
1358 | if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) |
1359 | return encoder; | |
1360 | } else { | |
1361 | if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || | |
1362 | encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) | |
1363 | return encoder; | |
1364 | } | |
1365 | } | |
1366 | ||
1367 | /* see if we have a default encoder TODO */ | |
1368 | ||
1369 | /* then check use digitial */ | |
1370 | /* pick the first one */ | |
b957f457 RC |
1371 | if (enc_id) |
1372 | return drm_encoder_find(connector->dev, enc_id); | |
771fe6b9 JG |
1373 | return NULL; |
1374 | } | |
1375 | ||
d50ba256 DA |
1376 | static void radeon_dvi_force(struct drm_connector *connector) |
1377 | { | |
1378 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
1379 | if (connector->force == DRM_FORCE_ON) | |
1380 | radeon_connector->use_digital = false; | |
1381 | if (connector->force == DRM_FORCE_ON_DIGITAL) | |
1382 | radeon_connector->use_digital = true; | |
1383 | } | |
1384 | ||
a3fa6320 AD |
1385 | static int radeon_dvi_mode_valid(struct drm_connector *connector, |
1386 | struct drm_display_mode *mode) | |
1387 | { | |
1b24203e AD |
1388 | struct drm_device *dev = connector->dev; |
1389 | struct radeon_device *rdev = dev->dev_private; | |
a3fa6320 AD |
1390 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1391 | ||
1392 | /* XXX check mode bandwidth */ | |
1393 | ||
1b24203e AD |
1394 | /* clocks over 135 MHz have heat issues with DVI on RV100 */ |
1395 | if (radeon_connector->use_digital && | |
1396 | (rdev->family == CHIP_RV100) && | |
1397 | (mode->clock > 135000)) | |
1398 | return MODE_CLOCK_HIGH; | |
1399 | ||
a3fa6320 AD |
1400 | if (radeon_connector->use_digital && (mode->clock > 165000)) { |
1401 | if ((radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || | |
1402 | (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || | |
1403 | (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) | |
1404 | return MODE_OK; | |
377bd8a9 | 1405 | else if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector_edid(connector))) { |
f2263fc7 AD |
1406 | /* HDMI 1.3+ supports max clock of 340 Mhz */ |
1407 | if (mode->clock > 340000) | |
e1e84017 | 1408 | return MODE_CLOCK_HIGH; |
f2263fc7 AD |
1409 | else |
1410 | return MODE_OK; | |
1411 | } else { | |
a3fa6320 | 1412 | return MODE_CLOCK_HIGH; |
f2263fc7 | 1413 | } |
a3fa6320 | 1414 | } |
b20f9bef AD |
1415 | |
1416 | /* check against the max pixel clock */ | |
1417 | if ((mode->clock / 10) > rdev->clock.max_pixel_clock) | |
1418 | return MODE_CLOCK_HIGH; | |
1419 | ||
a3fa6320 AD |
1420 | return MODE_OK; |
1421 | } | |
1422 | ||
1109ca09 | 1423 | static const struct drm_connector_helper_funcs radeon_dvi_connector_helper_funcs = { |
3e22920f | 1424 | .get_modes = radeon_vga_get_modes, |
a3fa6320 | 1425 | .mode_valid = radeon_dvi_mode_valid, |
771fe6b9 JG |
1426 | .best_encoder = radeon_dvi_encoder, |
1427 | }; | |
1428 | ||
1109ca09 | 1429 | static const struct drm_connector_funcs radeon_dvi_connector_funcs = { |
771fe6b9 JG |
1430 | .dpms = drm_helper_connector_dpms, |
1431 | .detect = radeon_dvi_detect, | |
1432 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1433 | .set_property = radeon_connector_set_property, | |
1434 | .destroy = radeon_connector_destroy, | |
d50ba256 | 1435 | .force = radeon_dvi_force, |
771fe6b9 JG |
1436 | }; |
1437 | ||
746c1aa4 DA |
1438 | static int radeon_dp_get_modes(struct drm_connector *connector) |
1439 | { | |
1440 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
8b834852 | 1441 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; |
591a10e1 | 1442 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); |
746c1aa4 DA |
1443 | int ret; |
1444 | ||
f89931f3 AD |
1445 | if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || |
1446 | (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { | |
d291767b AD |
1447 | struct drm_display_mode *mode; |
1448 | ||
2b69ffb9 AD |
1449 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
1450 | if (!radeon_dig_connector->edp_on) | |
1451 | atombios_set_edp_panel_power(connector, | |
1452 | ATOM_TRANSMITTER_ACTION_POWER_ON); | |
72a5c970 AD |
1453 | radeon_connector_get_edid(connector); |
1454 | ret = radeon_ddc_get_modes(connector); | |
2b69ffb9 AD |
1455 | if (!radeon_dig_connector->edp_on) |
1456 | atombios_set_edp_panel_power(connector, | |
1457 | ATOM_TRANSMITTER_ACTION_POWER_OFF); | |
1458 | } else { | |
1459 | /* need to setup ddc on the bridge */ | |
1460 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) != | |
1461 | ENCODER_OBJECT_ID_NONE) { | |
1462 | if (encoder) | |
1463 | radeon_atom_ext_encoder_setup_ddc(encoder); | |
1464 | } | |
72a5c970 AD |
1465 | radeon_connector_get_edid(connector); |
1466 | ret = radeon_ddc_get_modes(connector); | |
2b69ffb9 | 1467 | } |
d291767b AD |
1468 | |
1469 | if (ret > 0) { | |
d291767b AD |
1470 | if (encoder) { |
1471 | radeon_fixup_lvds_native_mode(encoder, connector); | |
1472 | /* add scaled modes */ | |
1473 | radeon_add_common_modes(encoder, connector); | |
1474 | } | |
1475 | return ret; | |
1476 | } | |
1477 | ||
d291767b AD |
1478 | if (!encoder) |
1479 | return 0; | |
1480 | ||
1481 | /* we have no EDID modes */ | |
1482 | mode = radeon_fp_native_mode(encoder); | |
1483 | if (mode) { | |
1484 | ret = 1; | |
1485 | drm_mode_probed_add(connector, mode); | |
1486 | /* add the width/height from vbios tables if available */ | |
1487 | connector->display_info.width_mm = mode->width_mm; | |
1488 | connector->display_info.height_mm = mode->height_mm; | |
1489 | /* add scaled modes */ | |
1490 | radeon_add_common_modes(encoder, connector); | |
1491 | } | |
591a10e1 AD |
1492 | } else { |
1493 | /* need to setup ddc on the bridge */ | |
1d33e1fc AD |
1494 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) != |
1495 | ENCODER_OBJECT_ID_NONE) { | |
591a10e1 AD |
1496 | if (encoder) |
1497 | radeon_atom_ext_encoder_setup_ddc(encoder); | |
1498 | } | |
72a5c970 AD |
1499 | radeon_connector_get_edid(connector); |
1500 | ret = radeon_ddc_get_modes(connector); | |
da997620 AD |
1501 | |
1502 | radeon_get_native_mode(connector); | |
591a10e1 | 1503 | } |
8b834852 | 1504 | |
746c1aa4 DA |
1505 | return ret; |
1506 | } | |
1507 | ||
1d33e1fc | 1508 | u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) |
d7fa8bb3 | 1509 | { |
d7fa8bb3 AD |
1510 | struct drm_encoder *encoder; |
1511 | struct radeon_encoder *radeon_encoder; | |
1512 | int i; | |
d7fa8bb3 AD |
1513 | |
1514 | for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { | |
1515 | if (connector->encoder_ids[i] == 0) | |
1516 | break; | |
1517 | ||
b957f457 RC |
1518 | encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); |
1519 | if (!encoder) | |
d7fa8bb3 AD |
1520 | continue; |
1521 | ||
d7fa8bb3 AD |
1522 | radeon_encoder = to_radeon_encoder(encoder); |
1523 | ||
1524 | switch (radeon_encoder->encoder_id) { | |
1525 | case ENCODER_OBJECT_ID_TRAVIS: | |
1526 | case ENCODER_OBJECT_ID_NUTMEG: | |
1d33e1fc | 1527 | return radeon_encoder->encoder_id; |
d7fa8bb3 AD |
1528 | default: |
1529 | break; | |
1530 | } | |
1531 | } | |
1532 | ||
1d33e1fc | 1533 | return ENCODER_OBJECT_ID_NONE; |
d7fa8bb3 AD |
1534 | } |
1535 | ||
ebdea82d | 1536 | static bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector) |
d7fa8bb3 | 1537 | { |
d7fa8bb3 AD |
1538 | struct drm_encoder *encoder; |
1539 | struct radeon_encoder *radeon_encoder; | |
1540 | int i; | |
1541 | bool found = false; | |
1542 | ||
1543 | for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { | |
1544 | if (connector->encoder_ids[i] == 0) | |
1545 | break; | |
1546 | ||
b957f457 RC |
1547 | encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); |
1548 | if (!encoder) | |
d7fa8bb3 AD |
1549 | continue; |
1550 | ||
d7fa8bb3 AD |
1551 | radeon_encoder = to_radeon_encoder(encoder); |
1552 | if (radeon_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) | |
1553 | found = true; | |
1554 | } | |
1555 | ||
1556 | return found; | |
1557 | } | |
1558 | ||
1559 | bool radeon_connector_is_dp12_capable(struct drm_connector *connector) | |
1560 | { | |
1561 | struct drm_device *dev = connector->dev; | |
1562 | struct radeon_device *rdev = dev->dev_private; | |
1563 | ||
1564 | if (ASIC_IS_DCE5(rdev) && | |
af5d3653 | 1565 | (rdev->clock.default_dispclk >= 53900) && |
d7fa8bb3 AD |
1566 | radeon_connector_encoder_is_hbr2(connector)) { |
1567 | return true; | |
1568 | } | |
1569 | ||
1570 | return false; | |
1571 | } | |
1572 | ||
7b334fcb | 1573 | static enum drm_connector_status |
930a9e28 | 1574 | radeon_dp_detect(struct drm_connector *connector, bool force) |
746c1aa4 | 1575 | { |
f8d0edde AD |
1576 | struct drm_device *dev = connector->dev; |
1577 | struct radeon_device *rdev = dev->dev_private; | |
746c1aa4 | 1578 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
746c1aa4 | 1579 | enum drm_connector_status ret = connector_status_disconnected; |
4143e919 | 1580 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; |
591a10e1 | 1581 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); |
10ebc0bc | 1582 | int r; |
746c1aa4 | 1583 | |
10ebc0bc DA |
1584 | r = pm_runtime_get_sync(connector->dev->dev); |
1585 | if (r < 0) | |
1586 | return connector_status_disconnected; | |
1587 | ||
1588 | if (!force && radeon_check_hpd_status_unchanged(connector)) { | |
1589 | ret = connector->status; | |
1590 | goto out; | |
1591 | } | |
11fe1266 | 1592 | |
72a5c970 | 1593 | radeon_connector_free_edid(connector); |
746c1aa4 | 1594 | |
f89931f3 AD |
1595 | if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || |
1596 | (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { | |
d291767b AD |
1597 | if (encoder) { |
1598 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1599 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; | |
1600 | ||
1601 | /* check if panel is valid */ | |
1602 | if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) | |
1603 | ret = connector_status_connected; | |
13485794 AD |
1604 | /* don't fetch the edid from the vbios if ddc fails and runpm is |
1605 | * enabled so we report disconnected. | |
1606 | */ | |
1607 | if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0)) | |
1608 | ret = connector_status_disconnected; | |
d291767b | 1609 | } |
6f50eae7 AD |
1610 | /* eDP is always DP */ |
1611 | radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; | |
8b834852 AD |
1612 | if (!radeon_dig_connector->edp_on) |
1613 | atombios_set_edp_panel_power(connector, | |
1614 | ATOM_TRANSMITTER_ACTION_POWER_ON); | |
6f50eae7 | 1615 | if (radeon_dp_getdpcd(radeon_connector)) |
9fa05c98 | 1616 | ret = connector_status_connected; |
8b834852 AD |
1617 | if (!radeon_dig_connector->edp_on) |
1618 | atombios_set_edp_panel_power(connector, | |
1619 | ATOM_TRANSMITTER_ACTION_POWER_OFF); | |
1d33e1fc AD |
1620 | } else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) != |
1621 | ENCODER_OBJECT_ID_NONE) { | |
b06947b5 AD |
1622 | /* DP bridges are always DP */ |
1623 | radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; | |
1624 | /* get the DPCD from the bridge */ | |
1625 | radeon_dp_getdpcd(radeon_connector); | |
1626 | ||
6777a4f6 AD |
1627 | if (encoder) { |
1628 | /* setup ddc on the bridge */ | |
1629 | radeon_atom_ext_encoder_setup_ddc(encoder); | |
0a9069d3 NOS |
1630 | /* bridge chips are always aux */ |
1631 | if (radeon_ddc_probe(radeon_connector, true)) /* try DDC */ | |
b06947b5 | 1632 | ret = connector_status_connected; |
6777a4f6 AD |
1633 | else if (radeon_connector->dac_load_detect) { /* try load detection */ |
1634 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
b06947b5 AD |
1635 | ret = encoder_funcs->detect(encoder, connector); |
1636 | } | |
591a10e1 | 1637 | } |
b06947b5 | 1638 | } else { |
6f50eae7 | 1639 | radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector); |
f8d0edde AD |
1640 | if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) { |
1641 | ret = connector_status_connected; | |
1642 | if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) | |
1643 | radeon_dp_getdpcd(radeon_connector); | |
6f50eae7 | 1644 | } else { |
f8d0edde AD |
1645 | if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { |
1646 | if (radeon_dp_getdpcd(radeon_connector)) | |
1647 | ret = connector_status_connected; | |
1648 | } else { | |
d592fca9 | 1649 | /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ |
0a9069d3 | 1650 | if (radeon_ddc_probe(radeon_connector, false)) |
f8d0edde AD |
1651 | ret = connector_status_connected; |
1652 | } | |
4143e919 | 1653 | } |
746c1aa4 | 1654 | } |
4143e919 | 1655 | |
30f44372 | 1656 | radeon_connector_update_scratch_regs(connector, ret); |
10ebc0bc DA |
1657 | out: |
1658 | pm_runtime_mark_last_busy(connector->dev->dev); | |
1659 | pm_runtime_put_autosuspend(connector->dev->dev); | |
1660 | ||
746c1aa4 DA |
1661 | return ret; |
1662 | } | |
1663 | ||
5801ead6 AD |
1664 | static int radeon_dp_mode_valid(struct drm_connector *connector, |
1665 | struct drm_display_mode *mode) | |
1666 | { | |
6536a3a6 AD |
1667 | struct drm_device *dev = connector->dev; |
1668 | struct radeon_device *rdev = dev->dev_private; | |
5801ead6 AD |
1669 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1670 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; | |
1671 | ||
1672 | /* XXX check mode bandwidth */ | |
1673 | ||
f89931f3 AD |
1674 | if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || |
1675 | (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { | |
d291767b AD |
1676 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); |
1677 | ||
1678 | if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) | |
1679 | return MODE_PANEL; | |
1680 | ||
1681 | if (encoder) { | |
1682 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1683 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; | |
1684 | ||
f89931f3 | 1685 | /* AVIVO hardware supports downscaling modes larger than the panel |
d291767b AD |
1686 | * to the panel size, but I'm not sure this is desirable. |
1687 | */ | |
1688 | if ((mode->hdisplay > native_mode->hdisplay) || | |
1689 | (mode->vdisplay > native_mode->vdisplay)) | |
1690 | return MODE_PANEL; | |
1691 | ||
1692 | /* if scaling is disabled, block non-native modes */ | |
1693 | if (radeon_encoder->rmx_type == RMX_OFF) { | |
1694 | if ((mode->hdisplay != native_mode->hdisplay) || | |
1695 | (mode->vdisplay != native_mode->vdisplay)) | |
1696 | return MODE_PANEL; | |
1697 | } | |
1698 | } | |
d291767b AD |
1699 | } else { |
1700 | if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || | |
6536a3a6 | 1701 | (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { |
d291767b | 1702 | return radeon_dp_mode_valid_helper(connector, mode); |
6536a3a6 | 1703 | } else { |
377bd8a9 | 1704 | if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector_edid(connector))) { |
6536a3a6 AD |
1705 | /* HDMI 1.3+ supports max clock of 340 Mhz */ |
1706 | if (mode->clock > 340000) | |
1707 | return MODE_CLOCK_HIGH; | |
1708 | } else { | |
1709 | if (mode->clock > 165000) | |
1710 | return MODE_CLOCK_HIGH; | |
1711 | } | |
1712 | } | |
d291767b | 1713 | } |
6536a3a6 AD |
1714 | |
1715 | return MODE_OK; | |
5801ead6 AD |
1716 | } |
1717 | ||
1109ca09 | 1718 | static const struct drm_connector_helper_funcs radeon_dp_connector_helper_funcs = { |
746c1aa4 | 1719 | .get_modes = radeon_dp_get_modes, |
5801ead6 | 1720 | .mode_valid = radeon_dp_mode_valid, |
746c1aa4 DA |
1721 | .best_encoder = radeon_dvi_encoder, |
1722 | }; | |
1723 | ||
1109ca09 | 1724 | static const struct drm_connector_funcs radeon_dp_connector_funcs = { |
746c1aa4 DA |
1725 | .dpms = drm_helper_connector_dpms, |
1726 | .detect = radeon_dp_detect, | |
1727 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1728 | .set_property = radeon_connector_set_property, | |
379dfc25 | 1729 | .destroy = radeon_connector_destroy, |
746c1aa4 DA |
1730 | .force = radeon_dvi_force, |
1731 | }; | |
1732 | ||
855f5f1d AD |
1733 | static const struct drm_connector_funcs radeon_edp_connector_funcs = { |
1734 | .dpms = drm_helper_connector_dpms, | |
1735 | .detect = radeon_dp_detect, | |
1736 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1737 | .set_property = radeon_lvds_set_property, | |
379dfc25 | 1738 | .destroy = radeon_connector_destroy, |
855f5f1d AD |
1739 | .force = radeon_dvi_force, |
1740 | }; | |
1741 | ||
1742 | static const struct drm_connector_funcs radeon_lvds_bridge_connector_funcs = { | |
1743 | .dpms = drm_helper_connector_dpms, | |
1744 | .detect = radeon_dp_detect, | |
1745 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1746 | .set_property = radeon_lvds_set_property, | |
379dfc25 | 1747 | .destroy = radeon_connector_destroy, |
855f5f1d AD |
1748 | .force = radeon_dvi_force, |
1749 | }; | |
1750 | ||
771fe6b9 JG |
1751 | void |
1752 | radeon_add_atom_connector(struct drm_device *dev, | |
1753 | uint32_t connector_id, | |
1754 | uint32_t supported_device, | |
1755 | int connector_type, | |
1756 | struct radeon_i2c_bus_rec *i2c_bus, | |
b75fad06 | 1757 | uint32_t igp_lane_info, |
eed45b30 | 1758 | uint16_t connector_object_id, |
26b5bc98 AD |
1759 | struct radeon_hpd *hpd, |
1760 | struct radeon_router *router) | |
771fe6b9 | 1761 | { |
445282db | 1762 | struct radeon_device *rdev = dev->dev_private; |
771fe6b9 JG |
1763 | struct drm_connector *connector; |
1764 | struct radeon_connector *radeon_connector; | |
1765 | struct radeon_connector_atom_dig *radeon_dig_connector; | |
eac4dff6 AD |
1766 | struct drm_encoder *encoder; |
1767 | struct radeon_encoder *radeon_encoder; | |
771fe6b9 | 1768 | uint32_t subpixel_order = SubPixelNone; |
0294cf4f | 1769 | bool shared_ddc = false; |
eac4dff6 | 1770 | bool is_dp_bridge = false; |
496263bf | 1771 | bool has_aux = false; |
771fe6b9 | 1772 | |
4ce001ab | 1773 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) |
771fe6b9 JG |
1774 | return; |
1775 | ||
cf4c12f9 AD |
1776 | /* if the user selected tv=0 don't try and add the connector */ |
1777 | if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) || | |
1778 | (connector_type == DRM_MODE_CONNECTOR_Composite) || | |
1779 | (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) && | |
1780 | (radeon_tv == 0)) | |
1781 | return; | |
1782 | ||
771fe6b9 JG |
1783 | /* see if we already added it */ |
1784 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1785 | radeon_connector = to_radeon_connector(connector); | |
1786 | if (radeon_connector->connector_id == connector_id) { | |
1787 | radeon_connector->devices |= supported_device; | |
1788 | return; | |
1789 | } | |
0294cf4f | 1790 | if (radeon_connector->ddc_bus && i2c_bus->valid) { |
d3932d6c | 1791 | if (radeon_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { |
0294cf4f AD |
1792 | radeon_connector->shared_ddc = true; |
1793 | shared_ddc = true; | |
1794 | } | |
fb939dfc | 1795 | if (radeon_connector->router_bus && router->ddc_valid && |
26b5bc98 AD |
1796 | (radeon_connector->router.router_id == router->router_id)) { |
1797 | radeon_connector->shared_ddc = false; | |
1798 | shared_ddc = false; | |
1799 | } | |
0294cf4f | 1800 | } |
771fe6b9 JG |
1801 | } |
1802 | ||
eac4dff6 AD |
1803 | /* check if it's a dp bridge */ |
1804 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1805 | radeon_encoder = to_radeon_encoder(encoder); | |
1806 | if (radeon_encoder->devices & supported_device) { | |
1807 | switch (radeon_encoder->encoder_id) { | |
1808 | case ENCODER_OBJECT_ID_TRAVIS: | |
1809 | case ENCODER_OBJECT_ID_NUTMEG: | |
1810 | is_dp_bridge = true; | |
1811 | break; | |
1812 | default: | |
1813 | break; | |
1814 | } | |
1815 | } | |
1816 | } | |
1817 | ||
771fe6b9 JG |
1818 | radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL); |
1819 | if (!radeon_connector) | |
1820 | return; | |
1821 | ||
1822 | connector = &radeon_connector->base; | |
1823 | ||
1824 | radeon_connector->connector_id = connector_id; | |
1825 | radeon_connector->devices = supported_device; | |
0294cf4f | 1826 | radeon_connector->shared_ddc = shared_ddc; |
b75fad06 | 1827 | radeon_connector->connector_object_id = connector_object_id; |
eed45b30 | 1828 | radeon_connector->hpd = *hpd; |
bc1c4dc3 | 1829 | |
26b5bc98 | 1830 | radeon_connector->router = *router; |
fb939dfc | 1831 | if (router->ddc_valid || router->cd_valid) { |
26b5bc98 AD |
1832 | radeon_connector->router_bus = radeon_i2c_lookup(rdev, &router->i2c_info); |
1833 | if (!radeon_connector->router_bus) | |
a70882aa | 1834 | DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); |
26b5bc98 | 1835 | } |
eac4dff6 AD |
1836 | |
1837 | if (is_dp_bridge) { | |
771fe6b9 JG |
1838 | radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); |
1839 | if (!radeon_dig_connector) | |
1840 | goto failed; | |
771fe6b9 JG |
1841 | radeon_dig_connector->igp_lane_info = igp_lane_info; |
1842 | radeon_connector->con_priv = radeon_dig_connector; | |
771fe6b9 | 1843 | if (i2c_bus->valid) { |
379dfc25 AD |
1844 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); |
1845 | if (radeon_connector->ddc_bus) | |
496263bf AD |
1846 | has_aux = true; |
1847 | else | |
eac4dff6 | 1848 | DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); |
771fe6b9 | 1849 | } |
eac4dff6 AD |
1850 | switch (connector_type) { |
1851 | case DRM_MODE_CONNECTOR_VGA: | |
1852 | case DRM_MODE_CONNECTOR_DVIA: | |
1853 | default: | |
855f5f1d AD |
1854 | drm_connector_init(dev, &radeon_connector->base, |
1855 | &radeon_dp_connector_funcs, connector_type); | |
1856 | drm_connector_helper_add(&radeon_connector->base, | |
1857 | &radeon_dp_connector_helper_funcs); | |
eac4dff6 AD |
1858 | connector->interlace_allowed = true; |
1859 | connector->doublescan_allowed = true; | |
d629a3ce | 1860 | radeon_connector->dac_load_detect = true; |
e35755fa | 1861 | drm_object_attach_property(&radeon_connector->base.base, |
d629a3ce AD |
1862 | rdev->mode_info.load_detect_property, |
1863 | 1); | |
da997620 AD |
1864 | drm_object_attach_property(&radeon_connector->base.base, |
1865 | dev->mode_config.scaling_mode_property, | |
1866 | DRM_MODE_SCALE_NONE); | |
eac4dff6 AD |
1867 | break; |
1868 | case DRM_MODE_CONNECTOR_DVII: | |
1869 | case DRM_MODE_CONNECTOR_DVID: | |
1870 | case DRM_MODE_CONNECTOR_HDMIA: | |
1871 | case DRM_MODE_CONNECTOR_HDMIB: | |
1872 | case DRM_MODE_CONNECTOR_DisplayPort: | |
855f5f1d AD |
1873 | drm_connector_init(dev, &radeon_connector->base, |
1874 | &radeon_dp_connector_funcs, connector_type); | |
1875 | drm_connector_helper_add(&radeon_connector->base, | |
1876 | &radeon_dp_connector_helper_funcs); | |
e35755fa | 1877 | drm_object_attach_property(&radeon_connector->base.base, |
430f70d5 | 1878 | rdev->mode_info.underscan_property, |
56bec7c0 | 1879 | UNDERSCAN_OFF); |
e35755fa | 1880 | drm_object_attach_property(&radeon_connector->base.base, |
5bccf5e3 MG |
1881 | rdev->mode_info.underscan_hborder_property, |
1882 | 0); | |
e35755fa | 1883 | drm_object_attach_property(&radeon_connector->base.base, |
5bccf5e3 MG |
1884 | rdev->mode_info.underscan_vborder_property, |
1885 | 0); | |
91915260 | 1886 | |
da997620 AD |
1887 | drm_object_attach_property(&radeon_connector->base.base, |
1888 | dev->mode_config.scaling_mode_property, | |
1889 | DRM_MODE_SCALE_NONE); | |
1890 | ||
6214bb74 AD |
1891 | drm_object_attach_property(&radeon_connector->base.base, |
1892 | rdev->mode_info.dither_property, | |
1893 | RADEON_FMT_DITHER_DISABLE); | |
91915260 | 1894 | |
108dc8e8 AD |
1895 | if (radeon_audio != 0) |
1896 | drm_object_attach_property(&radeon_connector->base.base, | |
1897 | rdev->mode_info.audio_property, | |
e31fadd3 | 1898 | RADEON_AUDIO_AUTO); |
91915260 | 1899 | |
eac4dff6 AD |
1900 | subpixel_order = SubPixelHorizontalRGB; |
1901 | connector->interlace_allowed = true; | |
1902 | if (connector_type == DRM_MODE_CONNECTOR_HDMIB) | |
1903 | connector->doublescan_allowed = true; | |
1904 | else | |
1905 | connector->doublescan_allowed = false; | |
d629a3ce AD |
1906 | if (connector_type == DRM_MODE_CONNECTOR_DVII) { |
1907 | radeon_connector->dac_load_detect = true; | |
e35755fa | 1908 | drm_object_attach_property(&radeon_connector->base.base, |
d629a3ce AD |
1909 | rdev->mode_info.load_detect_property, |
1910 | 1); | |
1911 | } | |
eac4dff6 AD |
1912 | break; |
1913 | case DRM_MODE_CONNECTOR_LVDS: | |
1914 | case DRM_MODE_CONNECTOR_eDP: | |
855f5f1d AD |
1915 | drm_connector_init(dev, &radeon_connector->base, |
1916 | &radeon_lvds_bridge_connector_funcs, connector_type); | |
1917 | drm_connector_helper_add(&radeon_connector->base, | |
1918 | &radeon_dp_connector_helper_funcs); | |
e35755fa | 1919 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
1920 | dev->mode_config.scaling_mode_property, |
1921 | DRM_MODE_SCALE_FULLSCREEN); | |
1922 | subpixel_order = SubPixelHorizontalRGB; | |
1923 | connector->interlace_allowed = false; | |
1924 | connector->doublescan_allowed = false; | |
1925 | break; | |
5bccf5e3 | 1926 | } |
eac4dff6 AD |
1927 | } else { |
1928 | switch (connector_type) { | |
1929 | case DRM_MODE_CONNECTOR_VGA: | |
1930 | drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); | |
1931 | drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); | |
1932 | if (i2c_bus->valid) { | |
1933 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); | |
1934 | if (!radeon_connector->ddc_bus) | |
1935 | DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); | |
1936 | } | |
390d0bbe | 1937 | radeon_connector->dac_load_detect = true; |
e35755fa | 1938 | drm_object_attach_property(&radeon_connector->base.base, |
390d0bbe AD |
1939 | rdev->mode_info.load_detect_property, |
1940 | 1); | |
da997620 AD |
1941 | if (ASIC_IS_AVIVO(rdev)) |
1942 | drm_object_attach_property(&radeon_connector->base.base, | |
1943 | dev->mode_config.scaling_mode_property, | |
1944 | DRM_MODE_SCALE_NONE); | |
eac4dff6 AD |
1945 | /* no HPD on analog connectors */ |
1946 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | |
1947 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
1948 | connector->interlace_allowed = true; | |
c49948f4 | 1949 | connector->doublescan_allowed = true; |
eac4dff6 AD |
1950 | break; |
1951 | case DRM_MODE_CONNECTOR_DVIA: | |
1952 | drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); | |
1953 | drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); | |
1954 | if (i2c_bus->valid) { | |
1955 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); | |
1956 | if (!radeon_connector->ddc_bus) | |
1957 | DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); | |
1958 | } | |
1959 | radeon_connector->dac_load_detect = true; | |
e35755fa | 1960 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
1961 | rdev->mode_info.load_detect_property, |
1962 | 1); | |
da997620 AD |
1963 | if (ASIC_IS_AVIVO(rdev)) |
1964 | drm_object_attach_property(&radeon_connector->base.base, | |
1965 | dev->mode_config.scaling_mode_property, | |
1966 | DRM_MODE_SCALE_NONE); | |
eac4dff6 AD |
1967 | /* no HPD on analog connectors */ |
1968 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | |
1969 | connector->interlace_allowed = true; | |
1970 | connector->doublescan_allowed = true; | |
1971 | break; | |
1972 | case DRM_MODE_CONNECTOR_DVII: | |
1973 | case DRM_MODE_CONNECTOR_DVID: | |
1974 | radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); | |
1975 | if (!radeon_dig_connector) | |
1976 | goto failed; | |
1977 | radeon_dig_connector->igp_lane_info = igp_lane_info; | |
1978 | radeon_connector->con_priv = radeon_dig_connector; | |
1979 | drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); | |
1980 | drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); | |
1981 | if (i2c_bus->valid) { | |
1982 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); | |
1983 | if (!radeon_connector->ddc_bus) | |
1984 | DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); | |
1985 | } | |
1986 | subpixel_order = SubPixelHorizontalRGB; | |
e35755fa | 1987 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
1988 | rdev->mode_info.coherent_mode_property, |
1989 | 1); | |
1990 | if (ASIC_IS_AVIVO(rdev)) { | |
e35755fa | 1991 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
1992 | rdev->mode_info.underscan_property, |
1993 | UNDERSCAN_OFF); | |
e35755fa | 1994 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
1995 | rdev->mode_info.underscan_hborder_property, |
1996 | 0); | |
e35755fa | 1997 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
1998 | rdev->mode_info.underscan_vborder_property, |
1999 | 0); | |
da997620 AD |
2000 | drm_object_attach_property(&radeon_connector->base.base, |
2001 | rdev->mode_info.dither_property, | |
2002 | RADEON_FMT_DITHER_DISABLE); | |
2003 | drm_object_attach_property(&radeon_connector->base.base, | |
2004 | dev->mode_config.scaling_mode_property, | |
2005 | DRM_MODE_SCALE_NONE); | |
eac4dff6 | 2006 | } |
108dc8e8 | 2007 | if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) { |
8666c076 | 2008 | drm_object_attach_property(&radeon_connector->base.base, |
108dc8e8 | 2009 | rdev->mode_info.audio_property, |
e31fadd3 | 2010 | RADEON_AUDIO_AUTO); |
8666c076 | 2011 | } |
eac4dff6 AD |
2012 | if (connector_type == DRM_MODE_CONNECTOR_DVII) { |
2013 | radeon_connector->dac_load_detect = true; | |
e35755fa | 2014 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2015 | rdev->mode_info.load_detect_property, |
2016 | 1); | |
2017 | } | |
2018 | connector->interlace_allowed = true; | |
2019 | if (connector_type == DRM_MODE_CONNECTOR_DVII) | |
2020 | connector->doublescan_allowed = true; | |
2021 | else | |
2022 | connector->doublescan_allowed = false; | |
2023 | break; | |
2024 | case DRM_MODE_CONNECTOR_HDMIA: | |
2025 | case DRM_MODE_CONNECTOR_HDMIB: | |
2026 | radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); | |
2027 | if (!radeon_dig_connector) | |
2028 | goto failed; | |
2029 | radeon_dig_connector->igp_lane_info = igp_lane_info; | |
2030 | radeon_connector->con_priv = radeon_dig_connector; | |
2031 | drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); | |
2032 | drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); | |
2033 | if (i2c_bus->valid) { | |
2034 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); | |
2035 | if (!radeon_connector->ddc_bus) | |
2036 | DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); | |
2037 | } | |
e35755fa | 2038 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2039 | rdev->mode_info.coherent_mode_property, |
2040 | 1); | |
2041 | if (ASIC_IS_AVIVO(rdev)) { | |
e35755fa | 2042 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2043 | rdev->mode_info.underscan_property, |
2044 | UNDERSCAN_OFF); | |
e35755fa | 2045 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2046 | rdev->mode_info.underscan_hborder_property, |
2047 | 0); | |
e35755fa | 2048 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2049 | rdev->mode_info.underscan_vborder_property, |
2050 | 0); | |
da997620 AD |
2051 | drm_object_attach_property(&radeon_connector->base.base, |
2052 | rdev->mode_info.dither_property, | |
2053 | RADEON_FMT_DITHER_DISABLE); | |
2054 | drm_object_attach_property(&radeon_connector->base.base, | |
2055 | dev->mode_config.scaling_mode_property, | |
2056 | DRM_MODE_SCALE_NONE); | |
eac4dff6 | 2057 | } |
108dc8e8 | 2058 | if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) { |
8666c076 | 2059 | drm_object_attach_property(&radeon_connector->base.base, |
108dc8e8 | 2060 | rdev->mode_info.audio_property, |
e31fadd3 | 2061 | RADEON_AUDIO_AUTO); |
8666c076 | 2062 | } |
eac4dff6 AD |
2063 | subpixel_order = SubPixelHorizontalRGB; |
2064 | connector->interlace_allowed = true; | |
2065 | if (connector_type == DRM_MODE_CONNECTOR_HDMIB) | |
2066 | connector->doublescan_allowed = true; | |
2067 | else | |
2068 | connector->doublescan_allowed = false; | |
2069 | break; | |
2070 | case DRM_MODE_CONNECTOR_DisplayPort: | |
2071 | radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); | |
2072 | if (!radeon_dig_connector) | |
2073 | goto failed; | |
2074 | radeon_dig_connector->igp_lane_info = igp_lane_info; | |
2075 | radeon_connector->con_priv = radeon_dig_connector; | |
2076 | drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type); | |
2077 | drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs); | |
2078 | if (i2c_bus->valid) { | |
eac4dff6 | 2079 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); |
496263bf AD |
2080 | if (radeon_connector->ddc_bus) |
2081 | has_aux = true; | |
2082 | else | |
eac4dff6 AD |
2083 | DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); |
2084 | } | |
2085 | subpixel_order = SubPixelHorizontalRGB; | |
e35755fa | 2086 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2087 | rdev->mode_info.coherent_mode_property, |
2088 | 1); | |
2089 | if (ASIC_IS_AVIVO(rdev)) { | |
e35755fa | 2090 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2091 | rdev->mode_info.underscan_property, |
2092 | UNDERSCAN_OFF); | |
e35755fa | 2093 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2094 | rdev->mode_info.underscan_hborder_property, |
2095 | 0); | |
e35755fa | 2096 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2097 | rdev->mode_info.underscan_vborder_property, |
2098 | 0); | |
da997620 AD |
2099 | drm_object_attach_property(&radeon_connector->base.base, |
2100 | rdev->mode_info.dither_property, | |
2101 | RADEON_FMT_DITHER_DISABLE); | |
2102 | drm_object_attach_property(&radeon_connector->base.base, | |
2103 | dev->mode_config.scaling_mode_property, | |
2104 | DRM_MODE_SCALE_NONE); | |
eac4dff6 | 2105 | } |
108dc8e8 | 2106 | if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) { |
8666c076 | 2107 | drm_object_attach_property(&radeon_connector->base.base, |
108dc8e8 | 2108 | rdev->mode_info.audio_property, |
e31fadd3 | 2109 | RADEON_AUDIO_AUTO); |
8666c076 | 2110 | } |
eac4dff6 AD |
2111 | connector->interlace_allowed = true; |
2112 | /* in theory with a DP to VGA converter... */ | |
c49948f4 | 2113 | connector->doublescan_allowed = false; |
eac4dff6 AD |
2114 | break; |
2115 | case DRM_MODE_CONNECTOR_eDP: | |
2116 | radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); | |
2117 | if (!radeon_dig_connector) | |
2118 | goto failed; | |
2119 | radeon_dig_connector->igp_lane_info = igp_lane_info; | |
2120 | radeon_connector->con_priv = radeon_dig_connector; | |
855f5f1d | 2121 | drm_connector_init(dev, &radeon_connector->base, &radeon_edp_connector_funcs, connector_type); |
eac4dff6 AD |
2122 | drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs); |
2123 | if (i2c_bus->valid) { | |
379dfc25 AD |
2124 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); |
2125 | if (radeon_connector->ddc_bus) | |
496263bf AD |
2126 | has_aux = true; |
2127 | else | |
eac4dff6 AD |
2128 | DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); |
2129 | } | |
e35755fa | 2130 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2131 | dev->mode_config.scaling_mode_property, |
2132 | DRM_MODE_SCALE_FULLSCREEN); | |
2133 | subpixel_order = SubPixelHorizontalRGB; | |
2134 | connector->interlace_allowed = false; | |
2135 | connector->doublescan_allowed = false; | |
2136 | break; | |
2137 | case DRM_MODE_CONNECTOR_SVIDEO: | |
2138 | case DRM_MODE_CONNECTOR_Composite: | |
2139 | case DRM_MODE_CONNECTOR_9PinDIN: | |
2140 | drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); | |
2141 | drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); | |
2142 | radeon_connector->dac_load_detect = true; | |
e35755fa | 2143 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2144 | rdev->mode_info.load_detect_property, |
2145 | 1); | |
e35755fa | 2146 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2147 | rdev->mode_info.tv_std_property, |
2148 | radeon_atombios_get_tv_info(rdev)); | |
2149 | /* no HPD on analog connectors */ | |
2150 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | |
2151 | connector->interlace_allowed = false; | |
2152 | connector->doublescan_allowed = false; | |
2153 | break; | |
2154 | case DRM_MODE_CONNECTOR_LVDS: | |
2155 | radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); | |
2156 | if (!radeon_dig_connector) | |
2157 | goto failed; | |
2158 | radeon_dig_connector->igp_lane_info = igp_lane_info; | |
2159 | radeon_connector->con_priv = radeon_dig_connector; | |
2160 | drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); | |
2161 | drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); | |
2162 | if (i2c_bus->valid) { | |
2163 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); | |
2164 | if (!radeon_connector->ddc_bus) | |
2165 | DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); | |
2166 | } | |
e35755fa | 2167 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2168 | dev->mode_config.scaling_mode_property, |
2169 | DRM_MODE_SCALE_FULLSCREEN); | |
2170 | subpixel_order = SubPixelHorizontalRGB; | |
2171 | connector->interlace_allowed = false; | |
2172 | connector->doublescan_allowed = false; | |
2173 | break; | |
771fe6b9 | 2174 | } |
771fe6b9 JG |
2175 | } |
2176 | ||
2581afcc | 2177 | if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) { |
eb1f8e4f DA |
2178 | if (i2c_bus->valid) |
2179 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
2180 | } else | |
2181 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
2182 | ||
771fe6b9 | 2183 | connector->display_info.subpixel_order = subpixel_order; |
34ea3d38 | 2184 | drm_connector_register(connector); |
496263bf AD |
2185 | |
2186 | if (has_aux) | |
2187 | radeon_dp_aux_init(radeon_connector); | |
2188 | ||
771fe6b9 JG |
2189 | return; |
2190 | ||
2191 | failed: | |
771fe6b9 JG |
2192 | drm_connector_cleanup(connector); |
2193 | kfree(connector); | |
2194 | } | |
2195 | ||
2196 | void | |
2197 | radeon_add_legacy_connector(struct drm_device *dev, | |
2198 | uint32_t connector_id, | |
2199 | uint32_t supported_device, | |
2200 | int connector_type, | |
b75fad06 | 2201 | struct radeon_i2c_bus_rec *i2c_bus, |
eed45b30 AD |
2202 | uint16_t connector_object_id, |
2203 | struct radeon_hpd *hpd) | |
771fe6b9 | 2204 | { |
445282db | 2205 | struct radeon_device *rdev = dev->dev_private; |
771fe6b9 JG |
2206 | struct drm_connector *connector; |
2207 | struct radeon_connector *radeon_connector; | |
2208 | uint32_t subpixel_order = SubPixelNone; | |
2209 | ||
4ce001ab | 2210 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) |
771fe6b9 JG |
2211 | return; |
2212 | ||
cf4c12f9 AD |
2213 | /* if the user selected tv=0 don't try and add the connector */ |
2214 | if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) || | |
2215 | (connector_type == DRM_MODE_CONNECTOR_Composite) || | |
2216 | (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) && | |
2217 | (radeon_tv == 0)) | |
2218 | return; | |
2219 | ||
771fe6b9 JG |
2220 | /* see if we already added it */ |
2221 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2222 | radeon_connector = to_radeon_connector(connector); | |
2223 | if (radeon_connector->connector_id == connector_id) { | |
2224 | radeon_connector->devices |= supported_device; | |
2225 | return; | |
2226 | } | |
2227 | } | |
2228 | ||
2229 | radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL); | |
2230 | if (!radeon_connector) | |
2231 | return; | |
2232 | ||
2233 | connector = &radeon_connector->base; | |
2234 | ||
2235 | radeon_connector->connector_id = connector_id; | |
2236 | radeon_connector->devices = supported_device; | |
b75fad06 | 2237 | radeon_connector->connector_object_id = connector_object_id; |
eed45b30 | 2238 | radeon_connector->hpd = *hpd; |
bc1c4dc3 | 2239 | |
771fe6b9 JG |
2240 | switch (connector_type) { |
2241 | case DRM_MODE_CONNECTOR_VGA: | |
2242 | drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); | |
0b4c0f3f | 2243 | drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); |
771fe6b9 | 2244 | if (i2c_bus->valid) { |
f376b94f | 2245 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); |
771fe6b9 | 2246 | if (!radeon_connector->ddc_bus) |
a70882aa | 2247 | DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); |
771fe6b9 | 2248 | } |
35e4b7af | 2249 | radeon_connector->dac_load_detect = true; |
e35755fa | 2250 | drm_object_attach_property(&radeon_connector->base.base, |
445282db DA |
2251 | rdev->mode_info.load_detect_property, |
2252 | 1); | |
2581afcc AD |
2253 | /* no HPD on analog connectors */ |
2254 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | |
eb1f8e4f | 2255 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
c49948f4 AD |
2256 | connector->interlace_allowed = true; |
2257 | connector->doublescan_allowed = true; | |
771fe6b9 JG |
2258 | break; |
2259 | case DRM_MODE_CONNECTOR_DVIA: | |
2260 | drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); | |
0b4c0f3f | 2261 | drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); |
771fe6b9 | 2262 | if (i2c_bus->valid) { |
f376b94f | 2263 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); |
771fe6b9 | 2264 | if (!radeon_connector->ddc_bus) |
a70882aa | 2265 | DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); |
771fe6b9 | 2266 | } |
35e4b7af | 2267 | radeon_connector->dac_load_detect = true; |
e35755fa | 2268 | drm_object_attach_property(&radeon_connector->base.base, |
445282db DA |
2269 | rdev->mode_info.load_detect_property, |
2270 | 1); | |
2581afcc AD |
2271 | /* no HPD on analog connectors */ |
2272 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | |
c49948f4 AD |
2273 | connector->interlace_allowed = true; |
2274 | connector->doublescan_allowed = true; | |
771fe6b9 JG |
2275 | break; |
2276 | case DRM_MODE_CONNECTOR_DVII: | |
2277 | case DRM_MODE_CONNECTOR_DVID: | |
2278 | drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); | |
0b4c0f3f | 2279 | drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); |
771fe6b9 | 2280 | if (i2c_bus->valid) { |
f376b94f | 2281 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); |
771fe6b9 | 2282 | if (!radeon_connector->ddc_bus) |
a70882aa | 2283 | DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); |
68b3adb4 AD |
2284 | } |
2285 | if (connector_type == DRM_MODE_CONNECTOR_DVII) { | |
35e4b7af | 2286 | radeon_connector->dac_load_detect = true; |
e35755fa | 2287 | drm_object_attach_property(&radeon_connector->base.base, |
445282db DA |
2288 | rdev->mode_info.load_detect_property, |
2289 | 1); | |
771fe6b9 JG |
2290 | } |
2291 | subpixel_order = SubPixelHorizontalRGB; | |
c49948f4 AD |
2292 | connector->interlace_allowed = true; |
2293 | if (connector_type == DRM_MODE_CONNECTOR_DVII) | |
2294 | connector->doublescan_allowed = true; | |
2295 | else | |
2296 | connector->doublescan_allowed = false; | |
771fe6b9 JG |
2297 | break; |
2298 | case DRM_MODE_CONNECTOR_SVIDEO: | |
2299 | case DRM_MODE_CONNECTOR_Composite: | |
2300 | case DRM_MODE_CONNECTOR_9PinDIN: | |
cf4c12f9 AD |
2301 | drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); |
2302 | drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); | |
2303 | radeon_connector->dac_load_detect = true; | |
2304 | /* RS400,RC410,RS480 chipset seems to report a lot | |
2305 | * of false positive on load detect, we haven't yet | |
2306 | * found a way to make load detect reliable on those | |
2307 | * chipset, thus just disable it for TV. | |
2308 | */ | |
2309 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) | |
2310 | radeon_connector->dac_load_detect = false; | |
e35755fa | 2311 | drm_object_attach_property(&radeon_connector->base.base, |
cf4c12f9 AD |
2312 | rdev->mode_info.load_detect_property, |
2313 | radeon_connector->dac_load_detect); | |
e35755fa | 2314 | drm_object_attach_property(&radeon_connector->base.base, |
cf4c12f9 AD |
2315 | rdev->mode_info.tv_std_property, |
2316 | radeon_combios_get_tv_info(rdev)); | |
2317 | /* no HPD on analog connectors */ | |
2318 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | |
c49948f4 AD |
2319 | connector->interlace_allowed = false; |
2320 | connector->doublescan_allowed = false; | |
771fe6b9 JG |
2321 | break; |
2322 | case DRM_MODE_CONNECTOR_LVDS: | |
2323 | drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); | |
0b4c0f3f | 2324 | drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); |
771fe6b9 | 2325 | if (i2c_bus->valid) { |
f376b94f | 2326 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); |
771fe6b9 | 2327 | if (!radeon_connector->ddc_bus) |
a70882aa | 2328 | DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); |
771fe6b9 | 2329 | } |
e35755fa | 2330 | drm_object_attach_property(&radeon_connector->base.base, |
445282db DA |
2331 | dev->mode_config.scaling_mode_property, |
2332 | DRM_MODE_SCALE_FULLSCREEN); | |
771fe6b9 | 2333 | subpixel_order = SubPixelHorizontalRGB; |
c49948f4 AD |
2334 | connector->interlace_allowed = false; |
2335 | connector->doublescan_allowed = false; | |
771fe6b9 JG |
2336 | break; |
2337 | } | |
2338 | ||
2581afcc | 2339 | if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) { |
eb1f8e4f DA |
2340 | if (i2c_bus->valid) |
2341 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
2342 | } else | |
2343 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
771fe6b9 | 2344 | connector->display_info.subpixel_order = subpixel_order; |
34ea3d38 | 2345 | drm_connector_register(connector); |
771fe6b9 | 2346 | } |