[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_cs.c

/*
 * Copyright 2008 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 */
#include "drmP.h"
#include "radeon_drm.h"
#include "radeon_reg.h"
#include "radeon.h"

void r100_cs_dump_packet(struct radeon_cs_parser *p,
			 struct radeon_cs_packet *pkt);

int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
{
	struct drm_device *ddev = p->rdev->ddev;
	struct radeon_cs_chunk *chunk;
	unsigned i, j;
	bool duplicate;

	if (p->chunk_relocs_idx == -1) {
		return 0;
	}
	chunk = &p->chunks[p->chunk_relocs_idx];
	/* FIXME: we assume that each relocs use 4 dwords */
	p->nrelocs = chunk->length_dw / 4;
	p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
	if (p->relocs_ptr == NULL) {
		return -ENOMEM;
	}
	p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
	if (p->relocs == NULL) {
		return -ENOMEM;
	}
	for (i = 0; i < p->nrelocs; i++) {
		struct drm_radeon_cs_reloc *r;

		duplicate = false;
		r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
		for (j = 0; j < i; j++) {
			if (r->handle == p->relocs[j].handle) {
				p->relocs_ptr[i] = &p->relocs[j];
				duplicate = true;
				break;
			}
		}
		if (!duplicate) {
			p->relocs[i].gobj = drm_gem_object_lookup(ddev,
								  p->filp,
								  r->handle);
			if (p->relocs[i].gobj == NULL) {
				DRM_ERROR("gem object lookup failed 0x%x\n",
					  r->handle);
				return -ENOENT;
			}
			p->relocs_ptr[i] = &p->relocs[i];
			p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
			p->relocs[i].lobj.bo = p->relocs[i].robj;
			p->relocs[i].lobj.wdomain = r->write_domain;
			p->relocs[i].lobj.rdomain = r->read_domains;
			p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
			p->relocs[i].handle = r->handle;
			p->relocs[i].flags = r->flags;
			radeon_bo_list_add_object(&p->relocs[i].lobj,
						  &p->validated);

		} else
			p->relocs[i].handle = 0;
	}
	return radeon_bo_list_validate(&p->validated);
}

static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
{
	p->priority = priority;

	switch (ring) {
	default:
		DRM_ERROR("unknown ring id: %d\n", ring);
		return -EINVAL;
	case RADEON_CS_RING_GFX:
		p->ring = RADEON_RING_TYPE_GFX_INDEX;
		break;
	case RADEON_CS_RING_COMPUTE:
		/* for now */
		p->ring = RADEON_RING_TYPE_GFX_INDEX;
		break;
	}
	return 0;
}

static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
{
	bool sync_to_ring[RADEON_NUM_RINGS] = { };
	int i, r;

	for (i = 0; i < p->nrelocs; i++) {
		if (!p->relocs[i].robj || !p->relocs[i].robj->tbo.sync_obj)
			continue;

		if (!(p->relocs[i].flags & RADEON_RELOC_DONT_SYNC)) {
			struct radeon_fence *fence = p->relocs[i].robj->tbo.sync_obj;
			if (!radeon_fence_signaled(fence)) {
				sync_to_ring[fence->ring] = true;
			}
		}
	}

	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
		/* no need to sync to our own or unused rings */
		if (i == p->ring || !sync_to_ring[i] || !p->rdev->ring[i].ready)
			continue;

		if (!p->ib->fence->semaphore) {
			r = radeon_semaphore_create(p->rdev, &p->ib->fence->semaphore);
			if (r)
				return r;
		}

		r = radeon_ring_lock(p->rdev, &p->rdev->ring[i], 3);
		if (r)
			return r;
		radeon_semaphore_emit_signal(p->rdev, i, p->ib->fence->semaphore);
		radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[i]);

		r = radeon_ring_lock(p->rdev, &p->rdev->ring[p->ring], 3);
		if (r)
			return r;
		radeon_semaphore_emit_wait(p->rdev, p->ring, p->ib->fence->semaphore);
		radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[p->ring]);
	}
	return 0;
}

int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
{
	struct drm_radeon_cs *cs = data;
	uint64_t *chunk_array_ptr;
	unsigned size, i;
	u32 ring = RADEON_CS_RING_GFX;
	s32 priority = 0;

	if (!cs->num_chunks) {
		return 0;
	}
	/* get chunks */
	INIT_LIST_HEAD(&p->validated);
	p->idx = 0;
	p->chunk_ib_idx = -1;
	p->chunk_relocs_idx = -1;
	p->chunk_flags_idx = -1;
	p->chunk_const_ib_idx = -1;
	p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
	if (p->chunks_array == NULL) {
		return -ENOMEM;
	}
	chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
	if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
			       sizeof(uint64_t)*cs->num_chunks)) {
		return -EFAULT;
	}
	p->cs_flags = 0;
	p->nchunks = cs->num_chunks;
	p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
	if (p->chunks == NULL) {
		return -ENOMEM;
	}
	for (i = 0; i < p->nchunks; i++) {
		struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
		struct drm_radeon_cs_chunk user_chunk;
		uint32_t __user *cdata;

		chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
		if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
				       sizeof(struct drm_radeon_cs_chunk))) {
			return -EFAULT;
		}
		p->chunks[i].length_dw = user_chunk.length_dw;
		p->chunks[i].kdata = NULL;
		p->chunks[i].chunk_id = user_chunk.chunk_id;

		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
			p->chunk_relocs_idx = i;
		}
		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
			p->chunk_ib_idx = i;
			/* zero length IB isn't useful */
			if (p->chunks[i].length_dw == 0)
				return -EINVAL;
		}
		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
			p->chunk_const_ib_idx = i;
			/* zero length CONST IB isn't useful */
			if (p->chunks[i].length_dw == 0)
				return -EINVAL;
		}
		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
			p->chunk_flags_idx = i;
			/* zero length flags aren't useful */
			if (p->chunks[i].length_dw == 0)
				return -EINVAL;
		}

		p->chunks[i].length_dw = user_chunk.length_dw;
		p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;

		cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
		if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
		    (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
			size = p->chunks[i].length_dw * sizeof(uint32_t);
			p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
			if (p->chunks[i].kdata == NULL) {
				return -ENOMEM;
			}
			if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
					       p->chunks[i].user_ptr, size)) {
				return -EFAULT;
			}
			if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
				p->cs_flags = p->chunks[i].kdata[0];
				if (p->chunks[i].length_dw > 1)
					ring = p->chunks[i].kdata[1];
				if (p->chunks[i].length_dw > 2)
					priority = (s32)p->chunks[i].kdata[2];
			}
		}
	}

	if ((p->cs_flags & RADEON_CS_USE_VM) &&
	    !p->rdev->vm_manager.enabled) {
		DRM_ERROR("VM not active on asic!\n");
		return -EINVAL;
	}

	/* we only support VM on SI+ */
	if ((p->rdev->family >= CHIP_TAHITI) &&
	    ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
		DRM_ERROR("VM required on SI+!\n");
		return -EINVAL;
	}

	if (radeon_cs_get_ring(p, ring, priority))
		return -EINVAL;


	/* deal with non-vm */
	if ((p->chunk_ib_idx != -1) &&
	    ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
	    (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
		if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
			DRM_ERROR("cs IB too big: %d\n",
				  p->chunks[p->chunk_ib_idx].length_dw);
			return -EINVAL;
		}
		p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
		p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
		if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
		    p->chunks[p->chunk_ib_idx].kpage[1] == NULL)
			return -ENOMEM;
		p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
		p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
		p->chunks[p->chunk_ib_idx].last_copied_page = -1;
		p->chunks[p->chunk_ib_idx].last_page_index =
			((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
	}

	return 0;
}

/**
 * cs_parser_fini() - clean parser states
 * @parser:	parser structure holding parsing context.
 * @error:	error number
 *
 * If error is set than unvalidate buffer, otherwise just free memory
 * used by parsing context.
 **/
static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
{
	unsigned i;


	if (!error && parser->ib)
		ttm_eu_fence_buffer_objects(&parser->validated,
					    parser->ib->fence);
	else
		ttm_eu_backoff_reservation(&parser->validated);

	if (parser->relocs != NULL) {
		for (i = 0; i < parser->nrelocs; i++) {
			if (parser->relocs[i].gobj)
				drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
		}
	}
	kfree(parser->track);
	kfree(parser->relocs);
	kfree(parser->relocs_ptr);
	for (i = 0; i < parser->nchunks; i++) {
		kfree(parser->chunks[i].kdata);
		kfree(parser->chunks[i].kpage[0]);
		kfree(parser->chunks[i].kpage[1]);
	}
	kfree(parser->chunks);
	kfree(parser->chunks_array);
	radeon_ib_free(parser->rdev, &parser->ib);
}

static int radeon_cs_ib_chunk(struct radeon_device *rdev,
			      struct radeon_cs_parser *parser)
{
	struct radeon_cs_chunk *ib_chunk;
	int r;

	if (parser->chunk_ib_idx == -1)
		return 0;

	if (parser->cs_flags & RADEON_CS_USE_VM)
		return 0;

	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	/* Copy the packet into the IB, the parser will read from the
	 * input memory (cached) and write to the IB (which can be
	 * uncached).
	 */
	r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
			   ib_chunk->length_dw * 4);
	if (r) {
		DRM_ERROR("Failed to get ib !\n");
		return r;
	}
	parser->ib->length_dw = ib_chunk->length_dw;
	r = radeon_cs_parse(rdev, parser->ring, parser);
	if (r || parser->parser_error) {
		DRM_ERROR("Invalid command stream !\n");
		return r;
	}
	r = radeon_cs_finish_pages(parser);
	if (r) {
		DRM_ERROR("Invalid command stream !\n");
		return r;
	}
	r = radeon_cs_sync_rings(parser);
	if (r) {
		DRM_ERROR("Failed to synchronize rings !\n");
	}
	parser->ib->vm_id = 0;
	r = radeon_ib_schedule(rdev, parser->ib);
	if (r) {
		DRM_ERROR("Failed to schedule IB !\n");
	}
	return 0;
}

static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
				   struct radeon_vm *vm)
{
	struct radeon_bo_list *lobj;
	struct radeon_bo *bo;
	int r;

	list_for_each_entry(lobj, &parser->validated, tv.head) {
		bo = lobj->bo;
		r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
		if (r) {
			return r;
		}
	}
	return 0;
}

static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
				 struct radeon_cs_parser *parser)
{
	struct radeon_cs_chunk *ib_chunk;
	struct radeon_fpriv *fpriv = parser->filp->driver_priv;
	struct radeon_vm *vm = &fpriv->vm;
	int r;

	if (parser->chunk_ib_idx == -1)
		return 0;

	if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
		return 0;

	if ((rdev->family >= CHIP_TAHITI) &&
	    (parser->chunk_const_ib_idx != -1)) {
		ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
		if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
			DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
			return -EINVAL;
		}
		r =  radeon_ib_get(rdev, parser->ring, &parser->const_ib,
				   ib_chunk->length_dw * 4);
		if (r) {
			DRM_ERROR("Failed to get const ib !\n");
			return r;
		}
		parser->const_ib->is_const_ib = true;
		parser->const_ib->length_dw = ib_chunk->length_dw;
		/* Copy the packet into the IB */
		if (DRM_COPY_FROM_USER(parser->const_ib->ptr, ib_chunk->user_ptr,
				       ib_chunk->length_dw * 4)) {
			return -EFAULT;
		}
		r = radeon_ring_ib_parse(rdev, parser->ring, parser->const_ib);
		if (r) {
			return r;
		}
	}

	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
		DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
		return -EINVAL;
	}
	r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
			   ib_chunk->length_dw * 4);
	if (r) {
		DRM_ERROR("Failed to get ib !\n");
		return r;
	}
	parser->ib->length_dw = ib_chunk->length_dw;
	/* Copy the packet into the IB */
	if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr,
			       ib_chunk->length_dw * 4)) {
		return -EFAULT;
	}
	r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib);
	if (r) {
		return r;
	}

	mutex_lock(&vm->mutex);
	r = radeon_vm_bind(rdev, vm);
	if (r) {
		goto out;
	}
	r = radeon_bo_vm_update_pte(parser, vm);
	if (r) {
		goto out;
	}
	r = radeon_cs_sync_rings(parser);
	if (r) {
		DRM_ERROR("Failed to synchronize rings !\n");
	}

	if ((rdev->family >= CHIP_TAHITI) &&
	    (parser->chunk_const_ib_idx != -1)) {
		parser->const_ib->vm_id = vm->id;
		/* ib pool is bind at 0 in virtual address space to gpu_addr is the
		 * offset inside the pool bo
		 */
		parser->const_ib->gpu_addr = parser->const_ib->sa_bo.offset;
		r = radeon_ib_schedule(rdev, parser->const_ib);
		if (r)
			goto out;
	}

	parser->ib->vm_id = vm->id;
	/* ib pool is bind at 0 in virtual address space to gpu_addr is the
	 * offset inside the pool bo
	 */
	parser->ib->gpu_addr = parser->ib->sa_bo.offset;
	parser->ib->is_const_ib = false;
	r = radeon_ib_schedule(rdev, parser->ib);
out:
	if (!r) {
		if (vm->fence) {
			radeon_fence_unref(&vm->fence);
		}
		vm->fence = radeon_fence_ref(parser->ib->fence);
	}
	mutex_unlock(&fpriv->vm.mutex);
	return r;
}

int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_cs_parser parser;
	int r;

	radeon_mutex_lock(&rdev->cs_mutex);
	if (!rdev->accel_working) {
		radeon_mutex_unlock(&rdev->cs_mutex);
		return -EBUSY;
	}
	/* initialize parser */
	memset(&parser, 0, sizeof(struct radeon_cs_parser));
	parser.filp = filp;
	parser.rdev = rdev;
	parser.dev = rdev->dev;
	parser.family = rdev->family;
	r = radeon_cs_parser_init(&parser, data);
	if (r) {
		DRM_ERROR("Failed to initialize parser !\n");
		radeon_cs_parser_fini(&parser, r);
		radeon_mutex_unlock(&rdev->cs_mutex);
		return r;
	}
	r = radeon_cs_parser_relocs(&parser);
	if (r) {
		if (r != -ERESTARTSYS)
			DRM_ERROR("Failed to parse relocation %d!\n", r);
		radeon_cs_parser_fini(&parser, r);
		radeon_mutex_unlock(&rdev->cs_mutex);
		return r;
	}
	r = radeon_cs_ib_chunk(rdev, &parser);
	if (r) {
		goto out;
	}
	r = radeon_cs_ib_vm_chunk(rdev, &parser);
	if (r) {
		goto out;
	}
out:
	radeon_cs_parser_fini(&parser, r);
	radeon_mutex_unlock(&rdev->cs_mutex);
	return r;
}

int radeon_cs_finish_pages(struct radeon_cs_parser *p)
{
	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	int i;
	int size = PAGE_SIZE;

	for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
		if (i == ibc->last_page_index) {
			size = (ibc->length_dw * 4) % PAGE_SIZE;
			if (size == 0)
				size = PAGE_SIZE;
		}
		
		if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
				       ibc->user_ptr + (i * PAGE_SIZE),
				       size))
			return -EFAULT;
	}
	return 0;
}

int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
{
	int new_page;
	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	int i;
	int size = PAGE_SIZE;

	for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
		if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
				       ibc->user_ptr + (i * PAGE_SIZE),
				       PAGE_SIZE)) {
			p->parser_error = -EFAULT;
			return 0;
		}
	}

	new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;

	if (pg_idx == ibc->last_page_index) {
		size = (ibc->length_dw * 4) % PAGE_SIZE;
			if (size == 0)
				size = PAGE_SIZE;
	}

	if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
			       ibc->user_ptr + (pg_idx * PAGE_SIZE),
			       size)) {
		p->parser_error = -EFAULT;
		return 0;
	}

	/* copy to IB here */
	memcpy((void *)(p->ib->ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);

	ibc->last_copied_page = pg_idx;
	ibc->kpage_idx[new_page] = pg_idx;

	return new_page;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Jerome Glisse.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors:
	25	* Jerome Glisse <glisse@freedesktop.org>
	26	*/
	27	#include "drmP.h"
	28	#include "radeon_drm.h"
	29	#include "radeon_reg.h"
	30	#include "radeon.h"
	31
	32	void r100_cs_dump_packet(struct radeon_cs_parser *p,
	33	struct radeon_cs_packet *pkt);
	34
	35	int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
	36	{
	37	struct drm_device *ddev = p->rdev->ddev;
	38	struct radeon_cs_chunk *chunk;
	39	unsigned i, j;
	40	bool duplicate;
	41
	42	if (p->chunk_relocs_idx == -1) {
	43	return 0;
	44	}
	45	chunk = &p->chunks[p->chunk_relocs_idx];
	46	/* FIXME: we assume that each relocs use 4 dwords */
	47	p->nrelocs = chunk->length_dw / 4;
	48	p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
	49	if (p->relocs_ptr == NULL) {
	50	return -ENOMEM;
	51	}
	52	p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
	53	if (p->relocs == NULL) {
	54	return -ENOMEM;
	55	}
	56	for (i = 0; i < p->nrelocs; i++) {
	57	struct drm_radeon_cs_reloc *r;
	58
	59	duplicate = false;
	60	r = (struct drm_radeon_cs_reloc )&chunk->kdata[i4];
16557f1e	61	for (j = 0; j < i; j++) {
771fe6b9 JG	62	if (r->handle == p->relocs[j].handle) {
	63	p->relocs_ptr[i] = &p->relocs[j];
	64	duplicate = true;
	65	break;
	66	}
	67	}
	68	if (!duplicate) {
	69	p->relocs[i].gobj = drm_gem_object_lookup(ddev,
	70	p->filp,
	71	r->handle);
	72	if (p->relocs[i].gobj == NULL) {
	73	DRM_ERROR("gem object lookup failed 0x%x\n",
	74	r->handle);
bf79cb91	75	return -ENOENT;
771fe6b9 JG	76	}
771fe6b9 JG	77	p->relocs_ptr[i] = &p->relocs[i];
7e4d15d9	78	p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
4c788679	79	p->relocs[i].lobj.bo = p->relocs[i].robj;
771fe6b9	80	p->relocs[i].lobj.wdomain = r->write_domain;
147666fb TH	81	p->relocs[i].lobj.rdomain = r->read_domains;
147666fb TH	82	p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
771fe6b9 JG	83	p->relocs[i].handle = r->handle;
771fe6b9 JG	84	p->relocs[i].flags = r->flags;
4c788679	85	radeon_bo_list_add_object(&p->relocs[i].lobj,
147666fb	86	&p->validated);
93504fce	87
16557f1e CK	88	} else
16557f1e CK	89	p->relocs[i].handle = 0;
771fe6b9	90	}
94429bb6	91	return radeon_bo_list_validate(&p->validated);
771fe6b9 JG	92	}
771fe6b9 JG	93
721604a1 JG	94	static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
	95	{
	96	p->priority = priority;
	97
	98	switch (ring) {
	99	default:
	100	DRM_ERROR("unknown ring id: %d\n", ring);
	101	return -EINVAL;
	102	case RADEON_CS_RING_GFX:
	103	p->ring = RADEON_RING_TYPE_GFX_INDEX;
	104	break;
	105	case RADEON_CS_RING_COMPUTE:
	106	/* for now */
	107	p->ring = RADEON_RING_TYPE_GFX_INDEX;
	108	break;
	109	}
	110	return 0;
	111	}
	112
93504fce CK	113	static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
93504fce CK	114	{
cdac5504	115	bool sync_to_ring[RADEON_NUM_RINGS] = { };
93504fce CK	116	int i, r;
93504fce CK	117
cdac5504 CK	118	for (i = 0; i < p->nrelocs; i++) {
	119	if (!p->relocs[i].robj \|\| !p->relocs[i].robj->tbo.sync_obj)
	120	continue;
	121
	122	if (!(p->relocs[i].flags & RADEON_RELOC_DONT_SYNC)) {
	123	struct radeon_fence *fence = p->relocs[i].robj->tbo.sync_obj;
	124	if (!radeon_fence_signaled(fence)) {
	125	sync_to_ring[fence->ring] = true;
	126	}
	127	}
	128	}
	129
93504fce CK	130	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
93504fce CK	131	/* no need to sync to our own or unused rings */
cdac5504	132	if (i == p->ring \|\| !sync_to_ring[i] \|\| !p->rdev->ring[i].ready)
93504fce CK	133	continue;
	134
	135	if (!p->ib->fence->semaphore) {
	136	r = radeon_semaphore_create(p->rdev, &p->ib->fence->semaphore);
	137	if (r)
	138	return r;
	139	}
	140
	141	r = radeon_ring_lock(p->rdev, &p->rdev->ring[i], 3);
	142	if (r)
	143	return r;
	144	radeon_semaphore_emit_signal(p->rdev, i, p->ib->fence->semaphore);
	145	radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[i]);
	146
	147	r = radeon_ring_lock(p->rdev, &p->rdev->ring[p->ring], 3);
	148	if (r)
	149	return r;
	150	radeon_semaphore_emit_wait(p->rdev, p->ring, p->ib->fence->semaphore);
	151	radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[p->ring]);
	152	}
	153	return 0;
	154	}
	155
771fe6b9 JG	156	int radeon_cs_parser_init(struct radeon_cs_parser p, void data)
	157	{
	158	struct drm_radeon_cs *cs = data;
	159	uint64_t *chunk_array_ptr;
721604a1 JG	160	unsigned size, i;
	161	u32 ring = RADEON_CS_RING_GFX;
	162	s32 priority = 0;
771fe6b9 JG	163
	164	if (!cs->num_chunks) {
	165	return 0;
	166	}
	167	/* get chunks */
	168	INIT_LIST_HEAD(&p->validated);
	169	p->idx = 0;
	170	p->chunk_ib_idx = -1;
	171	p->chunk_relocs_idx = -1;
721604a1	172	p->chunk_flags_idx = -1;
dfcf5f36	173	p->chunk_const_ib_idx = -1;
771fe6b9 JG	174	p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
	175	if (p->chunks_array == NULL) {
	176	return -ENOMEM;
	177	}
	178	chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
	179	if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
	180	sizeof(uint64_t)*cs->num_chunks)) {
	181	return -EFAULT;
	182	}
721604a1	183	p->cs_flags = 0;
771fe6b9 JG	184	p->nchunks = cs->num_chunks;
	185	p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
	186	if (p->chunks == NULL) {
	187	return -ENOMEM;
	188	}
	189	for (i = 0; i < p->nchunks; i++) {
	190	struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
	191	struct drm_radeon_cs_chunk user_chunk;
	192	uint32_t __user *cdata;
	193
	194	chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
	195	if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
	196	sizeof(struct drm_radeon_cs_chunk))) {
	197	return -EFAULT;
	198	}
5176fdc4 DA	199	p->chunks[i].length_dw = user_chunk.length_dw;
5176fdc4 DA	200	p->chunks[i].kdata = NULL;
771fe6b9	201	p->chunks[i].chunk_id = user_chunk.chunk_id;
5176fdc4	202
771fe6b9 JG	203	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
	204	p->chunk_relocs_idx = i;
	205	}
	206	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
	207	p->chunk_ib_idx = i;
5176fdc4 DA	208	/* zero length IB isn't useful */
	209	if (p->chunks[i].length_dw == 0)
	210	return -EINVAL;
771fe6b9	211	}
dfcf5f36 AD	212	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
	213	p->chunk_const_ib_idx = i;
	214	/* zero length CONST IB isn't useful */
	215	if (p->chunks[i].length_dw == 0)
	216	return -EINVAL;
	217	}
721604a1 JG	218	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
	219	p->chunk_flags_idx = i;
	220	/* zero length flags aren't useful */
	221	if (p->chunks[i].length_dw == 0)
	222	return -EINVAL;
e70f224c	223	}
5176fdc4	224
771fe6b9	225	p->chunks[i].length_dw = user_chunk.length_dw;
513bcb46	226	p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
771fe6b9	227
513bcb46	228	cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
721604a1 JG	229	if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) \|\|
721604a1 JG	230	(p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
513bcb46 DA	231	size = p->chunks[i].length_dw * sizeof(uint32_t);
	232	p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
	233	if (p->chunks[i].kdata == NULL) {
	234	return -ENOMEM;
	235	}
	236	if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
	237	p->chunks[i].user_ptr, size)) {
	238	return -EFAULT;
	239	}
e70f224c	240	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
721604a1 JG	241	p->cs_flags = p->chunks[i].kdata[0];
	242	if (p->chunks[i].length_dw > 1)
	243	ring = p->chunks[i].kdata[1];
	244	if (p->chunks[i].length_dw > 2)
	245	priority = (s32)p->chunks[i].kdata[2];
e70f224c	246	}
771fe6b9 JG	247	}
771fe6b9 JG	248	}
721604a1 JG	249
721604a1 JG	250	if ((p->cs_flags & RADEON_CS_USE_VM) &&
67e915e4 AD	251	!p->rdev->vm_manager.enabled) {
67e915e4 AD	252	DRM_ERROR("VM not active on asic!\n");
771fe6b9 JG	253	return -EINVAL;
771fe6b9 JG	254	}
e70f224c	255
1b5475db AD	256	/* we only support VM on SI+ */
	257	if ((p->rdev->family >= CHIP_TAHITI) &&
	258	((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
	259	DRM_ERROR("VM required on SI+!\n");
	260	return -EINVAL;
	261	}
	262
f48bb04a	263	if (radeon_cs_get_ring(p, ring, priority))
721604a1	264	return -EINVAL;
721604a1 JG	265
	266
	267	/* deal with non-vm */
	268	if ((p->chunk_ib_idx != -1) &&
	269	((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
	270	(p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
	271	if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
	272	DRM_ERROR("cs IB too big: %d\n",
	273	p->chunks[p->chunk_ib_idx].length_dw);
	274	return -EINVAL;
	275	}
	276	p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
	277	p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
	278	if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL \|\|
f48bb04a	279	p->chunks[p->chunk_ib_idx].kpage[1] == NULL)
721604a1	280	return -ENOMEM;
721604a1 JG	281	p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
	282	p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
	283	p->chunks[p->chunk_ib_idx].last_copied_page = -1;
	284	p->chunks[p->chunk_ib_idx].last_page_index =
	285	((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
	286	}
	287
771fe6b9 JG	288	return 0;
	289	}
	290
	291	/**
	292	* cs_parser_fini() - clean parser states
	293	* @parser: parser structure holding parsing context.
	294	* @error: error number
	295	*
	296	* If error is set than unvalidate buffer, otherwise just free memory
	297	* used by parsing context.
	298	**/
	299	static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
	300	{
	301	unsigned i;
	302
147666fb TH	303
	304	if (!error && parser->ib)
	305	ttm_eu_fence_buffer_objects(&parser->validated,
	306	parser->ib->fence);
	307	else
	308	ttm_eu_backoff_reservation(&parser->validated);
	309
fcbc451b PN	310	if (parser->relocs != NULL) {
	311	for (i = 0; i < parser->nrelocs; i++) {
	312	if (parser->relocs[i].gobj)
	313	drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
	314	}
771fe6b9	315	}
48e113e5	316	kfree(parser->track);
771fe6b9 JG	317	kfree(parser->relocs);
	318	kfree(parser->relocs_ptr);
	319	for (i = 0; i < parser->nchunks; i++) {
	320	kfree(parser->chunks[i].kdata);
513bcb46 DA	321	kfree(parser->chunks[i].kpage[0]);
513bcb46 DA	322	kfree(parser->chunks[i].kpage[1]);
771fe6b9 JG	323	}
	324	kfree(parser->chunks);
	325	kfree(parser->chunks_array);
	326	radeon_ib_free(parser->rdev, &parser->ib);
	327	}
	328
721604a1 JG	329	static int radeon_cs_ib_chunk(struct radeon_device *rdev,
	330	struct radeon_cs_parser *parser)
	331	{
	332	struct radeon_cs_chunk *ib_chunk;
	333	int r;
	334
	335	if (parser->chunk_ib_idx == -1)
	336	return 0;
	337
	338	if (parser->cs_flags & RADEON_CS_USE_VM)
	339	return 0;
	340
	341	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	342	/* Copy the packet into the IB, the parser will read from the
	343	* input memory (cached) and write to the IB (which can be
	344	* uncached).
	345	*/
	346	r = radeon_ib_get(rdev, parser->ring, &parser->ib,
	347	ib_chunk->length_dw * 4);
	348	if (r) {
	349	DRM_ERROR("Failed to get ib !\n");
	350	return r;
	351	}
	352	parser->ib->length_dw = ib_chunk->length_dw;
eb0c19c5	353	r = radeon_cs_parse(rdev, parser->ring, parser);
721604a1 JG	354	if (r \|\| parser->parser_error) {
	355	DRM_ERROR("Invalid command stream !\n");
	356	return r;
	357	}
	358	r = radeon_cs_finish_pages(parser);
	359	if (r) {
	360	DRM_ERROR("Invalid command stream !\n");
	361	return r;
	362	}
93504fce CK	363	r = radeon_cs_sync_rings(parser);
	364	if (r) {
	365	DRM_ERROR("Failed to synchronize rings !\n");
	366	}
721604a1 JG	367	parser->ib->vm_id = 0;
	368	r = radeon_ib_schedule(rdev, parser->ib);
	369	if (r) {
	370	DRM_ERROR("Failed to schedule IB !\n");
	371	}
	372	return 0;
	373	}
	374
	375	static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
	376	struct radeon_vm *vm)
	377	{
	378	struct radeon_bo_list *lobj;
	379	struct radeon_bo *bo;
	380	int r;
	381
	382	list_for_each_entry(lobj, &parser->validated, tv.head) {
	383	bo = lobj->bo;
	384	r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
	385	if (r) {
	386	return r;
	387	}
	388	}
	389	return 0;
	390	}
	391
	392	static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
	393	struct radeon_cs_parser *parser)
	394	{
	395	struct radeon_cs_chunk *ib_chunk;
	396	struct radeon_fpriv *fpriv = parser->filp->driver_priv;
	397	struct radeon_vm *vm = &fpriv->vm;
	398	int r;
	399
	400	if (parser->chunk_ib_idx == -1)
	401	return 0;
	402
	403	if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
	404	return 0;
	405
dfcf5f36 AD	406	if ((rdev->family >= CHIP_TAHITI) &&
	407	(parser->chunk_const_ib_idx != -1)) {
	408	ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
	409	if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
	410	DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
	411	return -EINVAL;
	412	}
	413	r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
	414	ib_chunk->length_dw * 4);
	415	if (r) {
	416	DRM_ERROR("Failed to get const ib !\n");
	417	return r;
	418	}
	419	parser->const_ib->is_const_ib = true;
	420	parser->const_ib->length_dw = ib_chunk->length_dw;
	421	/* Copy the packet into the IB */
	422	if (DRM_COPY_FROM_USER(parser->const_ib->ptr, ib_chunk->user_ptr,
	423	ib_chunk->length_dw * 4)) {
	424	return -EFAULT;
	425	}
	426	r = radeon_ring_ib_parse(rdev, parser->ring, parser->const_ib);
	427	if (r) {
	428	return r;
	429	}
	430	}
	431
721604a1 JG	432	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	433	if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
	434	DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
	435	return -EINVAL;
	436	}
	437	r = radeon_ib_get(rdev, parser->ring, &parser->ib,
	438	ib_chunk->length_dw * 4);
	439	if (r) {
	440	DRM_ERROR("Failed to get ib !\n");
	441	return r;
	442	}
	443	parser->ib->length_dw = ib_chunk->length_dw;
	444	/* Copy the packet into the IB */
	445	if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr,
	446	ib_chunk->length_dw * 4)) {
	447	return -EFAULT;
	448	}
	449	r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib);
	450	if (r) {
	451	return r;
	452	}
	453
	454	mutex_lock(&vm->mutex);
	455	r = radeon_vm_bind(rdev, vm);
	456	if (r) {
	457	goto out;
	458	}
	459	r = radeon_bo_vm_update_pte(parser, vm);
	460	if (r) {
	461	goto out;
	462	}
93504fce CK	463	r = radeon_cs_sync_rings(parser);
	464	if (r) {
	465	DRM_ERROR("Failed to synchronize rings !\n");
	466	}
dfcf5f36 AD	467
	468	if ((rdev->family >= CHIP_TAHITI) &&
	469	(parser->chunk_const_ib_idx != -1)) {
	470	parser->const_ib->vm_id = vm->id;
	471	/* ib pool is bind at 0 in virtual address space to gpu_addr is the
	472	* offset inside the pool bo
	473	*/
	474	parser->const_ib->gpu_addr = parser->const_ib->sa_bo.offset;
	475	r = radeon_ib_schedule(rdev, parser->const_ib);
	476	if (r)
	477	goto out;
	478	}
	479
721604a1 JG	480	parser->ib->vm_id = vm->id;
	481	/* ib pool is bind at 0 in virtual address space to gpu_addr is the
	482	* offset inside the pool bo
	483	*/
	484	parser->ib->gpu_addr = parser->ib->sa_bo.offset;
dfcf5f36	485	parser->ib->is_const_ib = false;
721604a1 JG	486	r = radeon_ib_schedule(rdev, parser->ib);
	487	out:
	488	if (!r) {
	489	if (vm->fence) {
	490	radeon_fence_unref(&vm->fence);
	491	}
	492	vm->fence = radeon_fence_ref(parser->ib->fence);
	493	}
	494	mutex_unlock(&fpriv->vm.mutex);
	495	return r;
	496	}
	497
771fe6b9 JG	498	int radeon_cs_ioctl(struct drm_device dev, void data, struct drm_file *filp)
	499	{
	500	struct radeon_device *rdev = dev->dev_private;
	501	struct radeon_cs_parser parser;
771fe6b9 JG	502	int r;
771fe6b9 JG	503
7a1619b9	504	radeon_mutex_lock(&rdev->cs_mutex);
6b7746e8 JG	505	if (!rdev->accel_working) {
	506	radeon_mutex_unlock(&rdev->cs_mutex);
	507	return -EBUSY;
	508	}
771fe6b9 JG	509	/* initialize parser */
	510	memset(&parser, 0, sizeof(struct radeon_cs_parser));
	511	parser.filp = filp;
	512	parser.rdev = rdev;
c8c15ff1	513	parser.dev = rdev->dev;
428c6e36	514	parser.family = rdev->family;
771fe6b9 JG	515	r = radeon_cs_parser_init(&parser, data);
	516	if (r) {
	517	DRM_ERROR("Failed to initialize parser !\n");
	518	radeon_cs_parser_fini(&parser, r);
7a1619b9	519	radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9 JG	520	return r;
771fe6b9 JG	521	}
771fe6b9 JG	522	r = radeon_cs_parser_relocs(&parser);
771fe6b9 JG	523	if (r) {
97f23b3d DA	524	if (r != -ERESTARTSYS)
97f23b3d DA	525	DRM_ERROR("Failed to parse relocation %d!\n", r);
771fe6b9	526	radeon_cs_parser_fini(&parser, r);
7a1619b9	527	radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9 JG	528	return r;
771fe6b9 JG	529	}
721604a1	530	r = radeon_cs_ib_chunk(rdev, &parser);
771fe6b9	531	if (r) {
721604a1	532	goto out;
771fe6b9	533	}
721604a1	534	r = radeon_cs_ib_vm_chunk(rdev, &parser);
771fe6b9	535	if (r) {
721604a1	536	goto out;
771fe6b9	537	}
721604a1	538	out:
771fe6b9	539	radeon_cs_parser_fini(&parser, r);
7a1619b9	540	radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9 JG	541	return r;
771fe6b9 JG	542	}
513bcb46 DA	543
	544	int radeon_cs_finish_pages(struct radeon_cs_parser *p)
	545	{
	546	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	547	int i;
	548	int size = PAGE_SIZE;
	549
	550	for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
	551	if (i == ibc->last_page_index) {
	552	size = (ibc->length_dw * 4) % PAGE_SIZE;
	553	if (size == 0)
	554	size = PAGE_SIZE;
	555	}
	556
	557	if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
	558	ibc->user_ptr + (i * PAGE_SIZE),
	559	size))
	560	return -EFAULT;
	561	}
	562	return 0;
	563	}
	564
	565	int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
	566	{
	567	int new_page;
513bcb46 DA	568	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	569	int i;
	570	int size = PAGE_SIZE;
	571
c5e617e2	572	for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
513bcb46 DA	573	if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
	574	ibc->user_ptr + (i * PAGE_SIZE),
	575	PAGE_SIZE)) {
	576	p->parser_error = -EFAULT;
	577	return 0;
	578	}
	579	}
	580
	581	new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
	582
	583	if (pg_idx == ibc->last_page_index) {
	584	size = (ibc->length_dw * 4) % PAGE_SIZE;
	585	if (size == 0)
	586	size = PAGE_SIZE;
	587	}
	588
	589	if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
	590	ibc->user_ptr + (pg_idx * PAGE_SIZE),
	591	size)) {
	592	p->parser_error = -EFAULT;
	593	return 0;
	594	}
	595
	596	/* copy to IB here */
	597	memcpy((void )(p->ib->ptr+(pg_idx(PAGE_SIZE/4))), ibc->kpage[new_page], size);
	598
	599	ibc->last_copied_page = pg_idx;
	600	ibc->kpage_idx[new_page] = pg_idx;
	601
	602	return new_page;
	603	}