[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_cs.c

/*
 * Copyright 2008 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 */
#include "drmP.h"
#include "radeon_drm.h"
#include "radeon_reg.h"
#include "radeon.h"

void r100_cs_dump_packet(struct radeon_cs_parser *p,
			 struct radeon_cs_packet *pkt);

int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
{
	struct drm_device *ddev = p->rdev->ddev;
	struct radeon_cs_chunk *chunk;
	unsigned i, j;
	bool duplicate;

	if (p->chunk_relocs_idx == -1) {
		return 0;
	}
	chunk = &p->chunks[p->chunk_relocs_idx];
	/* FIXME: we assume that each relocs use 4 dwords */
	p->nrelocs = chunk->length_dw / 4;
	p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
	if (p->relocs_ptr == NULL) {
		return -ENOMEM;
	}
	p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
	if (p->relocs == NULL) {
		return -ENOMEM;
	}
	for (i = 0; i < p->nrelocs; i++) {
		struct drm_radeon_cs_reloc *r;

		duplicate = false;
		r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
		for (j = 0; j < i; j++) {
			if (r->handle == p->relocs[j].handle) {
				p->relocs_ptr[i] = &p->relocs[j];
				duplicate = true;
				break;
			}
		}
		if (!duplicate) {
			p->relocs[i].gobj = drm_gem_object_lookup(ddev,
								  p->filp,
								  r->handle);
			if (p->relocs[i].gobj == NULL) {
				DRM_ERROR("gem object lookup failed 0x%x\n",
					  r->handle);
				return -ENOENT;
			}
			p->relocs_ptr[i] = &p->relocs[i];
			p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
			p->relocs[i].lobj.bo = p->relocs[i].robj;
			p->relocs[i].lobj.wdomain = r->write_domain;
			p->relocs[i].lobj.rdomain = r->read_domains;
			p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
			p->relocs[i].handle = r->handle;
			p->relocs[i].flags = r->flags;
			radeon_bo_list_add_object(&p->relocs[i].lobj,
						  &p->validated);

		} else
			p->relocs[i].handle = 0;
	}
	return radeon_bo_list_validate(&p->validated);
}

static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
{
	p->priority = priority;

	switch (ring) {
	default:
		DRM_ERROR("unknown ring id: %d\n", ring);
		return -EINVAL;
	case RADEON_CS_RING_GFX:
		p->ring = RADEON_RING_TYPE_GFX_INDEX;
		break;
	case RADEON_CS_RING_COMPUTE:
		if (p->rdev->family >= CHIP_TAHITI) {
			if (p->priority > 0)
				p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
			else
				p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
		} else
			p->ring = RADEON_RING_TYPE_GFX_INDEX;
		break;
	}
	return 0;
}

static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
{
	bool sync_to_ring[RADEON_NUM_RINGS] = { };
	bool need_sync = false;
	int i, r;

	for (i = 0; i < p->nrelocs; i++) {
		struct radeon_fence *fence;

		if (!p->relocs[i].robj || !p->relocs[i].robj->tbo.sync_obj)
			continue;

		fence = p->relocs[i].robj->tbo.sync_obj;
		if (fence->ring != p->ring && !radeon_fence_signaled(fence)) {
			sync_to_ring[fence->ring] = true;
			need_sync = true;
		}
	}

	if (!need_sync) {
		return 0;
	}

	r = radeon_semaphore_create(p->rdev, &p->ib.semaphore);
	if (r) {
		return r;
	}

	return radeon_semaphore_sync_rings(p->rdev, p->ib.semaphore,
					   sync_to_ring, p->ring);
}

int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
{
	struct drm_radeon_cs *cs = data;
	uint64_t *chunk_array_ptr;
	unsigned size, i;
	u32 ring = RADEON_CS_RING_GFX;
	s32 priority = 0;

	if (!cs->num_chunks) {
		return 0;
	}
	/* get chunks */
	INIT_LIST_HEAD(&p->validated);
	p->idx = 0;
	p->ib.sa_bo = NULL;
	p->ib.semaphore = NULL;
	p->const_ib.sa_bo = NULL;
	p->const_ib.semaphore = NULL;
	p->chunk_ib_idx = -1;
	p->chunk_relocs_idx = -1;
	p->chunk_flags_idx = -1;
	p->chunk_const_ib_idx = -1;
	p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
	if (p->chunks_array == NULL) {
		return -ENOMEM;
	}
	chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
	if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
			       sizeof(uint64_t)*cs->num_chunks)) {
		return -EFAULT;
	}
	p->cs_flags = 0;
	p->nchunks = cs->num_chunks;
	p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
	if (p->chunks == NULL) {
		return -ENOMEM;
	}
	for (i = 0; i < p->nchunks; i++) {
		struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
		struct drm_radeon_cs_chunk user_chunk;
		uint32_t __user *cdata;

		chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
		if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
				       sizeof(struct drm_radeon_cs_chunk))) {
			return -EFAULT;
		}
		p->chunks[i].length_dw = user_chunk.length_dw;
		p->chunks[i].kdata = NULL;
		p->chunks[i].chunk_id = user_chunk.chunk_id;

		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
			p->chunk_relocs_idx = i;
		}
		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
			p->chunk_ib_idx = i;
			/* zero length IB isn't useful */
			if (p->chunks[i].length_dw == 0)
				return -EINVAL;
		}
		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
			p->chunk_const_ib_idx = i;
			/* zero length CONST IB isn't useful */
			if (p->chunks[i].length_dw == 0)
				return -EINVAL;
		}
		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
			p->chunk_flags_idx = i;
			/* zero length flags aren't useful */
			if (p->chunks[i].length_dw == 0)
				return -EINVAL;
		}

		p->chunks[i].length_dw = user_chunk.length_dw;
		p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;

		cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
		if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
		    (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
			size = p->chunks[i].length_dw * sizeof(uint32_t);
			p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
			if (p->chunks[i].kdata == NULL) {
				return -ENOMEM;
			}
			if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
					       p->chunks[i].user_ptr, size)) {
				return -EFAULT;
			}
			if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
				p->cs_flags = p->chunks[i].kdata[0];
				if (p->chunks[i].length_dw > 1)
					ring = p->chunks[i].kdata[1];
				if (p->chunks[i].length_dw > 2)
					priority = (s32)p->chunks[i].kdata[2];
			}
		}
	}

	if ((p->cs_flags & RADEON_CS_USE_VM) &&
	    !p->rdev->vm_manager.enabled) {
		DRM_ERROR("VM not active on asic!\n");
		return -EINVAL;
	}

	/* we only support VM on SI+ */
	if ((p->rdev->family >= CHIP_TAHITI) &&
	    ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
		DRM_ERROR("VM required on SI+!\n");
		return -EINVAL;
	}

	if (radeon_cs_get_ring(p, ring, priority))
		return -EINVAL;


	/* deal with non-vm */
	if ((p->chunk_ib_idx != -1) &&
	    ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
	    (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
		if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
			DRM_ERROR("cs IB too big: %d\n",
				  p->chunks[p->chunk_ib_idx].length_dw);
			return -EINVAL;
		}
		if ((p->rdev->flags & RADEON_IS_AGP)) {
			p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
			p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
			if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
			    p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
				kfree(p->chunks[i].kpage[0]);
				kfree(p->chunks[i].kpage[1]);
				return -ENOMEM;
			}
		}
		p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
		p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
		p->chunks[p->chunk_ib_idx].last_copied_page = -1;
		p->chunks[p->chunk_ib_idx].last_page_index =
			((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
	}

	return 0;
}

/**
 * cs_parser_fini() - clean parser states
 * @parser:	parser structure holding parsing context.
 * @error:	error number
 *
 * If error is set than unvalidate buffer, otherwise just free memory
 * used by parsing context.
 **/
static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
{
	unsigned i;

	if (!error)
		ttm_eu_fence_buffer_objects(&parser->validated,
					    parser->ib.fence);
	else
		ttm_eu_backoff_reservation(&parser->validated);

	if (parser->relocs != NULL) {
		for (i = 0; i < parser->nrelocs; i++) {
			if (parser->relocs[i].gobj)
				drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
		}
	}
	kfree(parser->track);
	kfree(parser->relocs);
	kfree(parser->relocs_ptr);
	for (i = 0; i < parser->nchunks; i++) {
		kfree(parser->chunks[i].kdata);
		if ((parser->rdev->flags & RADEON_IS_AGP)) {
			kfree(parser->chunks[i].kpage[0]);
			kfree(parser->chunks[i].kpage[1]);
		}
	}
	kfree(parser->chunks);
	kfree(parser->chunks_array);
	radeon_ib_free(parser->rdev, &parser->ib);
	radeon_ib_free(parser->rdev, &parser->const_ib);
}

static int radeon_cs_ib_chunk(struct radeon_device *rdev,
			      struct radeon_cs_parser *parser)
{
	struct radeon_cs_chunk *ib_chunk;
	int r;

	if (parser->chunk_ib_idx == -1)
		return 0;

	if (parser->cs_flags & RADEON_CS_USE_VM)
		return 0;

	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	/* Copy the packet into the IB, the parser will read from the
	 * input memory (cached) and write to the IB (which can be
	 * uncached).
	 */
	r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
			   ib_chunk->length_dw * 4);
	if (r) {
		DRM_ERROR("Failed to get ib !\n");
		return r;
	}
	parser->ib.length_dw = ib_chunk->length_dw;
	r = radeon_cs_parse(rdev, parser->ring, parser);
	if (r || parser->parser_error) {
		DRM_ERROR("Invalid command stream !\n");
		return r;
	}
	r = radeon_cs_finish_pages(parser);
	if (r) {
		DRM_ERROR("Invalid command stream !\n");
		return r;
	}
	r = radeon_cs_sync_rings(parser);
	if (r) {
		DRM_ERROR("Failed to synchronize rings !\n");
	}
	parser->ib.vm_id = 0;
	r = radeon_ib_schedule(rdev, &parser->ib);
	if (r) {
		DRM_ERROR("Failed to schedule IB !\n");
	}
	return 0;
}

static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
				   struct radeon_vm *vm)
{
	struct radeon_bo_list *lobj;
	struct radeon_bo *bo;
	int r;

	list_for_each_entry(lobj, &parser->validated, tv.head) {
		bo = lobj->bo;
		r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
		if (r) {
			return r;
		}
	}
	return 0;
}

static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
				 struct radeon_cs_parser *parser)
{
	struct radeon_cs_chunk *ib_chunk;
	struct radeon_fpriv *fpriv = parser->filp->driver_priv;
	struct radeon_vm *vm = &fpriv->vm;
	int r;

	if (parser->chunk_ib_idx == -1)
		return 0;

	if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
		return 0;

	if ((rdev->family >= CHIP_TAHITI) &&
	    (parser->chunk_const_ib_idx != -1)) {
		ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
		if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
			DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
			return -EINVAL;
		}
		r =  radeon_ib_get(rdev, parser->ring, &parser->const_ib,
				   ib_chunk->length_dw * 4);
		if (r) {
			DRM_ERROR("Failed to get const ib !\n");
			return r;
		}
		parser->const_ib.is_const_ib = true;
		parser->const_ib.length_dw = ib_chunk->length_dw;
		/* Copy the packet into the IB */
		if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
				       ib_chunk->length_dw * 4)) {
			return -EFAULT;
		}
		r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
		if (r) {
			return r;
		}
	}

	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
		DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
		return -EINVAL;
	}
	r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
			   ib_chunk->length_dw * 4);
	if (r) {
		DRM_ERROR("Failed to get ib !\n");
		return r;
	}
	parser->ib.length_dw = ib_chunk->length_dw;
	/* Copy the packet into the IB */
	if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
			       ib_chunk->length_dw * 4)) {
		return -EFAULT;
	}
	r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
	if (r) {
		return r;
	}

	mutex_lock(&vm->mutex);
	r = radeon_vm_bind(rdev, vm);
	if (r) {
		goto out;
	}
	r = radeon_bo_vm_update_pte(parser, vm);
	if (r) {
		goto out;
	}
	r = radeon_cs_sync_rings(parser);
	if (r) {
		DRM_ERROR("Failed to synchronize rings !\n");
	}

	if ((rdev->family >= CHIP_TAHITI) &&
	    (parser->chunk_const_ib_idx != -1)) {
		parser->const_ib.vm_id = vm->id;
		/* ib pool is bind at 0 in virtual address space to gpu_addr is the
		 * offset inside the pool bo
		 */
		parser->const_ib.gpu_addr = parser->const_ib.sa_bo->soffset;
		r = radeon_ib_schedule(rdev, &parser->const_ib);
		if (r)
			goto out;
	}

	parser->ib.vm_id = vm->id;
	/* ib pool is bind at 0 in virtual address space to gpu_addr is the
	 * offset inside the pool bo
	 */
	parser->ib.gpu_addr = parser->ib.sa_bo->soffset;
	parser->ib.is_const_ib = false;
	r = radeon_ib_schedule(rdev, &parser->ib);
out:
	if (!r) {
		if (vm->fence) {
			radeon_fence_unref(&vm->fence);
		}
		vm->fence = radeon_fence_ref(parser->ib.fence);
	}
	mutex_unlock(&fpriv->vm.mutex);
	return r;
}

static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
{
	if (r == -EDEADLK) {
		r = radeon_gpu_reset(rdev);
		if (!r)
			r = -EAGAIN;
	}
	return r;
}

int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_cs_parser parser;
	int r;

	radeon_mutex_lock(&rdev->cs_mutex);
	if (!rdev->accel_working) {
		radeon_mutex_unlock(&rdev->cs_mutex);
		return -EBUSY;
	}
	/* initialize parser */
	memset(&parser, 0, sizeof(struct radeon_cs_parser));
	parser.filp = filp;
	parser.rdev = rdev;
	parser.dev = rdev->dev;
	parser.family = rdev->family;
	r = radeon_cs_parser_init(&parser, data);
	if (r) {
		DRM_ERROR("Failed to initialize parser !\n");
		radeon_cs_parser_fini(&parser, r);
		r = radeon_cs_handle_lockup(rdev, r);
		radeon_mutex_unlock(&rdev->cs_mutex);
		return r;
	}
	r = radeon_cs_parser_relocs(&parser);
	if (r) {
		if (r != -ERESTARTSYS)
			DRM_ERROR("Failed to parse relocation %d!\n", r);
		radeon_cs_parser_fini(&parser, r);
		r = radeon_cs_handle_lockup(rdev, r);
		radeon_mutex_unlock(&rdev->cs_mutex);
		return r;
	}
	r = radeon_cs_ib_chunk(rdev, &parser);
	if (r) {
		goto out;
	}
	r = radeon_cs_ib_vm_chunk(rdev, &parser);
	if (r) {
		goto out;
	}
out:
	radeon_cs_parser_fini(&parser, r);
	r = radeon_cs_handle_lockup(rdev, r);
	radeon_mutex_unlock(&rdev->cs_mutex);
	return r;
}

int radeon_cs_finish_pages(struct radeon_cs_parser *p)
{
	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	int i;
	int size = PAGE_SIZE;

	for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
		if (i == ibc->last_page_index) {
			size = (ibc->length_dw * 4) % PAGE_SIZE;
			if (size == 0)
				size = PAGE_SIZE;
		}
		
		if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
				       ibc->user_ptr + (i * PAGE_SIZE),
				       size))
			return -EFAULT;
	}
	return 0;
}

int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
{
	int new_page;
	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	int i;
	int size = PAGE_SIZE;
	bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true;

	for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
		if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
				       ibc->user_ptr + (i * PAGE_SIZE),
				       PAGE_SIZE)) {
			p->parser_error = -EFAULT;
			return 0;
		}
	}

	if (pg_idx == ibc->last_page_index) {
		size = (ibc->length_dw * 4) % PAGE_SIZE;
		if (size == 0)
			size = PAGE_SIZE;
	}

	new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
	if (copy1)
		ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));

	if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
			       ibc->user_ptr + (pg_idx * PAGE_SIZE),
			       size)) {
		p->parser_error = -EFAULT;
		return 0;
	}

	/* copy to IB for non single case */
	if (!copy1)
		memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);

	ibc->last_copied_page = pg_idx;
	ibc->kpage_idx[new_page] = pg_idx;

	return new_page;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Jerome Glisse.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors:
	25	* Jerome Glisse <glisse@freedesktop.org>
	26	*/
	27	#include "drmP.h"
	28	#include "radeon_drm.h"
	29	#include "radeon_reg.h"
	30	#include "radeon.h"
	31
	32	void r100_cs_dump_packet(struct radeon_cs_parser *p,
	33	struct radeon_cs_packet *pkt);
	34
	35	int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
	36	{
	37	struct drm_device *ddev = p->rdev->ddev;
	38	struct radeon_cs_chunk *chunk;
	39	unsigned i, j;
	40	bool duplicate;
	41
	42	if (p->chunk_relocs_idx == -1) {
	43	return 0;
	44	}
	45	chunk = &p->chunks[p->chunk_relocs_idx];
	46	/* FIXME: we assume that each relocs use 4 dwords */
	47	p->nrelocs = chunk->length_dw / 4;
	48	p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
	49	if (p->relocs_ptr == NULL) {
	50	return -ENOMEM;
	51	}
	52	p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
	53	if (p->relocs == NULL) {
	54	return -ENOMEM;
	55	}
	56	for (i = 0; i < p->nrelocs; i++) {
	57	struct drm_radeon_cs_reloc *r;
	58
	59	duplicate = false;
	60	r = (struct drm_radeon_cs_reloc )&chunk->kdata[i4];
16557f1e	61	for (j = 0; j < i; j++) {
771fe6b9 JG	62	if (r->handle == p->relocs[j].handle) {
	63	p->relocs_ptr[i] = &p->relocs[j];
	64	duplicate = true;
	65	break;
	66	}
	67	}
	68	if (!duplicate) {
	69	p->relocs[i].gobj = drm_gem_object_lookup(ddev,
	70	p->filp,
	71	r->handle);
	72	if (p->relocs[i].gobj == NULL) {
	73	DRM_ERROR("gem object lookup failed 0x%x\n",
	74	r->handle);
bf79cb91	75	return -ENOENT;
771fe6b9 JG	76	}
771fe6b9 JG	77	p->relocs_ptr[i] = &p->relocs[i];
7e4d15d9	78	p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
4c788679	79	p->relocs[i].lobj.bo = p->relocs[i].robj;
771fe6b9	80	p->relocs[i].lobj.wdomain = r->write_domain;
147666fb TH	81	p->relocs[i].lobj.rdomain = r->read_domains;
147666fb TH	82	p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
771fe6b9 JG	83	p->relocs[i].handle = r->handle;
771fe6b9 JG	84	p->relocs[i].flags = r->flags;
4c788679	85	radeon_bo_list_add_object(&p->relocs[i].lobj,
147666fb	86	&p->validated);
93504fce	87
16557f1e CK	88	} else
16557f1e CK	89	p->relocs[i].handle = 0;
771fe6b9	90	}
94429bb6	91	return radeon_bo_list_validate(&p->validated);
771fe6b9 JG	92	}
771fe6b9 JG	93
721604a1 JG	94	static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
	95	{
	96	p->priority = priority;
	97
	98	switch (ring) {
	99	default:
	100	DRM_ERROR("unknown ring id: %d\n", ring);
	101	return -EINVAL;
	102	case RADEON_CS_RING_GFX:
	103	p->ring = RADEON_RING_TYPE_GFX_INDEX;
	104	break;
	105	case RADEON_CS_RING_COMPUTE:
8d5ef7b1 AD	106	if (p->rdev->family >= CHIP_TAHITI) {
	107	if (p->priority > 0)
	108	p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
	109	else
	110	p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
	111	} else
	112	p->ring = RADEON_RING_TYPE_GFX_INDEX;
721604a1 JG	113	break;
	114	}
	115	return 0;
	116	}
	117
93504fce CK	118	static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
93504fce CK	119	{
cdac5504	120	bool sync_to_ring[RADEON_NUM_RINGS] = { };
8f676c4c	121	bool need_sync = false;
93504fce CK	122	int i, r;
93504fce CK	123
cdac5504	124	for (i = 0; i < p->nrelocs; i++) {
133f4cb3 JG	125	struct radeon_fence *fence;
133f4cb3 JG	126
cdac5504 CK	127	if (!p->relocs[i].robj \|\| !p->relocs[i].robj->tbo.sync_obj)
	128	continue;
	129
133f4cb3 JG	130	fence = p->relocs[i].robj->tbo.sync_obj;
	131	if (fence->ring != p->ring && !radeon_fence_signaled(fence)) {
	132	sync_to_ring[fence->ring] = true;
	133	need_sync = true;
cdac5504 CK	134	}
	135	}
	136
8f676c4c CK	137	if (!need_sync) {
	138	return 0;
	139	}
93504fce	140
f2e39221	141	r = radeon_semaphore_create(p->rdev, &p->ib.semaphore);
8f676c4c CK	142	if (r) {
8f676c4c CK	143	return r;
93504fce	144	}
8f676c4c	145
f2e39221	146	return radeon_semaphore_sync_rings(p->rdev, p->ib.semaphore,
8f676c4c	147	sync_to_ring, p->ring);
93504fce CK	148	}
93504fce CK	149
771fe6b9 JG	150	int radeon_cs_parser_init(struct radeon_cs_parser p, void data)
	151	{
	152	struct drm_radeon_cs *cs = data;
	153	uint64_t *chunk_array_ptr;
721604a1 JG	154	unsigned size, i;
	155	u32 ring = RADEON_CS_RING_GFX;
	156	s32 priority = 0;
771fe6b9 JG	157
	158	if (!cs->num_chunks) {
	159	return 0;
	160	}
	161	/* get chunks */
	162	INIT_LIST_HEAD(&p->validated);
	163	p->idx = 0;
f2e39221 JG	164	p->ib.sa_bo = NULL;
	165	p->ib.semaphore = NULL;
	166	p->const_ib.sa_bo = NULL;
	167	p->const_ib.semaphore = NULL;
771fe6b9 JG	168	p->chunk_ib_idx = -1;
771fe6b9 JG	169	p->chunk_relocs_idx = -1;
721604a1	170	p->chunk_flags_idx = -1;
dfcf5f36	171	p->chunk_const_ib_idx = -1;
771fe6b9 JG	172	p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
	173	if (p->chunks_array == NULL) {
	174	return -ENOMEM;
	175	}
	176	chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
	177	if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
	178	sizeof(uint64_t)*cs->num_chunks)) {
	179	return -EFAULT;
	180	}
721604a1	181	p->cs_flags = 0;
771fe6b9 JG	182	p->nchunks = cs->num_chunks;
	183	p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
	184	if (p->chunks == NULL) {
	185	return -ENOMEM;
	186	}
	187	for (i = 0; i < p->nchunks; i++) {
	188	struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
	189	struct drm_radeon_cs_chunk user_chunk;
	190	uint32_t __user *cdata;
	191
	192	chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
	193	if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
	194	sizeof(struct drm_radeon_cs_chunk))) {
	195	return -EFAULT;
	196	}
5176fdc4 DA	197	p->chunks[i].length_dw = user_chunk.length_dw;
5176fdc4 DA	198	p->chunks[i].kdata = NULL;
771fe6b9	199	p->chunks[i].chunk_id = user_chunk.chunk_id;
5176fdc4	200
771fe6b9 JG	201	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
	202	p->chunk_relocs_idx = i;
	203	}
	204	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
	205	p->chunk_ib_idx = i;
5176fdc4 DA	206	/* zero length IB isn't useful */
	207	if (p->chunks[i].length_dw == 0)
	208	return -EINVAL;
771fe6b9	209	}
dfcf5f36 AD	210	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
	211	p->chunk_const_ib_idx = i;
	212	/* zero length CONST IB isn't useful */
	213	if (p->chunks[i].length_dw == 0)
	214	return -EINVAL;
	215	}
721604a1 JG	216	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
	217	p->chunk_flags_idx = i;
	218	/* zero length flags aren't useful */
	219	if (p->chunks[i].length_dw == 0)
	220	return -EINVAL;
e70f224c	221	}
5176fdc4	222
771fe6b9	223	p->chunks[i].length_dw = user_chunk.length_dw;
513bcb46	224	p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
771fe6b9	225
513bcb46	226	cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
721604a1 JG	227	if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) \|\|
721604a1 JG	228	(p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
513bcb46 DA	229	size = p->chunks[i].length_dw * sizeof(uint32_t);
	230	p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
	231	if (p->chunks[i].kdata == NULL) {
	232	return -ENOMEM;
	233	}
	234	if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
	235	p->chunks[i].user_ptr, size)) {
	236	return -EFAULT;
	237	}
e70f224c	238	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
721604a1 JG	239	p->cs_flags = p->chunks[i].kdata[0];
	240	if (p->chunks[i].length_dw > 1)
	241	ring = p->chunks[i].kdata[1];
	242	if (p->chunks[i].length_dw > 2)
	243	priority = (s32)p->chunks[i].kdata[2];
e70f224c	244	}
771fe6b9 JG	245	}
771fe6b9 JG	246	}
721604a1 JG	247
721604a1 JG	248	if ((p->cs_flags & RADEON_CS_USE_VM) &&
67e915e4 AD	249	!p->rdev->vm_manager.enabled) {
67e915e4 AD	250	DRM_ERROR("VM not active on asic!\n");
771fe6b9 JG	251	return -EINVAL;
771fe6b9 JG	252	}
e70f224c	253
1b5475db AD	254	/* we only support VM on SI+ */
	255	if ((p->rdev->family >= CHIP_TAHITI) &&
	256	((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
	257	DRM_ERROR("VM required on SI+!\n");
	258	return -EINVAL;
	259	}
	260
f48bb04a	261	if (radeon_cs_get_ring(p, ring, priority))
721604a1	262	return -EINVAL;
721604a1 JG	263
	264
	265	/* deal with non-vm */
	266	if ((p->chunk_ib_idx != -1) &&
	267	((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
	268	(p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
	269	if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
	270	DRM_ERROR("cs IB too big: %d\n",
	271	p->chunks[p->chunk_ib_idx].length_dw);
	272	return -EINVAL;
	273	}
6a7068b4 DA	274	if ((p->rdev->flags & RADEON_IS_AGP)) {
	275	p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
	276	p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
	277	if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL \|\|
	278	p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
	279	kfree(p->chunks[i].kpage[0]);
	280	kfree(p->chunks[i].kpage[1]);
	281	return -ENOMEM;
	282	}
	283	}
721604a1 JG	284	p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
	285	p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
	286	p->chunks[p->chunk_ib_idx].last_copied_page = -1;
	287	p->chunks[p->chunk_ib_idx].last_page_index =
	288	((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
	289	}
	290
771fe6b9 JG	291	return 0;
	292	}
	293
	294	/**
	295	* cs_parser_fini() - clean parser states
	296	* @parser: parser structure holding parsing context.
	297	* @error: error number
	298	*
	299	* If error is set than unvalidate buffer, otherwise just free memory
	300	* used by parsing context.
	301	**/
	302	static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
	303	{
	304	unsigned i;
	305
f2e39221	306	if (!error)
147666fb	307	ttm_eu_fence_buffer_objects(&parser->validated,
f2e39221	308	parser->ib.fence);
147666fb TH	309	else
	310	ttm_eu_backoff_reservation(&parser->validated);
	311
fcbc451b PN	312	if (parser->relocs != NULL) {
	313	for (i = 0; i < parser->nrelocs; i++) {
	314	if (parser->relocs[i].gobj)
	315	drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
	316	}
771fe6b9	317	}
48e113e5	318	kfree(parser->track);
771fe6b9 JG	319	kfree(parser->relocs);
	320	kfree(parser->relocs_ptr);
	321	for (i = 0; i < parser->nchunks; i++) {
	322	kfree(parser->chunks[i].kdata);
6a7068b4 DA	323	if ((parser->rdev->flags & RADEON_IS_AGP)) {
	324	kfree(parser->chunks[i].kpage[0]);
	325	kfree(parser->chunks[i].kpage[1]);
	326	}
771fe6b9 JG	327	}
	328	kfree(parser->chunks);
	329	kfree(parser->chunks_array);
	330	radeon_ib_free(parser->rdev, &parser->ib);
f2e39221	331	radeon_ib_free(parser->rdev, &parser->const_ib);
771fe6b9 JG	332	}
771fe6b9 JG	333
721604a1 JG	334	static int radeon_cs_ib_chunk(struct radeon_device *rdev,
	335	struct radeon_cs_parser *parser)
	336	{
	337	struct radeon_cs_chunk *ib_chunk;
	338	int r;
	339
	340	if (parser->chunk_ib_idx == -1)
	341	return 0;
	342
	343	if (parser->cs_flags & RADEON_CS_USE_VM)
	344	return 0;
	345
	346	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	347	/* Copy the packet into the IB, the parser will read from the
	348	* input memory (cached) and write to the IB (which can be
	349	* uncached).
	350	*/
	351	r = radeon_ib_get(rdev, parser->ring, &parser->ib,
	352	ib_chunk->length_dw * 4);
	353	if (r) {
	354	DRM_ERROR("Failed to get ib !\n");
	355	return r;
	356	}
f2e39221	357	parser->ib.length_dw = ib_chunk->length_dw;
eb0c19c5	358	r = radeon_cs_parse(rdev, parser->ring, parser);
721604a1 JG	359	if (r \|\| parser->parser_error) {
	360	DRM_ERROR("Invalid command stream !\n");
	361	return r;
	362	}
	363	r = radeon_cs_finish_pages(parser);
	364	if (r) {
	365	DRM_ERROR("Invalid command stream !\n");
	366	return r;
	367	}
93504fce CK	368	r = radeon_cs_sync_rings(parser);
	369	if (r) {
	370	DRM_ERROR("Failed to synchronize rings !\n");
	371	}
f2e39221 JG	372	parser->ib.vm_id = 0;
f2e39221 JG	373	r = radeon_ib_schedule(rdev, &parser->ib);
721604a1 JG	374	if (r) {
	375	DRM_ERROR("Failed to schedule IB !\n");
	376	}
	377	return 0;
	378	}
	379
	380	static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
	381	struct radeon_vm *vm)
	382	{
	383	struct radeon_bo_list *lobj;
	384	struct radeon_bo *bo;
	385	int r;
	386
	387	list_for_each_entry(lobj, &parser->validated, tv.head) {
	388	bo = lobj->bo;
	389	r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
	390	if (r) {
	391	return r;
	392	}
	393	}
	394	return 0;
	395	}
	396
	397	static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
	398	struct radeon_cs_parser *parser)
	399	{
	400	struct radeon_cs_chunk *ib_chunk;
	401	struct radeon_fpriv *fpriv = parser->filp->driver_priv;
	402	struct radeon_vm *vm = &fpriv->vm;
	403	int r;
	404
	405	if (parser->chunk_ib_idx == -1)
	406	return 0;
	407
	408	if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
	409	return 0;
	410
dfcf5f36 AD	411	if ((rdev->family >= CHIP_TAHITI) &&
	412	(parser->chunk_const_ib_idx != -1)) {
	413	ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
	414	if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
	415	DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
	416	return -EINVAL;
	417	}
	418	r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
	419	ib_chunk->length_dw * 4);
	420	if (r) {
	421	DRM_ERROR("Failed to get const ib !\n");
	422	return r;
	423	}
f2e39221 JG	424	parser->const_ib.is_const_ib = true;
f2e39221 JG	425	parser->const_ib.length_dw = ib_chunk->length_dw;
dfcf5f36	426	/* Copy the packet into the IB */
f2e39221	427	if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
dfcf5f36 AD	428	ib_chunk->length_dw * 4)) {
	429	return -EFAULT;
	430	}
f2e39221	431	r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
dfcf5f36 AD	432	if (r) {
	433	return r;
	434	}
	435	}
	436
721604a1 JG	437	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	438	if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
	439	DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
	440	return -EINVAL;
	441	}
	442	r = radeon_ib_get(rdev, parser->ring, &parser->ib,
	443	ib_chunk->length_dw * 4);
	444	if (r) {
	445	DRM_ERROR("Failed to get ib !\n");
	446	return r;
	447	}
f2e39221	448	parser->ib.length_dw = ib_chunk->length_dw;
721604a1	449	/* Copy the packet into the IB */
f2e39221	450	if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
721604a1 JG	451	ib_chunk->length_dw * 4)) {
	452	return -EFAULT;
	453	}
f2e39221	454	r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
721604a1 JG	455	if (r) {
	456	return r;
	457	}
	458
	459	mutex_lock(&vm->mutex);
	460	r = radeon_vm_bind(rdev, vm);
	461	if (r) {
	462	goto out;
	463	}
	464	r = radeon_bo_vm_update_pte(parser, vm);
	465	if (r) {
	466	goto out;
	467	}
93504fce CK	468	r = radeon_cs_sync_rings(parser);
	469	if (r) {
	470	DRM_ERROR("Failed to synchronize rings !\n");
	471	}
dfcf5f36 AD	472
	473	if ((rdev->family >= CHIP_TAHITI) &&
	474	(parser->chunk_const_ib_idx != -1)) {
f2e39221	475	parser->const_ib.vm_id = vm->id;
dfcf5f36 AD	476	/* ib pool is bind at 0 in virtual address space to gpu_addr is the
	477	* offset inside the pool bo
	478	*/
f2e39221 JG	479	parser->const_ib.gpu_addr = parser->const_ib.sa_bo->soffset;
f2e39221 JG	480	r = radeon_ib_schedule(rdev, &parser->const_ib);
dfcf5f36 AD	481	if (r)
	482	goto out;
	483	}
	484
f2e39221	485	parser->ib.vm_id = vm->id;
721604a1 JG	486	/* ib pool is bind at 0 in virtual address space to gpu_addr is the
	487	* offset inside the pool bo
	488	*/
f2e39221 JG	489	parser->ib.gpu_addr = parser->ib.sa_bo->soffset;
	490	parser->ib.is_const_ib = false;
	491	r = radeon_ib_schedule(rdev, &parser->ib);
721604a1 JG	492	out:
	493	if (!r) {
	494	if (vm->fence) {
	495	radeon_fence_unref(&vm->fence);
	496	}
f2e39221	497	vm->fence = radeon_fence_ref(parser->ib.fence);
721604a1 JG	498	}
	499	mutex_unlock(&fpriv->vm.mutex);
	500	return r;
	501	}
	502
6c6f4783 CK	503	static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
	504	{
	505	if (r == -EDEADLK) {
	506	r = radeon_gpu_reset(rdev);
	507	if (!r)
	508	r = -EAGAIN;
	509	}
	510	return r;
	511	}
	512
771fe6b9 JG	513	int radeon_cs_ioctl(struct drm_device dev, void data, struct drm_file *filp)
	514	{
	515	struct radeon_device *rdev = dev->dev_private;
	516	struct radeon_cs_parser parser;
771fe6b9 JG	517	int r;
771fe6b9 JG	518
7a1619b9	519	radeon_mutex_lock(&rdev->cs_mutex);
6b7746e8 JG	520	if (!rdev->accel_working) {
	521	radeon_mutex_unlock(&rdev->cs_mutex);
	522	return -EBUSY;
	523	}
771fe6b9 JG	524	/* initialize parser */
	525	memset(&parser, 0, sizeof(struct radeon_cs_parser));
	526	parser.filp = filp;
	527	parser.rdev = rdev;
c8c15ff1	528	parser.dev = rdev->dev;
428c6e36	529	parser.family = rdev->family;
771fe6b9 JG	530	r = radeon_cs_parser_init(&parser, data);
	531	if (r) {
	532	DRM_ERROR("Failed to initialize parser !\n");
	533	radeon_cs_parser_fini(&parser, r);
6c6f4783	534	r = radeon_cs_handle_lockup(rdev, r);
7a1619b9	535	radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9 JG	536	return r;
771fe6b9 JG	537	}
771fe6b9 JG	538	r = radeon_cs_parser_relocs(&parser);
771fe6b9 JG	539	if (r) {
97f23b3d DA	540	if (r != -ERESTARTSYS)
97f23b3d DA	541	DRM_ERROR("Failed to parse relocation %d!\n", r);
771fe6b9	542	radeon_cs_parser_fini(&parser, r);
6c6f4783	543	r = radeon_cs_handle_lockup(rdev, r);
7a1619b9	544	radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9 JG	545	return r;
771fe6b9 JG	546	}
721604a1	547	r = radeon_cs_ib_chunk(rdev, &parser);
771fe6b9	548	if (r) {
721604a1	549	goto out;
771fe6b9	550	}
721604a1	551	r = radeon_cs_ib_vm_chunk(rdev, &parser);
771fe6b9	552	if (r) {
721604a1	553	goto out;
771fe6b9	554	}
721604a1	555	out:
771fe6b9	556	radeon_cs_parser_fini(&parser, r);
6c6f4783	557	r = radeon_cs_handle_lockup(rdev, r);
7a1619b9	558	radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9 JG	559	return r;
771fe6b9 JG	560	}
513bcb46 DA	561
	562	int radeon_cs_finish_pages(struct radeon_cs_parser *p)
	563	{
	564	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	565	int i;
	566	int size = PAGE_SIZE;
	567
	568	for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
	569	if (i == ibc->last_page_index) {
	570	size = (ibc->length_dw * 4) % PAGE_SIZE;
	571	if (size == 0)
	572	size = PAGE_SIZE;
	573	}
	574
f2e39221	575	if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
513bcb46 DA	576	ibc->user_ptr + (i * PAGE_SIZE),
	577	size))
	578	return -EFAULT;
	579	}
	580	return 0;
	581	}
	582
	583	int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
	584	{
	585	int new_page;
513bcb46 DA	586	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	587	int i;
	588	int size = PAGE_SIZE;
6a7068b4	589	bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true;
513bcb46	590
c5e617e2	591	for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
f2e39221	592	if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
513bcb46 DA	593	ibc->user_ptr + (i * PAGE_SIZE),
	594	PAGE_SIZE)) {
	595	p->parser_error = -EFAULT;
	596	return 0;
	597	}
	598	}
	599
513bcb46 DA	600	if (pg_idx == ibc->last_page_index) {
513bcb46 DA	601	size = (ibc->length_dw * 4) % PAGE_SIZE;
6a7068b4 DA	602	if (size == 0)
6a7068b4 DA	603	size = PAGE_SIZE;
513bcb46 DA	604	}
513bcb46 DA	605
6a7068b4 DA	606	new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
6a7068b4 DA	607	if (copy1)
f2e39221	608	ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));
6a7068b4	609
513bcb46 DA	610	if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
	611	ibc->user_ptr + (pg_idx * PAGE_SIZE),
	612	size)) {
	613	p->parser_error = -EFAULT;
	614	return 0;
	615	}
	616
6a7068b4 DA	617	/* copy to IB for non single case */
6a7068b4 DA	618	if (!copy1)
f2e39221	619	memcpy((void )(p->ib.ptr+(pg_idx(PAGE_SIZE/4))), ibc->kpage[new_page], size);
513bcb46 DA	620
	621	ibc->last_copied_page = pg_idx;
	622	ibc->kpage_idx[new_page] = pg_idx;
	623
	624	return new_page;
	625	}