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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/console.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
771fe6b9 JG |
30 | #include <drm/drmP.h> |
31 | #include <drm/drm_crtc_helper.h> | |
32 | #include <drm/radeon_drm.h> | |
28d52043 | 33 | #include <linux/vgaarb.h> |
6a9ee8af | 34 | #include <linux/vga_switcheroo.h> |
771fe6b9 JG |
35 | #include "radeon_reg.h" |
36 | #include "radeon.h" | |
771fe6b9 JG |
37 | #include "atom.h" |
38 | ||
1b5331d9 JG |
39 | static const char radeon_family_name[][16] = { |
40 | "R100", | |
41 | "RV100", | |
42 | "RS100", | |
43 | "RV200", | |
44 | "RS200", | |
45 | "R200", | |
46 | "RV250", | |
47 | "RS300", | |
48 | "RV280", | |
49 | "R300", | |
50 | "R350", | |
51 | "RV350", | |
52 | "RV380", | |
53 | "R420", | |
54 | "R423", | |
55 | "RV410", | |
56 | "RS400", | |
57 | "RS480", | |
58 | "RS600", | |
59 | "RS690", | |
60 | "RS740", | |
61 | "RV515", | |
62 | "R520", | |
63 | "RV530", | |
64 | "RV560", | |
65 | "RV570", | |
66 | "R580", | |
67 | "R600", | |
68 | "RV610", | |
69 | "RV630", | |
70 | "RV670", | |
71 | "RV620", | |
72 | "RV635", | |
73 | "RS780", | |
74 | "RS880", | |
75 | "RV770", | |
76 | "RV730", | |
77 | "RV710", | |
78 | "RV740", | |
79 | "CEDAR", | |
80 | "REDWOOD", | |
81 | "JUNIPER", | |
82 | "CYPRESS", | |
83 | "HEMLOCK", | |
84 | "LAST", | |
85 | }; | |
86 | ||
b1e3a6d1 MD |
87 | /* |
88 | * Clear GPU surface registers. | |
89 | */ | |
3ce0a23d | 90 | void radeon_surface_init(struct radeon_device *rdev) |
b1e3a6d1 MD |
91 | { |
92 | /* FIXME: check this out */ | |
93 | if (rdev->family < CHIP_R600) { | |
94 | int i; | |
95 | ||
550e2d92 DA |
96 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
97 | if (rdev->surface_regs[i].bo) | |
98 | radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); | |
99 | else | |
100 | radeon_clear_surface_reg(rdev, i); | |
b1e3a6d1 | 101 | } |
e024e110 DA |
102 | /* enable surfaces */ |
103 | WREG32(RADEON_SURFACE_CNTL, 0); | |
b1e3a6d1 MD |
104 | } |
105 | } | |
106 | ||
771fe6b9 JG |
107 | /* |
108 | * GPU scratch registers helpers function. | |
109 | */ | |
3ce0a23d | 110 | void radeon_scratch_init(struct radeon_device *rdev) |
771fe6b9 JG |
111 | { |
112 | int i; | |
113 | ||
114 | /* FIXME: check this out */ | |
115 | if (rdev->family < CHIP_R300) { | |
116 | rdev->scratch.num_reg = 5; | |
117 | } else { | |
118 | rdev->scratch.num_reg = 7; | |
119 | } | |
120 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
121 | rdev->scratch.free[i] = true; | |
122 | rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); | |
123 | } | |
124 | } | |
125 | ||
126 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) | |
127 | { | |
128 | int i; | |
129 | ||
130 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
131 | if (rdev->scratch.free[i]) { | |
132 | rdev->scratch.free[i] = false; | |
133 | *reg = rdev->scratch.reg[i]; | |
134 | return 0; | |
135 | } | |
136 | } | |
137 | return -EINVAL; | |
138 | } | |
139 | ||
140 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) | |
141 | { | |
142 | int i; | |
143 | ||
144 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
145 | if (rdev->scratch.reg[i] == reg) { | |
146 | rdev->scratch.free[i] = true; | |
147 | return; | |
148 | } | |
149 | } | |
150 | } | |
151 | ||
d594e46a JG |
152 | /** |
153 | * radeon_vram_location - try to find VRAM location | |
154 | * @rdev: radeon device structure holding all necessary informations | |
155 | * @mc: memory controller structure holding memory informations | |
156 | * @base: base address at which to put VRAM | |
157 | * | |
158 | * Function will place try to place VRAM at base address provided | |
159 | * as parameter (which is so far either PCI aperture address or | |
160 | * for IGP TOM base address). | |
161 | * | |
162 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
163 | * address space then we limit the VRAM size to the aperture. | |
164 | * | |
165 | * If we are using AGP and if the AGP aperture doesn't allow us to have | |
166 | * room for all the VRAM than we restrict the VRAM to the PCI aperture | |
167 | * size and print a warning. | |
168 | * | |
169 | * This function will never fails, worst case are limiting VRAM. | |
170 | * | |
171 | * Note: GTT start, end, size should be initialized before calling this | |
172 | * function on AGP platform. | |
173 | * | |
174 | * Note: We don't explictly enforce VRAM start to be aligned on VRAM size, | |
175 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
176 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
177 | * not IGP. | |
178 | * | |
179 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
180 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
181 | * Novell bug 204882 + along with lots of ubuntu ones | |
182 | * | |
183 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
184 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
185 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
186 | * ones) | |
187 | * | |
188 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
189 | * explicitly check for that thought. | |
190 | * | |
191 | * FIXME: when reducing VRAM size align new size on power of 2. | |
771fe6b9 | 192 | */ |
d594e46a | 193 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
771fe6b9 | 194 | { |
d594e46a JG |
195 | mc->vram_start = base; |
196 | if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { | |
197 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); | |
198 | mc->real_vram_size = mc->aper_size; | |
199 | mc->mc_vram_size = mc->aper_size; | |
200 | } | |
201 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
2cbeb4ef | 202 | if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { |
d594e46a JG |
203 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
204 | mc->real_vram_size = mc->aper_size; | |
205 | mc->mc_vram_size = mc->aper_size; | |
206 | } | |
207 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
208 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", | |
209 | mc->mc_vram_size >> 20, mc->vram_start, | |
210 | mc->vram_end, mc->real_vram_size >> 20); | |
211 | } | |
771fe6b9 | 212 | |
d594e46a JG |
213 | /** |
214 | * radeon_gtt_location - try to find GTT location | |
215 | * @rdev: radeon device structure holding all necessary informations | |
216 | * @mc: memory controller structure holding memory informations | |
217 | * | |
218 | * Function will place try to place GTT before or after VRAM. | |
219 | * | |
220 | * If GTT size is bigger than space left then we ajust GTT size. | |
221 | * Thus function will never fails. | |
222 | * | |
223 | * FIXME: when reducing GTT size align new size on power of 2. | |
224 | */ | |
225 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) | |
226 | { | |
227 | u64 size_af, size_bf; | |
228 | ||
8d369bb1 AD |
229 | size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; |
230 | size_bf = mc->vram_start & ~mc->gtt_base_align; | |
d594e46a JG |
231 | if (size_bf > size_af) { |
232 | if (mc->gtt_size > size_bf) { | |
233 | dev_warn(rdev->dev, "limiting GTT\n"); | |
234 | mc->gtt_size = size_bf; | |
771fe6b9 | 235 | } |
8d369bb1 | 236 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; |
771fe6b9 | 237 | } else { |
d594e46a JG |
238 | if (mc->gtt_size > size_af) { |
239 | dev_warn(rdev->dev, "limiting GTT\n"); | |
240 | mc->gtt_size = size_af; | |
241 | } | |
8d369bb1 | 242 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; |
771fe6b9 | 243 | } |
d594e46a JG |
244 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; |
245 | dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n", | |
246 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); | |
771fe6b9 JG |
247 | } |
248 | ||
771fe6b9 JG |
249 | /* |
250 | * GPU helpers function. | |
251 | */ | |
9f022ddf | 252 | bool radeon_card_posted(struct radeon_device *rdev) |
771fe6b9 JG |
253 | { |
254 | uint32_t reg; | |
255 | ||
256 | /* first check CRTCs */ | |
bcc1c2a1 AD |
257 | if (ASIC_IS_DCE4(rdev)) { |
258 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | | |
259 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | | |
260 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | | |
261 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | | |
262 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | | |
263 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); | |
264 | if (reg & EVERGREEN_CRTC_MASTER_EN) | |
265 | return true; | |
266 | } else if (ASIC_IS_AVIVO(rdev)) { | |
771fe6b9 JG |
267 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
268 | RREG32(AVIVO_D2CRTC_CONTROL); | |
269 | if (reg & AVIVO_CRTC_EN) { | |
270 | return true; | |
271 | } | |
272 | } else { | |
273 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | | |
274 | RREG32(RADEON_CRTC2_GEN_CNTL); | |
275 | if (reg & RADEON_CRTC_EN) { | |
276 | return true; | |
277 | } | |
278 | } | |
279 | ||
280 | /* then check MEM_SIZE, in case the crtcs are off */ | |
281 | if (rdev->family >= CHIP_R600) | |
282 | reg = RREG32(R600_CONFIG_MEMSIZE); | |
283 | else | |
284 | reg = RREG32(RADEON_CONFIG_MEMSIZE); | |
285 | ||
286 | if (reg) | |
287 | return true; | |
288 | ||
289 | return false; | |
290 | ||
291 | } | |
292 | ||
f47299c5 AD |
293 | void radeon_update_bandwidth_info(struct radeon_device *rdev) |
294 | { | |
295 | fixed20_12 a; | |
8807286e AD |
296 | u32 sclk = rdev->pm.current_sclk; |
297 | u32 mclk = rdev->pm.current_mclk; | |
f47299c5 | 298 | |
8807286e AD |
299 | /* sclk/mclk in Mhz */ |
300 | a.full = dfixed_const(100); | |
301 | rdev->pm.sclk.full = dfixed_const(sclk); | |
302 | rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); | |
303 | rdev->pm.mclk.full = dfixed_const(mclk); | |
304 | rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); | |
f47299c5 | 305 | |
8807286e | 306 | if (rdev->flags & RADEON_IS_IGP) { |
68adac5e | 307 | a.full = dfixed_const(16); |
f47299c5 | 308 | /* core_bandwidth = sclk(Mhz) * 16 */ |
68adac5e | 309 | rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); |
f47299c5 AD |
310 | } |
311 | } | |
312 | ||
72542d77 DA |
313 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
314 | { | |
315 | if (radeon_card_posted(rdev)) | |
316 | return true; | |
317 | ||
318 | if (rdev->bios) { | |
319 | DRM_INFO("GPU not posted. posting now...\n"); | |
320 | if (rdev->is_atom_bios) | |
321 | atom_asic_init(rdev->mode_info.atom_context); | |
322 | else | |
323 | radeon_combios_asic_init(rdev->ddev); | |
324 | return true; | |
325 | } else { | |
326 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); | |
327 | return false; | |
328 | } | |
329 | } | |
330 | ||
3ce0a23d JG |
331 | int radeon_dummy_page_init(struct radeon_device *rdev) |
332 | { | |
82568565 DA |
333 | if (rdev->dummy_page.page) |
334 | return 0; | |
3ce0a23d JG |
335 | rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); |
336 | if (rdev->dummy_page.page == NULL) | |
337 | return -ENOMEM; | |
338 | rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, | |
339 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
a30f6fb7 BH |
340 | if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) { |
341 | dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
3ce0a23d JG |
342 | __free_page(rdev->dummy_page.page); |
343 | rdev->dummy_page.page = NULL; | |
344 | return -ENOMEM; | |
345 | } | |
346 | return 0; | |
347 | } | |
348 | ||
349 | void radeon_dummy_page_fini(struct radeon_device *rdev) | |
350 | { | |
351 | if (rdev->dummy_page.page == NULL) | |
352 | return; | |
353 | pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, | |
354 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
355 | __free_page(rdev->dummy_page.page); | |
356 | rdev->dummy_page.page = NULL; | |
357 | } | |
358 | ||
771fe6b9 | 359 | |
771fe6b9 JG |
360 | /* ATOM accessor methods */ |
361 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
362 | { | |
363 | struct radeon_device *rdev = info->dev->dev_private; | |
364 | uint32_t r; | |
365 | ||
366 | r = rdev->pll_rreg(rdev, reg); | |
367 | return r; | |
368 | } | |
369 | ||
370 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
371 | { | |
372 | struct radeon_device *rdev = info->dev->dev_private; | |
373 | ||
374 | rdev->pll_wreg(rdev, reg, val); | |
375 | } | |
376 | ||
377 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
378 | { | |
379 | struct radeon_device *rdev = info->dev->dev_private; | |
380 | uint32_t r; | |
381 | ||
382 | r = rdev->mc_rreg(rdev, reg); | |
383 | return r; | |
384 | } | |
385 | ||
386 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
387 | { | |
388 | struct radeon_device *rdev = info->dev->dev_private; | |
389 | ||
390 | rdev->mc_wreg(rdev, reg, val); | |
391 | } | |
392 | ||
393 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
394 | { | |
395 | struct radeon_device *rdev = info->dev->dev_private; | |
396 | ||
397 | WREG32(reg*4, val); | |
398 | } | |
399 | ||
400 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
401 | { | |
402 | struct radeon_device *rdev = info->dev->dev_private; | |
403 | uint32_t r; | |
404 | ||
405 | r = RREG32(reg*4); | |
406 | return r; | |
407 | } | |
408 | ||
351a52a2 AD |
409 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) |
410 | { | |
411 | struct radeon_device *rdev = info->dev->dev_private; | |
412 | ||
413 | WREG32_IO(reg*4, val); | |
414 | } | |
415 | ||
416 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
417 | { | |
418 | struct radeon_device *rdev = info->dev->dev_private; | |
419 | uint32_t r; | |
420 | ||
421 | r = RREG32_IO(reg*4); | |
422 | return r; | |
423 | } | |
424 | ||
771fe6b9 JG |
425 | int radeon_atombios_init(struct radeon_device *rdev) |
426 | { | |
61c4b24b MF |
427 | struct card_info *atom_card_info = |
428 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
429 | ||
430 | if (!atom_card_info) | |
431 | return -ENOMEM; | |
432 | ||
433 | rdev->mode_info.atom_card_info = atom_card_info; | |
434 | atom_card_info->dev = rdev->ddev; | |
435 | atom_card_info->reg_read = cail_reg_read; | |
436 | atom_card_info->reg_write = cail_reg_write; | |
351a52a2 AD |
437 | /* needed for iio ops */ |
438 | if (rdev->rio_mem) { | |
439 | atom_card_info->ioreg_read = cail_ioreg_read; | |
440 | atom_card_info->ioreg_write = cail_ioreg_write; | |
441 | } else { | |
442 | DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); | |
443 | atom_card_info->ioreg_read = cail_reg_read; | |
444 | atom_card_info->ioreg_write = cail_reg_write; | |
445 | } | |
61c4b24b MF |
446 | atom_card_info->mc_read = cail_mc_read; |
447 | atom_card_info->mc_write = cail_mc_write; | |
448 | atom_card_info->pll_read = cail_pll_read; | |
449 | atom_card_info->pll_write = cail_pll_write; | |
450 | ||
451 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); | |
c31ad97f | 452 | mutex_init(&rdev->mode_info.atom_context->mutex); |
771fe6b9 | 453 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
d904ef9b | 454 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
771fe6b9 JG |
455 | return 0; |
456 | } | |
457 | ||
458 | void radeon_atombios_fini(struct radeon_device *rdev) | |
459 | { | |
4a04a844 JG |
460 | if (rdev->mode_info.atom_context) { |
461 | kfree(rdev->mode_info.atom_context->scratch); | |
462 | kfree(rdev->mode_info.atom_context); | |
463 | } | |
61c4b24b | 464 | kfree(rdev->mode_info.atom_card_info); |
771fe6b9 JG |
465 | } |
466 | ||
467 | int radeon_combios_init(struct radeon_device *rdev) | |
468 | { | |
469 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); | |
470 | return 0; | |
471 | } | |
472 | ||
473 | void radeon_combios_fini(struct radeon_device *rdev) | |
474 | { | |
475 | } | |
476 | ||
28d52043 DA |
477 | /* if we get transitioned to only one device, tak VGA back */ |
478 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) | |
479 | { | |
480 | struct radeon_device *rdev = cookie; | |
28d52043 DA |
481 | radeon_vga_set_state(rdev, state); |
482 | if (state) | |
483 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
484 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
485 | else | |
486 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
487 | } | |
c1176d6f | 488 | |
36421338 JG |
489 | void radeon_check_arguments(struct radeon_device *rdev) |
490 | { | |
491 | /* vramlimit must be a power of two */ | |
492 | switch (radeon_vram_limit) { | |
493 | case 0: | |
494 | case 4: | |
495 | case 8: | |
496 | case 16: | |
497 | case 32: | |
498 | case 64: | |
499 | case 128: | |
500 | case 256: | |
501 | case 512: | |
502 | case 1024: | |
503 | case 2048: | |
504 | case 4096: | |
505 | break; | |
506 | default: | |
507 | dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", | |
508 | radeon_vram_limit); | |
509 | radeon_vram_limit = 0; | |
510 | break; | |
511 | } | |
512 | radeon_vram_limit = radeon_vram_limit << 20; | |
513 | /* gtt size must be power of two and greater or equal to 32M */ | |
514 | switch (radeon_gart_size) { | |
515 | case 4: | |
516 | case 8: | |
517 | case 16: | |
518 | dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", | |
519 | radeon_gart_size); | |
520 | radeon_gart_size = 512; | |
521 | break; | |
522 | case 32: | |
523 | case 64: | |
524 | case 128: | |
525 | case 256: | |
526 | case 512: | |
527 | case 1024: | |
528 | case 2048: | |
529 | case 4096: | |
530 | break; | |
531 | default: | |
532 | dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", | |
533 | radeon_gart_size); | |
534 | radeon_gart_size = 512; | |
535 | break; | |
536 | } | |
537 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
538 | /* AGP mode can only be -1, 1, 2, 4, 8 */ | |
539 | switch (radeon_agpmode) { | |
540 | case -1: | |
541 | case 0: | |
542 | case 1: | |
543 | case 2: | |
544 | case 4: | |
545 | case 8: | |
546 | break; | |
547 | default: | |
548 | dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " | |
549 | "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); | |
550 | radeon_agpmode = 0; | |
551 | break; | |
552 | } | |
553 | } | |
554 | ||
6a9ee8af DA |
555 | static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
556 | { | |
557 | struct drm_device *dev = pci_get_drvdata(pdev); | |
558 | struct radeon_device *rdev = dev->dev_private; | |
559 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
560 | if (state == VGA_SWITCHEROO_ON) { | |
561 | printk(KERN_INFO "radeon: switched on\n"); | |
562 | /* don't suspend or resume card normally */ | |
563 | rdev->powered_down = false; | |
564 | radeon_resume_kms(dev); | |
fbf81762 | 565 | drm_kms_helper_poll_enable(dev); |
6a9ee8af DA |
566 | } else { |
567 | printk(KERN_INFO "radeon: switched off\n"); | |
fbf81762 | 568 | drm_kms_helper_poll_disable(dev); |
6a9ee8af DA |
569 | radeon_suspend_kms(dev, pmm); |
570 | /* don't suspend or resume card normally */ | |
571 | rdev->powered_down = true; | |
572 | } | |
573 | } | |
574 | ||
575 | static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) | |
576 | { | |
577 | struct drm_device *dev = pci_get_drvdata(pdev); | |
578 | bool can_switch; | |
579 | ||
580 | spin_lock(&dev->count_lock); | |
581 | can_switch = (dev->open_count == 0); | |
582 | spin_unlock(&dev->count_lock); | |
583 | return can_switch; | |
584 | } | |
585 | ||
586 | ||
771fe6b9 JG |
587 | int radeon_device_init(struct radeon_device *rdev, |
588 | struct drm_device *ddev, | |
589 | struct pci_dev *pdev, | |
590 | uint32_t flags) | |
591 | { | |
351a52a2 | 592 | int r, i; |
ad49f501 | 593 | int dma_bits; |
771fe6b9 | 594 | |
771fe6b9 | 595 | rdev->shutdown = false; |
9f022ddf | 596 | rdev->dev = &pdev->dev; |
771fe6b9 JG |
597 | rdev->ddev = ddev; |
598 | rdev->pdev = pdev; | |
599 | rdev->flags = flags; | |
600 | rdev->family = flags & RADEON_FAMILY_MASK; | |
601 | rdev->is_atom_bios = false; | |
602 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; | |
603 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
604 | rdev->gpu_lockup = false; | |
733289c2 | 605 | rdev->accel_working = false; |
1b5331d9 JG |
606 | |
607 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n", | |
608 | radeon_family_name[rdev->family], pdev->vendor, pdev->device); | |
609 | ||
771fe6b9 JG |
610 | /* mutex initialization are all done here so we |
611 | * can recall function without having locking issues */ | |
612 | mutex_init(&rdev->cs_mutex); | |
613 | mutex_init(&rdev->ib_pool.mutex); | |
614 | mutex_init(&rdev->cp.mutex); | |
40bacf16 | 615 | mutex_init(&rdev->dc_hw_i2c_mutex); |
d8f60cfc AD |
616 | if (rdev->family >= CHIP_R600) |
617 | spin_lock_init(&rdev->ih.lock); | |
4c788679 | 618 | mutex_init(&rdev->gem.mutex); |
c913e23a | 619 | mutex_init(&rdev->pm.mutex); |
5876dd24 | 620 | mutex_init(&rdev->vram_mutex); |
771fe6b9 | 621 | rwlock_init(&rdev->fence_drv.lock); |
9f022ddf | 622 | INIT_LIST_HEAD(&rdev->gem.objects); |
73a6d3fc | 623 | init_waitqueue_head(&rdev->irq.vblank_queue); |
2031f77c | 624 | init_waitqueue_head(&rdev->irq.idle_queue); |
771fe6b9 | 625 | |
d4877cf2 AD |
626 | /* setup workqueue */ |
627 | rdev->wq = create_workqueue("radeon"); | |
628 | if (rdev->wq == NULL) | |
629 | return -ENOMEM; | |
630 | ||
4aac0473 JG |
631 | /* Set asic functions */ |
632 | r = radeon_asic_init(rdev); | |
36421338 | 633 | if (r) |
4aac0473 | 634 | return r; |
36421338 | 635 | radeon_check_arguments(rdev); |
4aac0473 | 636 | |
f95df9ca AD |
637 | /* all of the newer IGP chips have an internal gart |
638 | * However some rs4xx report as AGP, so remove that here. | |
639 | */ | |
640 | if ((rdev->family >= CHIP_RS400) && | |
641 | (rdev->flags & RADEON_IS_IGP)) { | |
642 | rdev->flags &= ~RADEON_IS_AGP; | |
643 | } | |
644 | ||
30256a3f | 645 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
b574f251 | 646 | radeon_agp_disable(rdev); |
771fe6b9 JG |
647 | } |
648 | ||
ad49f501 DA |
649 | /* set DMA mask + need_dma32 flags. |
650 | * PCIE - can handle 40-bits. | |
651 | * IGP - can handle 40-bits (in theory) | |
652 | * AGP - generally dma32 is safest | |
653 | * PCI - only dma32 | |
654 | */ | |
655 | rdev->need_dma32 = false; | |
656 | if (rdev->flags & RADEON_IS_AGP) | |
657 | rdev->need_dma32 = true; | |
658 | if (rdev->flags & RADEON_IS_PCI) | |
659 | rdev->need_dma32 = true; | |
660 | ||
661 | dma_bits = rdev->need_dma32 ? 32 : 40; | |
662 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); | |
771fe6b9 JG |
663 | if (r) { |
664 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); | |
665 | } | |
666 | ||
667 | /* Registers mapping */ | |
668 | /* TODO: block userspace mapping of io register */ | |
01d73a69 JC |
669 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); |
670 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); | |
771fe6b9 JG |
671 | rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); |
672 | if (rdev->rmmio == NULL) { | |
673 | return -ENOMEM; | |
674 | } | |
675 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); | |
676 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); | |
677 | ||
351a52a2 AD |
678 | /* io port mapping */ |
679 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
680 | if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { | |
681 | rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); | |
682 | rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); | |
683 | break; | |
684 | } | |
685 | } | |
686 | if (rdev->rio_mem == NULL) | |
687 | DRM_ERROR("Unable to find PCI I/O BAR\n"); | |
688 | ||
28d52043 | 689 | /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
93239ea1 DA |
690 | /* this will fail for cards that aren't VGA class devices, just |
691 | * ignore it */ | |
692 | vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); | |
6a9ee8af DA |
693 | vga_switcheroo_register_client(rdev->pdev, |
694 | radeon_switcheroo_set_state, | |
695 | radeon_switcheroo_can_switch); | |
28d52043 | 696 | |
3ce0a23d | 697 | r = radeon_init(rdev); |
b574f251 | 698 | if (r) |
3ce0a23d | 699 | return r; |
3ce0a23d | 700 | |
b574f251 JG |
701 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
702 | /* Acceleration not working on AGP card try again | |
703 | * with fallback to PCI or PCIE GART | |
704 | */ | |
a2d07b74 | 705 | radeon_asic_reset(rdev); |
b574f251 JG |
706 | radeon_fini(rdev); |
707 | radeon_agp_disable(rdev); | |
708 | r = radeon_init(rdev); | |
4aac0473 JG |
709 | if (r) |
710 | return r; | |
771fe6b9 | 711 | } |
ecc0b326 MD |
712 | if (radeon_testing) { |
713 | radeon_test_moves(rdev); | |
714 | } | |
771fe6b9 JG |
715 | if (radeon_benchmarking) { |
716 | radeon_benchmark(rdev); | |
717 | } | |
6cf8a3f5 | 718 | return 0; |
771fe6b9 JG |
719 | } |
720 | ||
721 | void radeon_device_fini(struct radeon_device *rdev) | |
722 | { | |
771fe6b9 JG |
723 | DRM_INFO("radeon: finishing device.\n"); |
724 | rdev->shutdown = true; | |
90aca4d2 JG |
725 | /* evict vram memory */ |
726 | radeon_bo_evict_vram(rdev); | |
62a8ea3f | 727 | radeon_fini(rdev); |
d4877cf2 | 728 | destroy_workqueue(rdev->wq); |
6a9ee8af | 729 | vga_switcheroo_unregister_client(rdev->pdev); |
c1176d6f | 730 | vga_client_register(rdev->pdev, NULL, NULL, NULL); |
e0a2ca73 AD |
731 | if (rdev->rio_mem) |
732 | pci_iounmap(rdev->pdev, rdev->rio_mem); | |
351a52a2 | 733 | rdev->rio_mem = NULL; |
771fe6b9 JG |
734 | iounmap(rdev->rmmio); |
735 | rdev->rmmio = NULL; | |
736 | } | |
737 | ||
738 | ||
739 | /* | |
740 | * Suspend & resume. | |
741 | */ | |
742 | int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) | |
743 | { | |
875c1866 | 744 | struct radeon_device *rdev; |
771fe6b9 | 745 | struct drm_crtc *crtc; |
d8dcaa1d | 746 | struct drm_connector *connector; |
4c788679 | 747 | int r; |
771fe6b9 | 748 | |
875c1866 | 749 | if (dev == NULL || dev->dev_private == NULL) { |
771fe6b9 JG |
750 | return -ENODEV; |
751 | } | |
752 | if (state.event == PM_EVENT_PRETHAW) { | |
753 | return 0; | |
754 | } | |
875c1866 DJ |
755 | rdev = dev->dev_private; |
756 | ||
6a9ee8af DA |
757 | if (rdev->powered_down) |
758 | return 0; | |
d8dcaa1d AD |
759 | |
760 | /* turn off display hw */ | |
761 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
762 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
763 | } | |
764 | ||
771fe6b9 JG |
765 | /* unpin the front buffers */ |
766 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
767 | struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); | |
4c788679 | 768 | struct radeon_bo *robj; |
771fe6b9 JG |
769 | |
770 | if (rfb == NULL || rfb->obj == NULL) { | |
771 | continue; | |
772 | } | |
773 | robj = rfb->obj->driver_private; | |
38651674 DA |
774 | /* don't unpin kernel fb objects */ |
775 | if (!radeon_fbdev_robj_is_fb(rdev, robj)) { | |
4c788679 | 776 | r = radeon_bo_reserve(robj, false); |
38651674 | 777 | if (r == 0) { |
4c788679 JG |
778 | radeon_bo_unpin(robj); |
779 | radeon_bo_unreserve(robj); | |
780 | } | |
771fe6b9 JG |
781 | } |
782 | } | |
783 | /* evict vram memory */ | |
4c788679 | 784 | radeon_bo_evict_vram(rdev); |
771fe6b9 JG |
785 | /* wait for gpu to finish processing current batch */ |
786 | radeon_fence_wait_last(rdev); | |
787 | ||
f657c2a7 YZ |
788 | radeon_save_bios_scratch_regs(rdev); |
789 | ||
ce8f5370 | 790 | radeon_pm_suspend(rdev); |
62a8ea3f | 791 | radeon_suspend(rdev); |
d4877cf2 | 792 | radeon_hpd_fini(rdev); |
771fe6b9 | 793 | /* evict remaining vram memory */ |
4c788679 | 794 | radeon_bo_evict_vram(rdev); |
771fe6b9 | 795 | |
10b06122 JG |
796 | radeon_agp_suspend(rdev); |
797 | ||
771fe6b9 JG |
798 | pci_save_state(dev->pdev); |
799 | if (state.event == PM_EVENT_SUSPEND) { | |
800 | /* Shut down the device */ | |
801 | pci_disable_device(dev->pdev); | |
802 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
803 | } | |
804 | acquire_console_sem(); | |
38651674 | 805 | radeon_fbdev_set_suspend(rdev, 1); |
771fe6b9 JG |
806 | release_console_sem(); |
807 | return 0; | |
808 | } | |
809 | ||
810 | int radeon_resume_kms(struct drm_device *dev) | |
811 | { | |
09bdf591 | 812 | struct drm_connector *connector; |
771fe6b9 | 813 | struct radeon_device *rdev = dev->dev_private; |
771fe6b9 | 814 | |
6a9ee8af DA |
815 | if (rdev->powered_down) |
816 | return 0; | |
817 | ||
771fe6b9 JG |
818 | acquire_console_sem(); |
819 | pci_set_power_state(dev->pdev, PCI_D0); | |
820 | pci_restore_state(dev->pdev); | |
821 | if (pci_enable_device(dev->pdev)) { | |
822 | release_console_sem(); | |
823 | return -1; | |
824 | } | |
825 | pci_set_master(dev->pdev); | |
0ebf1717 DA |
826 | /* resume AGP if in use */ |
827 | radeon_agp_resume(rdev); | |
62a8ea3f | 828 | radeon_resume(rdev); |
ce8f5370 | 829 | radeon_pm_resume(rdev); |
f657c2a7 | 830 | radeon_restore_bios_scratch_regs(rdev); |
09bdf591 CG |
831 | |
832 | /* turn on display hw */ | |
833 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
834 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
835 | } | |
836 | ||
38651674 | 837 | radeon_fbdev_set_suspend(rdev, 0); |
771fe6b9 JG |
838 | release_console_sem(); |
839 | ||
d4877cf2 AD |
840 | /* reset hpd state */ |
841 | radeon_hpd_init(rdev); | |
771fe6b9 JG |
842 | /* blat the mode back in */ |
843 | drm_helper_resume_force_mode(dev); | |
844 | return 0; | |
845 | } | |
846 | ||
90aca4d2 JG |
847 | int radeon_gpu_reset(struct radeon_device *rdev) |
848 | { | |
849 | int r; | |
850 | ||
851 | radeon_save_bios_scratch_regs(rdev); | |
852 | radeon_suspend(rdev); | |
853 | ||
854 | r = radeon_asic_reset(rdev); | |
855 | if (!r) { | |
856 | dev_info(rdev->dev, "GPU reset succeed\n"); | |
857 | radeon_resume(rdev); | |
858 | radeon_restore_bios_scratch_regs(rdev); | |
859 | drm_helper_resume_force_mode(rdev->ddev); | |
860 | return 0; | |
861 | } | |
862 | /* bad news, how to tell it to userspace ? */ | |
863 | dev_info(rdev->dev, "GPU reset failed\n"); | |
864 | return r; | |
865 | } | |
866 | ||
771fe6b9 JG |
867 | |
868 | /* | |
869 | * Debugfs | |
870 | */ | |
871 | struct radeon_debugfs { | |
872 | struct drm_info_list *files; | |
873 | unsigned num_files; | |
874 | }; | |
875 | static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES]; | |
876 | static unsigned _radeon_debugfs_count = 0; | |
877 | ||
878 | int radeon_debugfs_add_files(struct radeon_device *rdev, | |
879 | struct drm_info_list *files, | |
880 | unsigned nfiles) | |
881 | { | |
882 | unsigned i; | |
883 | ||
884 | for (i = 0; i < _radeon_debugfs_count; i++) { | |
885 | if (_radeon_debugfs[i].files == files) { | |
886 | /* Already registered */ | |
887 | return 0; | |
888 | } | |
889 | } | |
890 | if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) { | |
891 | DRM_ERROR("Reached maximum number of debugfs files.\n"); | |
892 | DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n"); | |
893 | return -EINVAL; | |
894 | } | |
895 | _radeon_debugfs[_radeon_debugfs_count].files = files; | |
896 | _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles; | |
897 | _radeon_debugfs_count++; | |
898 | #if defined(CONFIG_DEBUG_FS) | |
899 | drm_debugfs_create_files(files, nfiles, | |
900 | rdev->ddev->control->debugfs_root, | |
901 | rdev->ddev->control); | |
902 | drm_debugfs_create_files(files, nfiles, | |
903 | rdev->ddev->primary->debugfs_root, | |
904 | rdev->ddev->primary); | |
905 | #endif | |
906 | return 0; | |
907 | } | |
908 | ||
909 | #if defined(CONFIG_DEBUG_FS) | |
910 | int radeon_debugfs_init(struct drm_minor *minor) | |
911 | { | |
912 | return 0; | |
913 | } | |
914 | ||
915 | void radeon_debugfs_cleanup(struct drm_minor *minor) | |
916 | { | |
917 | unsigned i; | |
918 | ||
919 | for (i = 0; i < _radeon_debugfs_count; i++) { | |
920 | drm_debugfs_remove_files(_radeon_debugfs[i].files, | |
921 | _radeon_debugfs[i].num_files, minor); | |
922 | } | |
923 | } | |
924 | #endif |