Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
760285e7 DH |
26 | #include <drm/drmP.h> |
27 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
28 | #include "radeon.h" |
29 | ||
30 | #include "atom.h" | |
31 | #include <asm/div64.h> | |
32 | ||
760285e7 DH |
33 | #include <drm/drm_crtc_helper.h> |
34 | #include <drm/drm_edid.h> | |
771fe6b9 | 35 | |
771fe6b9 JG |
36 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) |
37 | { | |
38 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
39 | struct drm_device *dev = crtc->dev; | |
40 | struct radeon_device *rdev = dev->dev_private; | |
41 | int i; | |
42 | ||
d9fdaafb | 43 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
771fe6b9 JG |
44 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
45 | ||
46 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); | |
47 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); | |
48 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); | |
49 | ||
50 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); | |
51 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); | |
52 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); | |
53 | ||
54 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); | |
55 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); | |
56 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); | |
57 | ||
58 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); | |
59 | for (i = 0; i < 256; i++) { | |
60 | WREG32(AVIVO_DC_LUT_30_COLOR, | |
61 | (radeon_crtc->lut_r[i] << 20) | | |
62 | (radeon_crtc->lut_g[i] << 10) | | |
63 | (radeon_crtc->lut_b[i] << 0)); | |
64 | } | |
65 | ||
66 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); | |
67 | } | |
68 | ||
fee298fd | 69 | static void dce4_crtc_load_lut(struct drm_crtc *crtc) |
bcc1c2a1 AD |
70 | { |
71 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
72 | struct drm_device *dev = crtc->dev; | |
73 | struct radeon_device *rdev = dev->dev_private; | |
74 | int i; | |
75 | ||
d9fdaafb | 76 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
bcc1c2a1 AD |
77 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
78 | ||
79 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); | |
80 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); | |
81 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); | |
82 | ||
83 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); | |
84 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); | |
85 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); | |
86 | ||
677d0768 AD |
87 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
88 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); | |
bcc1c2a1 | 89 | |
677d0768 | 90 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
bcc1c2a1 | 91 | for (i = 0; i < 256; i++) { |
677d0768 | 92 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
bcc1c2a1 AD |
93 | (radeon_crtc->lut_r[i] << 20) | |
94 | (radeon_crtc->lut_g[i] << 10) | | |
95 | (radeon_crtc->lut_b[i] << 0)); | |
96 | } | |
97 | } | |
98 | ||
fee298fd AD |
99 | static void dce5_crtc_load_lut(struct drm_crtc *crtc) |
100 | { | |
101 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
102 | struct drm_device *dev = crtc->dev; | |
103 | struct radeon_device *rdev = dev->dev_private; | |
104 | int i; | |
105 | ||
106 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); | |
107 | ||
108 | WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, | |
109 | (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | | |
110 | NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); | |
111 | WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, | |
112 | NI_GRPH_PRESCALE_BYPASS); | |
113 | WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, | |
114 | NI_OVL_PRESCALE_BYPASS); | |
115 | WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, | |
116 | (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | | |
117 | NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); | |
118 | ||
119 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); | |
120 | ||
121 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); | |
122 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); | |
123 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); | |
124 | ||
125 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); | |
126 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); | |
127 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); | |
128 | ||
129 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); | |
130 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); | |
131 | ||
132 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); | |
133 | for (i = 0; i < 256; i++) { | |
134 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, | |
135 | (radeon_crtc->lut_r[i] << 20) | | |
136 | (radeon_crtc->lut_g[i] << 10) | | |
137 | (radeon_crtc->lut_b[i] << 0)); | |
138 | } | |
139 | ||
140 | WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, | |
141 | (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | | |
142 | NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | | |
143 | NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | | |
144 | NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); | |
145 | WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, | |
146 | (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | | |
147 | NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); | |
148 | WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, | |
149 | (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | | |
150 | NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); | |
151 | WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, | |
152 | (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) | | |
153 | NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); | |
154 | /* XXX match this to the depth of the crtc fmt block, move to modeset? */ | |
155 | WREG32(0x6940 + radeon_crtc->crtc_offset, 0); | |
156 | ||
157 | } | |
158 | ||
771fe6b9 JG |
159 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
160 | { | |
161 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
162 | struct drm_device *dev = crtc->dev; | |
163 | struct radeon_device *rdev = dev->dev_private; | |
164 | int i; | |
165 | uint32_t dac2_cntl; | |
166 | ||
167 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); | |
168 | if (radeon_crtc->crtc_id == 0) | |
169 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; | |
170 | else | |
171 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; | |
172 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); | |
173 | ||
174 | WREG8(RADEON_PALETTE_INDEX, 0); | |
175 | for (i = 0; i < 256; i++) { | |
176 | WREG32(RADEON_PALETTE_30_DATA, | |
177 | (radeon_crtc->lut_r[i] << 20) | | |
178 | (radeon_crtc->lut_g[i] << 10) | | |
179 | (radeon_crtc->lut_b[i] << 0)); | |
180 | } | |
181 | } | |
182 | ||
183 | void radeon_crtc_load_lut(struct drm_crtc *crtc) | |
184 | { | |
185 | struct drm_device *dev = crtc->dev; | |
186 | struct radeon_device *rdev = dev->dev_private; | |
187 | ||
188 | if (!crtc->enabled) | |
189 | return; | |
190 | ||
fee298fd AD |
191 | if (ASIC_IS_DCE5(rdev)) |
192 | dce5_crtc_load_lut(crtc); | |
193 | else if (ASIC_IS_DCE4(rdev)) | |
194 | dce4_crtc_load_lut(crtc); | |
bcc1c2a1 | 195 | else if (ASIC_IS_AVIVO(rdev)) |
771fe6b9 JG |
196 | avivo_crtc_load_lut(crtc); |
197 | else | |
198 | legacy_crtc_load_lut(crtc); | |
199 | } | |
200 | ||
b8c00ac5 | 201 | /** Sets the color ramps on behalf of fbcon */ |
771fe6b9 JG |
202 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
203 | u16 blue, int regno) | |
204 | { | |
205 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
206 | ||
771fe6b9 JG |
207 | radeon_crtc->lut_r[regno] = red >> 6; |
208 | radeon_crtc->lut_g[regno] = green >> 6; | |
209 | radeon_crtc->lut_b[regno] = blue >> 6; | |
210 | } | |
211 | ||
b8c00ac5 DA |
212 | /** Gets the color ramps on behalf of fbcon */ |
213 | void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, | |
214 | u16 *blue, int regno) | |
215 | { | |
216 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
217 | ||
218 | *red = radeon_crtc->lut_r[regno] << 6; | |
219 | *green = radeon_crtc->lut_g[regno] << 6; | |
220 | *blue = radeon_crtc->lut_b[regno] << 6; | |
221 | } | |
222 | ||
771fe6b9 | 223 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 224 | u16 *blue, uint32_t start, uint32_t size) |
771fe6b9 JG |
225 | { |
226 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
7203425a | 227 | int end = (start + size > 256) ? 256 : start + size, i; |
771fe6b9 | 228 | |
b8c00ac5 | 229 | /* userspace palettes are always correct as is */ |
7203425a | 230 | for (i = start; i < end; i++) { |
b8c00ac5 DA |
231 | radeon_crtc->lut_r[i] = red[i] >> 6; |
232 | radeon_crtc->lut_g[i] = green[i] >> 6; | |
233 | radeon_crtc->lut_b[i] = blue[i] >> 6; | |
771fe6b9 | 234 | } |
771fe6b9 JG |
235 | radeon_crtc_load_lut(crtc); |
236 | } | |
237 | ||
238 | static void radeon_crtc_destroy(struct drm_crtc *crtc) | |
239 | { | |
240 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
241 | ||
771fe6b9 JG |
242 | drm_crtc_cleanup(crtc); |
243 | kfree(radeon_crtc); | |
244 | } | |
245 | ||
6f34be50 AD |
246 | /* |
247 | * Handle unpin events outside the interrupt handler proper. | |
248 | */ | |
249 | static void radeon_unpin_work_func(struct work_struct *__work) | |
250 | { | |
251 | struct radeon_unpin_work *work = | |
252 | container_of(__work, struct radeon_unpin_work, work); | |
253 | int r; | |
254 | ||
255 | /* unpin of the old buffer */ | |
256 | r = radeon_bo_reserve(work->old_rbo, false); | |
257 | if (likely(r == 0)) { | |
258 | r = radeon_bo_unpin(work->old_rbo); | |
259 | if (unlikely(r != 0)) { | |
260 | DRM_ERROR("failed to unpin buffer after flip\n"); | |
261 | } | |
262 | radeon_bo_unreserve(work->old_rbo); | |
263 | } else | |
264 | DRM_ERROR("failed to reserve buffer after flip\n"); | |
498c555f DA |
265 | |
266 | drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); | |
6f34be50 AD |
267 | kfree(work); |
268 | } | |
269 | ||
270 | void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) | |
271 | { | |
272 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; | |
273 | struct radeon_unpin_work *work; | |
274 | struct drm_pending_vblank_event *e; | |
275 | struct timeval now; | |
276 | unsigned long flags; | |
277 | u32 update_pending; | |
278 | int vpos, hpos; | |
279 | ||
280 | spin_lock_irqsave(&rdev->ddev->event_lock, flags); | |
281 | work = radeon_crtc->unpin_work; | |
282 | if (work == NULL || | |
fcc485d6 | 283 | (work->fence && !radeon_fence_signaled(work->fence))) { |
6f34be50 AD |
284 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); |
285 | return; | |
286 | } | |
287 | /* New pageflip, or just completion of a previous one? */ | |
288 | if (!radeon_crtc->deferred_flip_completion) { | |
289 | /* do the flip (mmio) */ | |
290 | update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base); | |
291 | } else { | |
292 | /* This is just a completion of a flip queued in crtc | |
293 | * at last invocation. Make sure we go directly to | |
294 | * completion routine. | |
295 | */ | |
296 | update_pending = 0; | |
297 | radeon_crtc->deferred_flip_completion = 0; | |
298 | } | |
299 | ||
300 | /* Has the pageflip already completed in crtc, or is it certain | |
301 | * to complete in this vblank? | |
302 | */ | |
303 | if (update_pending && | |
304 | (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, | |
305 | &vpos, &hpos)) && | |
81ffbbed FK |
306 | ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || |
307 | (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { | |
308 | /* crtc didn't flip in this target vblank interval, | |
309 | * but flip is pending in crtc. Based on the current | |
310 | * scanout position we know that the current frame is | |
311 | * (nearly) complete and the flip will (likely) | |
312 | * complete before the start of the next frame. | |
313 | */ | |
314 | update_pending = 0; | |
315 | } | |
316 | if (update_pending) { | |
6f34be50 AD |
317 | /* crtc didn't flip in this target vblank interval, |
318 | * but flip is pending in crtc. It will complete it | |
319 | * in next vblank interval, so complete the flip at | |
320 | * next vblank irq. | |
321 | */ | |
322 | radeon_crtc->deferred_flip_completion = 1; | |
323 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); | |
324 | return; | |
325 | } | |
326 | ||
327 | /* Pageflip (will be) certainly completed in this vblank. Clean up. */ | |
328 | radeon_crtc->unpin_work = NULL; | |
329 | ||
330 | /* wakeup userspace */ | |
331 | if (work->event) { | |
332 | e = work->event; | |
b6724405 | 333 | e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now); |
6f34be50 AD |
334 | e->event.tv_sec = now.tv_sec; |
335 | e->event.tv_usec = now.tv_usec; | |
336 | list_add_tail(&e->base.link, &e->base.file_priv->event_list); | |
337 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
338 | } | |
339 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); | |
340 | ||
341 | drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); | |
342 | radeon_fence_unref(&work->fence); | |
343 | radeon_post_page_flip(work->rdev, work->crtc_id); | |
344 | schedule_work(&work->work); | |
345 | } | |
346 | ||
347 | static int radeon_crtc_page_flip(struct drm_crtc *crtc, | |
348 | struct drm_framebuffer *fb, | |
349 | struct drm_pending_vblank_event *event) | |
350 | { | |
351 | struct drm_device *dev = crtc->dev; | |
352 | struct radeon_device *rdev = dev->dev_private; | |
353 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
354 | struct radeon_framebuffer *old_radeon_fb; | |
355 | struct radeon_framebuffer *new_radeon_fb; | |
356 | struct drm_gem_object *obj; | |
357 | struct radeon_bo *rbo; | |
6f34be50 AD |
358 | struct radeon_unpin_work *work; |
359 | unsigned long flags; | |
360 | u32 tiling_flags, pitch_pixels; | |
361 | u64 base; | |
362 | int r; | |
363 | ||
364 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
365 | if (work == NULL) | |
366 | return -ENOMEM; | |
367 | ||
6f34be50 AD |
368 | work->event = event; |
369 | work->rdev = rdev; | |
370 | work->crtc_id = radeon_crtc->crtc_id; | |
6f34be50 AD |
371 | old_radeon_fb = to_radeon_framebuffer(crtc->fb); |
372 | new_radeon_fb = to_radeon_framebuffer(fb); | |
373 | /* schedule unpin of the old buffer */ | |
374 | obj = old_radeon_fb->obj; | |
498c555f DA |
375 | /* take a reference to the old object */ |
376 | drm_gem_object_reference(obj); | |
7e4d15d9 | 377 | rbo = gem_to_radeon_bo(obj); |
6f34be50 | 378 | work->old_rbo = rbo; |
fcc485d6 MD |
379 | obj = new_radeon_fb->obj; |
380 | rbo = gem_to_radeon_bo(obj); | |
9af20792 DV |
381 | |
382 | spin_lock(&rbo->tbo.bdev->fence_lock); | |
fcc485d6 MD |
383 | if (rbo->tbo.sync_obj) |
384 | work->fence = radeon_fence_ref(rbo->tbo.sync_obj); | |
9af20792 DV |
385 | spin_unlock(&rbo->tbo.bdev->fence_lock); |
386 | ||
6f34be50 AD |
387 | INIT_WORK(&work->work, radeon_unpin_work_func); |
388 | ||
389 | /* We borrow the event spin lock for protecting unpin_work */ | |
390 | spin_lock_irqsave(&dev->event_lock, flags); | |
391 | if (radeon_crtc->unpin_work) { | |
6f34be50 | 392 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
498c555f DA |
393 | r = -EBUSY; |
394 | goto unlock_free; | |
6f34be50 AD |
395 | } |
396 | radeon_crtc->unpin_work = work; | |
397 | radeon_crtc->deferred_flip_completion = 0; | |
398 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
399 | ||
400 | /* pin the new buffer */ | |
6f34be50 AD |
401 | DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n", |
402 | work->old_rbo, rbo); | |
403 | ||
404 | r = radeon_bo_reserve(rbo, false); | |
405 | if (unlikely(r != 0)) { | |
406 | DRM_ERROR("failed to reserve new rbo buffer before flip\n"); | |
407 | goto pflip_cleanup; | |
408 | } | |
0349af70 MD |
409 | /* Only 27 bit offset for legacy CRTC */ |
410 | r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, | |
411 | ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); | |
6f34be50 AD |
412 | if (unlikely(r != 0)) { |
413 | radeon_bo_unreserve(rbo); | |
414 | r = -EINVAL; | |
415 | DRM_ERROR("failed to pin new rbo buffer before flip\n"); | |
416 | goto pflip_cleanup; | |
417 | } | |
418 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); | |
419 | radeon_bo_unreserve(rbo); | |
420 | ||
421 | if (!ASIC_IS_AVIVO(rdev)) { | |
422 | /* crtc offset is from display base addr not FB location */ | |
423 | base -= radeon_crtc->legacy_display_base_addr; | |
01f2c773 | 424 | pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8); |
6f34be50 AD |
425 | |
426 | if (tiling_flags & RADEON_TILING_MACRO) { | |
427 | if (ASIC_IS_R300(rdev)) { | |
428 | base &= ~0x7ff; | |
429 | } else { | |
430 | int byteshift = fb->bits_per_pixel >> 4; | |
431 | int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; | |
432 | base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); | |
433 | } | |
434 | } else { | |
435 | int offset = crtc->y * pitch_pixels + crtc->x; | |
436 | switch (fb->bits_per_pixel) { | |
437 | case 8: | |
438 | default: | |
439 | offset *= 1; | |
440 | break; | |
441 | case 15: | |
442 | case 16: | |
443 | offset *= 2; | |
444 | break; | |
445 | case 24: | |
446 | offset *= 3; | |
447 | break; | |
448 | case 32: | |
449 | offset *= 4; | |
450 | break; | |
451 | } | |
452 | base += offset; | |
453 | } | |
454 | base &= ~7; | |
455 | } | |
456 | ||
457 | spin_lock_irqsave(&dev->event_lock, flags); | |
458 | work->new_crtc_base = base; | |
459 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
460 | ||
461 | /* update crtc fb */ | |
462 | crtc->fb = fb; | |
463 | ||
464 | r = drm_vblank_get(dev, radeon_crtc->crtc_id); | |
465 | if (r) { | |
466 | DRM_ERROR("failed to get vblank before flip\n"); | |
467 | goto pflip_cleanup1; | |
468 | } | |
469 | ||
6f34be50 AD |
470 | /* set the proper interrupt */ |
471 | radeon_pre_page_flip(rdev, radeon_crtc->crtc_id); | |
6f34be50 AD |
472 | |
473 | return 0; | |
474 | ||
6f34be50 | 475 | pflip_cleanup1: |
d0254d56 | 476 | if (unlikely(radeon_bo_reserve(rbo, false) != 0)) { |
6f34be50 AD |
477 | DRM_ERROR("failed to reserve new rbo in error path\n"); |
478 | goto pflip_cleanup; | |
479 | } | |
d0254d56 | 480 | if (unlikely(radeon_bo_unpin(rbo) != 0)) { |
6f34be50 | 481 | DRM_ERROR("failed to unpin new rbo in error path\n"); |
6f34be50 AD |
482 | } |
483 | radeon_bo_unreserve(rbo); | |
484 | ||
485 | pflip_cleanup: | |
486 | spin_lock_irqsave(&dev->event_lock, flags); | |
487 | radeon_crtc->unpin_work = NULL; | |
498c555f | 488 | unlock_free: |
6f34be50 | 489 | spin_unlock_irqrestore(&dev->event_lock, flags); |
db318d7a | 490 | drm_gem_object_unreference_unlocked(old_radeon_fb->obj); |
fcc485d6 | 491 | radeon_fence_unref(&work->fence); |
6f34be50 AD |
492 | kfree(work); |
493 | ||
494 | return r; | |
495 | } | |
496 | ||
771fe6b9 JG |
497 | static const struct drm_crtc_funcs radeon_crtc_funcs = { |
498 | .cursor_set = radeon_crtc_cursor_set, | |
499 | .cursor_move = radeon_crtc_cursor_move, | |
500 | .gamma_set = radeon_crtc_gamma_set, | |
501 | .set_config = drm_crtc_helper_set_config, | |
502 | .destroy = radeon_crtc_destroy, | |
6f34be50 | 503 | .page_flip = radeon_crtc_page_flip, |
771fe6b9 JG |
504 | }; |
505 | ||
506 | static void radeon_crtc_init(struct drm_device *dev, int index) | |
507 | { | |
508 | struct radeon_device *rdev = dev->dev_private; | |
509 | struct radeon_crtc *radeon_crtc; | |
510 | int i; | |
511 | ||
512 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
513 | if (radeon_crtc == NULL) | |
514 | return; | |
515 | ||
516 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); | |
517 | ||
518 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); | |
519 | radeon_crtc->crtc_id = index; | |
c93bb85b | 520 | rdev->mode_info.crtcs[index] = radeon_crtc; |
771fe6b9 | 521 | |
785b93ef | 522 | #if 0 |
771fe6b9 JG |
523 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
524 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); | |
525 | radeon_crtc->mode_set.num_connectors = 0; | |
785b93ef | 526 | #endif |
771fe6b9 JG |
527 | |
528 | for (i = 0; i < 256; i++) { | |
529 | radeon_crtc->lut_r[i] = i << 2; | |
530 | radeon_crtc->lut_g[i] = i << 2; | |
531 | radeon_crtc->lut_b[i] = i << 2; | |
532 | } | |
533 | ||
534 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) | |
535 | radeon_atombios_init_crtc(dev, radeon_crtc); | |
536 | else | |
537 | radeon_legacy_init_crtc(dev, radeon_crtc); | |
538 | } | |
539 | ||
df391c0d | 540 | static const char *encoder_names[37] = { |
771fe6b9 JG |
541 | "NONE", |
542 | "INTERNAL_LVDS", | |
543 | "INTERNAL_TMDS1", | |
544 | "INTERNAL_TMDS2", | |
545 | "INTERNAL_DAC1", | |
546 | "INTERNAL_DAC2", | |
547 | "INTERNAL_SDVOA", | |
548 | "INTERNAL_SDVOB", | |
549 | "SI170B", | |
550 | "CH7303", | |
551 | "CH7301", | |
552 | "INTERNAL_DVO1", | |
553 | "EXTERNAL_SDVOA", | |
554 | "EXTERNAL_SDVOB", | |
555 | "TITFP513", | |
556 | "INTERNAL_LVTM1", | |
557 | "VT1623", | |
558 | "HDMI_SI1930", | |
559 | "HDMI_INTERNAL", | |
560 | "INTERNAL_KLDSCP_TMDS1", | |
561 | "INTERNAL_KLDSCP_DVO1", | |
562 | "INTERNAL_KLDSCP_DAC1", | |
563 | "INTERNAL_KLDSCP_DAC2", | |
564 | "SI178", | |
565 | "MVPU_FPGA", | |
566 | "INTERNAL_DDI", | |
567 | "VT1625", | |
568 | "HDMI_SI1932", | |
569 | "DP_AN9801", | |
570 | "DP_DP501", | |
571 | "INTERNAL_UNIPHY", | |
572 | "INTERNAL_KLDSCP_LVTMA", | |
573 | "INTERNAL_UNIPHY1", | |
574 | "INTERNAL_UNIPHY2", | |
bf982ebf AD |
575 | "NUTMEG", |
576 | "TRAVIS", | |
df391c0d | 577 | "INTERNAL_VCE" |
771fe6b9 JG |
578 | }; |
579 | ||
cbd4623d | 580 | static const char *hpd_names[6] = { |
eed45b30 AD |
581 | "HPD1", |
582 | "HPD2", | |
583 | "HPD3", | |
584 | "HPD4", | |
585 | "HPD5", | |
586 | "HPD6", | |
587 | }; | |
588 | ||
771fe6b9 JG |
589 | static void radeon_print_display_setup(struct drm_device *dev) |
590 | { | |
591 | struct drm_connector *connector; | |
592 | struct radeon_connector *radeon_connector; | |
593 | struct drm_encoder *encoder; | |
594 | struct radeon_encoder *radeon_encoder; | |
595 | uint32_t devices; | |
596 | int i = 0; | |
597 | ||
598 | DRM_INFO("Radeon Display Connectors\n"); | |
599 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
600 | radeon_connector = to_radeon_connector(connector); | |
601 | DRM_INFO("Connector %d:\n", i); | |
c1d2dbd2 | 602 | DRM_INFO(" %s\n", drm_get_connector_name(connector)); |
eed45b30 AD |
603 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
604 | DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); | |
4b9d2a21 | 605 | if (radeon_connector->ddc_bus) { |
771fe6b9 JG |
606 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
607 | radeon_connector->ddc_bus->rec.mask_clk_reg, | |
608 | radeon_connector->ddc_bus->rec.mask_data_reg, | |
609 | radeon_connector->ddc_bus->rec.a_clk_reg, | |
610 | radeon_connector->ddc_bus->rec.a_data_reg, | |
9b9fe724 AD |
611 | radeon_connector->ddc_bus->rec.en_clk_reg, |
612 | radeon_connector->ddc_bus->rec.en_data_reg, | |
613 | radeon_connector->ddc_bus->rec.y_clk_reg, | |
614 | radeon_connector->ddc_bus->rec.y_data_reg); | |
fb939dfc | 615 | if (radeon_connector->router.ddc_valid) |
26b5bc98 | 616 | DRM_INFO(" DDC Router 0x%x/0x%x\n", |
fb939dfc AD |
617 | radeon_connector->router.ddc_mux_control_pin, |
618 | radeon_connector->router.ddc_mux_state); | |
619 | if (radeon_connector->router.cd_valid) | |
620 | DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", | |
621 | radeon_connector->router.cd_mux_control_pin, | |
622 | radeon_connector->router.cd_mux_state); | |
4b9d2a21 DA |
623 | } else { |
624 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || | |
625 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || | |
626 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || | |
627 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || | |
628 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || | |
629 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) | |
630 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); | |
631 | } | |
771fe6b9 JG |
632 | DRM_INFO(" Encoders:\n"); |
633 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
634 | radeon_encoder = to_radeon_encoder(encoder); | |
635 | devices = radeon_encoder->devices & radeon_connector->devices; | |
636 | if (devices) { | |
637 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) | |
638 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
639 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) | |
640 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
641 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) | |
642 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
643 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) | |
644 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
645 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) | |
646 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
647 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) | |
648 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
649 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) | |
650 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
651 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) | |
652 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
73758a5d AD |
653 | if (devices & ATOM_DEVICE_DFP6_SUPPORT) |
654 | DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
771fe6b9 JG |
655 | if (devices & ATOM_DEVICE_TV1_SUPPORT) |
656 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
657 | if (devices & ATOM_DEVICE_CV_SUPPORT) | |
658 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
659 | } | |
660 | } | |
661 | i++; | |
662 | } | |
663 | } | |
664 | ||
4ce001ab | 665 | static bool radeon_setup_enc_conn(struct drm_device *dev) |
771fe6b9 JG |
666 | { |
667 | struct radeon_device *rdev = dev->dev_private; | |
771fe6b9 JG |
668 | bool ret = false; |
669 | ||
670 | if (rdev->bios) { | |
671 | if (rdev->is_atom_bios) { | |
a084e6ee AD |
672 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
673 | if (ret == false) | |
771fe6b9 | 674 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
b9597a1c | 675 | } else { |
771fe6b9 | 676 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
b9597a1c AD |
677 | if (ret == false) |
678 | ret = radeon_get_legacy_connector_info_from_table(dev); | |
679 | } | |
771fe6b9 JG |
680 | } else { |
681 | if (!ASIC_IS_AVIVO(rdev)) | |
682 | ret = radeon_get_legacy_connector_info_from_table(dev); | |
683 | } | |
684 | if (ret) { | |
1f3b6a45 | 685 | radeon_setup_encoder_clones(dev); |
771fe6b9 | 686 | radeon_print_display_setup(dev); |
771fe6b9 JG |
687 | } |
688 | ||
689 | return ret; | |
690 | } | |
691 | ||
692 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) | |
693 | { | |
3c537889 AD |
694 | struct drm_device *dev = radeon_connector->base.dev; |
695 | struct radeon_device *rdev = dev->dev_private; | |
771fe6b9 JG |
696 | int ret = 0; |
697 | ||
26b5bc98 | 698 | /* on hw with routers, select right port */ |
fb939dfc AD |
699 | if (radeon_connector->router.ddc_valid) |
700 | radeon_router_select_ddc_port(radeon_connector); | |
26b5bc98 | 701 | |
0a9069d3 NOS |
702 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) != |
703 | ENCODER_OBJECT_ID_NONE) { | |
704 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; | |
705 | ||
706 | if (dig->dp_i2c_bus) | |
707 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, | |
708 | &dig->dp_i2c_bus->adapter); | |
709 | } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || | |
710 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { | |
746c1aa4 | 711 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
b06947b5 | 712 | |
7a15cbd4 DA |
713 | if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || |
714 | dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) | |
b06947b5 AD |
715 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, |
716 | &dig->dp_i2c_bus->adapter); | |
717 | else if (radeon_connector->ddc_bus && !radeon_connector->edid) | |
718 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, | |
719 | &radeon_connector->ddc_bus->adapter); | |
720 | } else { | |
721 | if (radeon_connector->ddc_bus && !radeon_connector->edid) | |
722 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, | |
723 | &radeon_connector->ddc_bus->adapter); | |
0294cf4f | 724 | } |
c324acd5 AD |
725 | |
726 | if (!radeon_connector->edid) { | |
727 | if (rdev->is_atom_bios) { | |
728 | /* some laptops provide a hardcoded edid in rom for LCDs */ | |
729 | if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) || | |
730 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP))) | |
731 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); | |
732 | } else | |
733 | /* some servers provide a hardcoded edid in rom for KVMs */ | |
734 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); | |
735 | } | |
0294cf4f AD |
736 | if (radeon_connector->edid) { |
737 | drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); | |
738 | ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); | |
771fe6b9 JG |
739 | return ret; |
740 | } | |
741 | drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); | |
42dea5dd | 742 | return 0; |
771fe6b9 JG |
743 | } |
744 | ||
f523f74e AD |
745 | /* avivo */ |
746 | static void avivo_get_fb_div(struct radeon_pll *pll, | |
747 | u32 target_clock, | |
748 | u32 post_div, | |
749 | u32 ref_div, | |
750 | u32 *fb_div, | |
751 | u32 *frac_fb_div) | |
752 | { | |
753 | u32 tmp = post_div * ref_div; | |
754 | ||
755 | tmp *= target_clock; | |
756 | *fb_div = tmp / pll->reference_freq; | |
757 | *frac_fb_div = tmp % pll->reference_freq; | |
a4b40d5d AD |
758 | |
759 | if (*fb_div > pll->max_feedback_div) | |
760 | *fb_div = pll->max_feedback_div; | |
761 | else if (*fb_div < pll->min_feedback_div) | |
762 | *fb_div = pll->min_feedback_div; | |
f523f74e AD |
763 | } |
764 | ||
765 | static u32 avivo_get_post_div(struct radeon_pll *pll, | |
766 | u32 target_clock) | |
767 | { | |
768 | u32 vco, post_div, tmp; | |
769 | ||
770 | if (pll->flags & RADEON_PLL_USE_POST_DIV) | |
771 | return pll->post_div; | |
772 | ||
773 | if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { | |
774 | if (pll->flags & RADEON_PLL_IS_LCD) | |
775 | vco = pll->lcd_pll_out_min; | |
776 | else | |
777 | vco = pll->pll_out_min; | |
778 | } else { | |
779 | if (pll->flags & RADEON_PLL_IS_LCD) | |
780 | vco = pll->lcd_pll_out_max; | |
781 | else | |
782 | vco = pll->pll_out_max; | |
783 | } | |
784 | ||
785 | post_div = vco / target_clock; | |
786 | tmp = vco % target_clock; | |
787 | ||
788 | if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { | |
789 | if (tmp) | |
790 | post_div++; | |
791 | } else { | |
792 | if (!tmp) | |
793 | post_div--; | |
794 | } | |
795 | ||
a4b40d5d AD |
796 | if (post_div > pll->max_post_div) |
797 | post_div = pll->max_post_div; | |
798 | else if (post_div < pll->min_post_div) | |
799 | post_div = pll->min_post_div; | |
800 | ||
f523f74e AD |
801 | return post_div; |
802 | } | |
803 | ||
804 | #define MAX_TOLERANCE 10 | |
805 | ||
806 | void radeon_compute_pll_avivo(struct radeon_pll *pll, | |
807 | u32 freq, | |
808 | u32 *dot_clock_p, | |
809 | u32 *fb_div_p, | |
810 | u32 *frac_fb_div_p, | |
811 | u32 *ref_div_p, | |
812 | u32 *post_div_p) | |
813 | { | |
814 | u32 target_clock = freq / 10; | |
815 | u32 post_div = avivo_get_post_div(pll, target_clock); | |
816 | u32 ref_div = pll->min_ref_div; | |
817 | u32 fb_div = 0, frac_fb_div = 0, tmp; | |
818 | ||
819 | if (pll->flags & RADEON_PLL_USE_REF_DIV) | |
820 | ref_div = pll->reference_div; | |
821 | ||
822 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { | |
823 | avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div); | |
824 | frac_fb_div = (100 * frac_fb_div) / pll->reference_freq; | |
825 | if (frac_fb_div >= 5) { | |
826 | frac_fb_div -= 5; | |
827 | frac_fb_div = frac_fb_div / 10; | |
828 | frac_fb_div++; | |
829 | } | |
830 | if (frac_fb_div >= 10) { | |
831 | fb_div++; | |
832 | frac_fb_div = 0; | |
833 | } | |
834 | } else { | |
835 | while (ref_div <= pll->max_ref_div) { | |
836 | avivo_get_fb_div(pll, target_clock, post_div, ref_div, | |
837 | &fb_div, &frac_fb_div); | |
838 | if (frac_fb_div >= (pll->reference_freq / 2)) | |
839 | fb_div++; | |
840 | frac_fb_div = 0; | |
841 | tmp = (pll->reference_freq * fb_div) / (post_div * ref_div); | |
842 | tmp = (tmp * 10000) / target_clock; | |
843 | ||
844 | if (tmp > (10000 + MAX_TOLERANCE)) | |
845 | ref_div++; | |
846 | else if (tmp >= (10000 - MAX_TOLERANCE)) | |
847 | break; | |
848 | else | |
849 | ref_div++; | |
850 | } | |
851 | } | |
852 | ||
853 | *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) / | |
854 | (ref_div * post_div * 10); | |
855 | *fb_div_p = fb_div; | |
856 | *frac_fb_div_p = frac_fb_div; | |
857 | *ref_div_p = ref_div; | |
858 | *post_div_p = post_div; | |
859 | DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n", | |
860 | *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div); | |
861 | } | |
862 | ||
863 | /* pre-avivo */ | |
771fe6b9 JG |
864 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) |
865 | { | |
866 | uint64_t mod; | |
867 | ||
868 | n += d / 2; | |
869 | ||
870 | mod = do_div(n, d); | |
871 | return n; | |
872 | } | |
873 | ||
f523f74e AD |
874 | void radeon_compute_pll_legacy(struct radeon_pll *pll, |
875 | uint64_t freq, | |
876 | uint32_t *dot_clock_p, | |
877 | uint32_t *fb_div_p, | |
878 | uint32_t *frac_fb_div_p, | |
879 | uint32_t *ref_div_p, | |
880 | uint32_t *post_div_p) | |
771fe6b9 JG |
881 | { |
882 | uint32_t min_ref_div = pll->min_ref_div; | |
883 | uint32_t max_ref_div = pll->max_ref_div; | |
fc10332b AD |
884 | uint32_t min_post_div = pll->min_post_div; |
885 | uint32_t max_post_div = pll->max_post_div; | |
771fe6b9 JG |
886 | uint32_t min_fractional_feed_div = 0; |
887 | uint32_t max_fractional_feed_div = 0; | |
888 | uint32_t best_vco = pll->best_vco; | |
889 | uint32_t best_post_div = 1; | |
890 | uint32_t best_ref_div = 1; | |
891 | uint32_t best_feedback_div = 1; | |
892 | uint32_t best_frac_feedback_div = 0; | |
893 | uint32_t best_freq = -1; | |
894 | uint32_t best_error = 0xffffffff; | |
895 | uint32_t best_vco_diff = 1; | |
896 | uint32_t post_div; | |
86cb2bbf | 897 | u32 pll_out_min, pll_out_max; |
771fe6b9 | 898 | |
d9fdaafb | 899 | DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
771fe6b9 JG |
900 | freq = freq * 1000; |
901 | ||
86cb2bbf AD |
902 | if (pll->flags & RADEON_PLL_IS_LCD) { |
903 | pll_out_min = pll->lcd_pll_out_min; | |
904 | pll_out_max = pll->lcd_pll_out_max; | |
905 | } else { | |
906 | pll_out_min = pll->pll_out_min; | |
907 | pll_out_max = pll->pll_out_max; | |
908 | } | |
909 | ||
619efb10 AD |
910 | if (pll_out_min > 64800) |
911 | pll_out_min = 64800; | |
912 | ||
fc10332b | 913 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
771fe6b9 JG |
914 | min_ref_div = max_ref_div = pll->reference_div; |
915 | else { | |
916 | while (min_ref_div < max_ref_div-1) { | |
917 | uint32_t mid = (min_ref_div + max_ref_div) / 2; | |
918 | uint32_t pll_in = pll->reference_freq / mid; | |
919 | if (pll_in < pll->pll_in_min) | |
920 | max_ref_div = mid; | |
921 | else if (pll_in > pll->pll_in_max) | |
922 | min_ref_div = mid; | |
923 | else | |
924 | break; | |
925 | } | |
926 | } | |
927 | ||
fc10332b AD |
928 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
929 | min_post_div = max_post_div = pll->post_div; | |
930 | ||
931 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { | |
771fe6b9 JG |
932 | min_fractional_feed_div = pll->min_frac_feedback_div; |
933 | max_fractional_feed_div = pll->max_frac_feedback_div; | |
934 | } | |
935 | ||
bd6a60af | 936 | for (post_div = max_post_div; post_div >= min_post_div; --post_div) { |
771fe6b9 JG |
937 | uint32_t ref_div; |
938 | ||
fc10332b | 939 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
771fe6b9 JG |
940 | continue; |
941 | ||
942 | /* legacy radeons only have a few post_divs */ | |
fc10332b | 943 | if (pll->flags & RADEON_PLL_LEGACY) { |
771fe6b9 JG |
944 | if ((post_div == 5) || |
945 | (post_div == 7) || | |
946 | (post_div == 9) || | |
947 | (post_div == 10) || | |
948 | (post_div == 11) || | |
949 | (post_div == 13) || | |
950 | (post_div == 14) || | |
951 | (post_div == 15)) | |
952 | continue; | |
953 | } | |
954 | ||
955 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { | |
956 | uint32_t feedback_div, current_freq = 0, error, vco_diff; | |
957 | uint32_t pll_in = pll->reference_freq / ref_div; | |
958 | uint32_t min_feed_div = pll->min_feedback_div; | |
959 | uint32_t max_feed_div = pll->max_feedback_div + 1; | |
960 | ||
961 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) | |
962 | continue; | |
963 | ||
964 | while (min_feed_div < max_feed_div) { | |
965 | uint32_t vco; | |
966 | uint32_t min_frac_feed_div = min_fractional_feed_div; | |
967 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; | |
968 | uint32_t frac_feedback_div; | |
969 | uint64_t tmp; | |
970 | ||
971 | feedback_div = (min_feed_div + max_feed_div) / 2; | |
972 | ||
973 | tmp = (uint64_t)pll->reference_freq * feedback_div; | |
974 | vco = radeon_div(tmp, ref_div); | |
975 | ||
86cb2bbf | 976 | if (vco < pll_out_min) { |
771fe6b9 JG |
977 | min_feed_div = feedback_div + 1; |
978 | continue; | |
86cb2bbf | 979 | } else if (vco > pll_out_max) { |
771fe6b9 JG |
980 | max_feed_div = feedback_div; |
981 | continue; | |
982 | } | |
983 | ||
984 | while (min_frac_feed_div < max_frac_feed_div) { | |
985 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; | |
986 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; | |
987 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; | |
988 | current_freq = radeon_div(tmp, ref_div * post_div); | |
989 | ||
fc10332b | 990 | if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
167ffc44 DC |
991 | if (freq < current_freq) |
992 | error = 0xffffffff; | |
993 | else | |
994 | error = freq - current_freq; | |
d0e275a9 AD |
995 | } else |
996 | error = abs(current_freq - freq); | |
771fe6b9 JG |
997 | vco_diff = abs(vco - best_vco); |
998 | ||
999 | if ((best_vco == 0 && error < best_error) || | |
1000 | (best_vco != 0 && | |
167ffc44 | 1001 | ((best_error > 100 && error < best_error - 100) || |
5480f727 | 1002 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { |
771fe6b9 JG |
1003 | best_post_div = post_div; |
1004 | best_ref_div = ref_div; | |
1005 | best_feedback_div = feedback_div; | |
1006 | best_frac_feedback_div = frac_feedback_div; | |
1007 | best_freq = current_freq; | |
1008 | best_error = error; | |
1009 | best_vco_diff = vco_diff; | |
5480f727 DA |
1010 | } else if (current_freq == freq) { |
1011 | if (best_freq == -1) { | |
1012 | best_post_div = post_div; | |
1013 | best_ref_div = ref_div; | |
1014 | best_feedback_div = feedback_div; | |
1015 | best_frac_feedback_div = frac_feedback_div; | |
1016 | best_freq = current_freq; | |
1017 | best_error = error; | |
1018 | best_vco_diff = vco_diff; | |
1019 | } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || | |
1020 | ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || | |
1021 | ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || | |
1022 | ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || | |
1023 | ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || | |
1024 | ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { | |
1025 | best_post_div = post_div; | |
1026 | best_ref_div = ref_div; | |
1027 | best_feedback_div = feedback_div; | |
1028 | best_frac_feedback_div = frac_feedback_div; | |
1029 | best_freq = current_freq; | |
1030 | best_error = error; | |
1031 | best_vco_diff = vco_diff; | |
1032 | } | |
771fe6b9 JG |
1033 | } |
1034 | if (current_freq < freq) | |
1035 | min_frac_feed_div = frac_feedback_div + 1; | |
1036 | else | |
1037 | max_frac_feed_div = frac_feedback_div; | |
1038 | } | |
1039 | if (current_freq < freq) | |
1040 | min_feed_div = feedback_div + 1; | |
1041 | else | |
1042 | max_feed_div = feedback_div; | |
1043 | } | |
1044 | } | |
1045 | } | |
1046 | ||
1047 | *dot_clock_p = best_freq / 10000; | |
1048 | *fb_div_p = best_feedback_div; | |
1049 | *frac_fb_div_p = best_frac_feedback_div; | |
1050 | *ref_div_p = best_ref_div; | |
1051 | *post_div_p = best_post_div; | |
bbb0aef5 JP |
1052 | DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
1053 | (long long)freq, | |
1054 | best_freq / 1000, best_feedback_div, best_frac_feedback_div, | |
51d4bf84 AD |
1055 | best_ref_div, best_post_div); |
1056 | ||
771fe6b9 JG |
1057 | } |
1058 | ||
1059 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
1060 | { | |
1061 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); | |
771fe6b9 | 1062 | |
29d08b3e | 1063 | if (radeon_fb->obj) { |
bc9025bd | 1064 | drm_gem_object_unreference_unlocked(radeon_fb->obj); |
29d08b3e | 1065 | } |
771fe6b9 JG |
1066 | drm_framebuffer_cleanup(fb); |
1067 | kfree(radeon_fb); | |
1068 | } | |
1069 | ||
1070 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
1071 | struct drm_file *file_priv, | |
1072 | unsigned int *handle) | |
1073 | { | |
1074 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); | |
1075 | ||
1076 | return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); | |
1077 | } | |
1078 | ||
1079 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { | |
1080 | .destroy = radeon_user_framebuffer_destroy, | |
1081 | .create_handle = radeon_user_framebuffer_create_handle, | |
1082 | }; | |
1083 | ||
aaefcd42 | 1084 | int |
38651674 DA |
1085 | radeon_framebuffer_init(struct drm_device *dev, |
1086 | struct radeon_framebuffer *rfb, | |
308e5bcb | 1087 | struct drm_mode_fb_cmd2 *mode_cmd, |
38651674 | 1088 | struct drm_gem_object *obj) |
771fe6b9 | 1089 | { |
aaefcd42 | 1090 | int ret; |
38651674 | 1091 | rfb->obj = obj; |
aaefcd42 DA |
1092 | ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); |
1093 | if (ret) { | |
1094 | rfb->obj = NULL; | |
1095 | return ret; | |
1096 | } | |
38651674 | 1097 | drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); |
aaefcd42 | 1098 | return 0; |
771fe6b9 JG |
1099 | } |
1100 | ||
1101 | static struct drm_framebuffer * | |
1102 | radeon_user_framebuffer_create(struct drm_device *dev, | |
1103 | struct drm_file *file_priv, | |
308e5bcb | 1104 | struct drm_mode_fb_cmd2 *mode_cmd) |
771fe6b9 JG |
1105 | { |
1106 | struct drm_gem_object *obj; | |
38651674 | 1107 | struct radeon_framebuffer *radeon_fb; |
aaefcd42 | 1108 | int ret; |
771fe6b9 | 1109 | |
308e5bcb | 1110 | obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); |
7e71c9e2 JG |
1111 | if (obj == NULL) { |
1112 | dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " | |
308e5bcb | 1113 | "can't create framebuffer\n", mode_cmd->handles[0]); |
cce13ff7 | 1114 | return ERR_PTR(-ENOENT); |
7e71c9e2 | 1115 | } |
38651674 DA |
1116 | |
1117 | radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); | |
cce13ff7 CW |
1118 | if (radeon_fb == NULL) |
1119 | return ERR_PTR(-ENOMEM); | |
38651674 | 1120 | |
aaefcd42 DA |
1121 | ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); |
1122 | if (ret) { | |
1123 | kfree(radeon_fb); | |
1124 | drm_gem_object_unreference_unlocked(obj); | |
1125 | return NULL; | |
1126 | } | |
38651674 DA |
1127 | |
1128 | return &radeon_fb->base; | |
771fe6b9 JG |
1129 | } |
1130 | ||
eb1f8e4f DA |
1131 | static void radeon_output_poll_changed(struct drm_device *dev) |
1132 | { | |
1133 | struct radeon_device *rdev = dev->dev_private; | |
1134 | radeon_fb_output_poll_changed(rdev); | |
1135 | } | |
1136 | ||
771fe6b9 JG |
1137 | static const struct drm_mode_config_funcs radeon_mode_funcs = { |
1138 | .fb_create = radeon_user_framebuffer_create, | |
eb1f8e4f | 1139 | .output_poll_changed = radeon_output_poll_changed |
771fe6b9 JG |
1140 | }; |
1141 | ||
445282db DA |
1142 | static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = |
1143 | { { 0, "driver" }, | |
1144 | { 1, "bios" }, | |
1145 | }; | |
1146 | ||
1147 | static struct drm_prop_enum_list radeon_tv_std_enum_list[] = | |
1148 | { { TV_STD_NTSC, "ntsc" }, | |
1149 | { TV_STD_PAL, "pal" }, | |
1150 | { TV_STD_PAL_M, "pal-m" }, | |
1151 | { TV_STD_PAL_60, "pal-60" }, | |
1152 | { TV_STD_NTSC_J, "ntsc-j" }, | |
1153 | { TV_STD_SCART_PAL, "scart-pal" }, | |
1154 | { TV_STD_PAL_CN, "pal-cn" }, | |
1155 | { TV_STD_SECAM, "secam" }, | |
1156 | }; | |
1157 | ||
5b1714d3 AD |
1158 | static struct drm_prop_enum_list radeon_underscan_enum_list[] = |
1159 | { { UNDERSCAN_OFF, "off" }, | |
1160 | { UNDERSCAN_ON, "on" }, | |
1161 | { UNDERSCAN_AUTO, "auto" }, | |
1162 | }; | |
1163 | ||
d79766fa | 1164 | static int radeon_modeset_create_props(struct radeon_device *rdev) |
445282db | 1165 | { |
4a67d391 | 1166 | int sz; |
445282db DA |
1167 | |
1168 | if (rdev->is_atom_bios) { | |
1169 | rdev->mode_info.coherent_mode_property = | |
d9bc3c02 | 1170 | drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); |
445282db DA |
1171 | if (!rdev->mode_info.coherent_mode_property) |
1172 | return -ENOMEM; | |
445282db DA |
1173 | } |
1174 | ||
1175 | if (!ASIC_IS_AVIVO(rdev)) { | |
1176 | sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); | |
1177 | rdev->mode_info.tmds_pll_property = | |
4a67d391 SH |
1178 | drm_property_create_enum(rdev->ddev, 0, |
1179 | "tmds_pll", | |
1180 | radeon_tmds_pll_enum_list, sz); | |
445282db DA |
1181 | } |
1182 | ||
1183 | rdev->mode_info.load_detect_property = | |
d9bc3c02 | 1184 | drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); |
445282db DA |
1185 | if (!rdev->mode_info.load_detect_property) |
1186 | return -ENOMEM; | |
445282db DA |
1187 | |
1188 | drm_mode_create_scaling_mode_property(rdev->ddev); | |
1189 | ||
1190 | sz = ARRAY_SIZE(radeon_tv_std_enum_list); | |
1191 | rdev->mode_info.tv_std_property = | |
4a67d391 SH |
1192 | drm_property_create_enum(rdev->ddev, 0, |
1193 | "tv standard", | |
1194 | radeon_tv_std_enum_list, sz); | |
445282db | 1195 | |
5b1714d3 AD |
1196 | sz = ARRAY_SIZE(radeon_underscan_enum_list); |
1197 | rdev->mode_info.underscan_property = | |
4a67d391 SH |
1198 | drm_property_create_enum(rdev->ddev, 0, |
1199 | "underscan", | |
1200 | radeon_underscan_enum_list, sz); | |
5b1714d3 | 1201 | |
5bccf5e3 | 1202 | rdev->mode_info.underscan_hborder_property = |
d9bc3c02 SH |
1203 | drm_property_create_range(rdev->ddev, 0, |
1204 | "underscan hborder", 0, 128); | |
5bccf5e3 MG |
1205 | if (!rdev->mode_info.underscan_hborder_property) |
1206 | return -ENOMEM; | |
5bccf5e3 MG |
1207 | |
1208 | rdev->mode_info.underscan_vborder_property = | |
d9bc3c02 SH |
1209 | drm_property_create_range(rdev->ddev, 0, |
1210 | "underscan vborder", 0, 128); | |
5bccf5e3 MG |
1211 | if (!rdev->mode_info.underscan_vborder_property) |
1212 | return -ENOMEM; | |
5bccf5e3 | 1213 | |
445282db DA |
1214 | return 0; |
1215 | } | |
1216 | ||
f46c0120 AD |
1217 | void radeon_update_display_priority(struct radeon_device *rdev) |
1218 | { | |
1219 | /* adjustment options for the display watermarks */ | |
1220 | if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { | |
1221 | /* set display priority to high for r3xx, rv515 chips | |
1222 | * this avoids flickering due to underflow to the | |
1223 | * display controllers during heavy acceleration. | |
45737447 AD |
1224 | * Don't force high on rs4xx igp chips as it seems to |
1225 | * affect the sound card. See kernel bug 15982. | |
f46c0120 | 1226 | */ |
45737447 AD |
1227 | if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && |
1228 | !(rdev->flags & RADEON_IS_IGP)) | |
f46c0120 AD |
1229 | rdev->disp_priority = 2; |
1230 | else | |
1231 | rdev->disp_priority = 0; | |
1232 | } else | |
1233 | rdev->disp_priority = radeon_disp_priority; | |
1234 | ||
1235 | } | |
1236 | ||
0783986a AD |
1237 | /* |
1238 | * Allocate hdmi structs and determine register offsets | |
1239 | */ | |
1240 | static void radeon_afmt_init(struct radeon_device *rdev) | |
1241 | { | |
1242 | int i; | |
1243 | ||
1244 | for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) | |
1245 | rdev->mode_info.afmt[i] = NULL; | |
1246 | ||
1247 | if (ASIC_IS_DCE6(rdev)) { | |
1248 | /* todo */ | |
1249 | } else if (ASIC_IS_DCE4(rdev)) { | |
1250 | /* DCE4/5 has 6 audio blocks tied to DIG encoders */ | |
1251 | /* DCE4.1 has 2 audio blocks tied to DIG encoders */ | |
1252 | rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); | |
1253 | if (rdev->mode_info.afmt[0]) { | |
1254 | rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET; | |
1255 | rdev->mode_info.afmt[0]->id = 0; | |
1256 | } | |
1257 | rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); | |
1258 | if (rdev->mode_info.afmt[1]) { | |
1259 | rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET; | |
1260 | rdev->mode_info.afmt[1]->id = 1; | |
1261 | } | |
1262 | if (!ASIC_IS_DCE41(rdev)) { | |
1263 | rdev->mode_info.afmt[2] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); | |
1264 | if (rdev->mode_info.afmt[2]) { | |
1265 | rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET; | |
1266 | rdev->mode_info.afmt[2]->id = 2; | |
1267 | } | |
1268 | rdev->mode_info.afmt[3] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); | |
1269 | if (rdev->mode_info.afmt[3]) { | |
1270 | rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET; | |
1271 | rdev->mode_info.afmt[3]->id = 3; | |
1272 | } | |
1273 | rdev->mode_info.afmt[4] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); | |
1274 | if (rdev->mode_info.afmt[4]) { | |
1275 | rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET; | |
1276 | rdev->mode_info.afmt[4]->id = 4; | |
1277 | } | |
1278 | rdev->mode_info.afmt[5] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); | |
1279 | if (rdev->mode_info.afmt[5]) { | |
1280 | rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET; | |
1281 | rdev->mode_info.afmt[5]->id = 5; | |
1282 | } | |
1283 | } | |
1284 | } else if (ASIC_IS_DCE3(rdev)) { | |
1285 | /* DCE3.x has 2 audio blocks tied to DIG encoders */ | |
1286 | rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); | |
1287 | if (rdev->mode_info.afmt[0]) { | |
1288 | rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; | |
1289 | rdev->mode_info.afmt[0]->id = 0; | |
1290 | } | |
1291 | rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); | |
1292 | if (rdev->mode_info.afmt[1]) { | |
1293 | rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; | |
1294 | rdev->mode_info.afmt[1]->id = 1; | |
1295 | } | |
1296 | } else if (ASIC_IS_DCE2(rdev)) { | |
1297 | /* DCE2 has at least 1 routable audio block */ | |
1298 | rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); | |
1299 | if (rdev->mode_info.afmt[0]) { | |
1300 | rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; | |
1301 | rdev->mode_info.afmt[0]->id = 0; | |
1302 | } | |
1303 | /* r6xx has 2 routable audio blocks */ | |
1304 | if (rdev->family >= CHIP_R600) { | |
1305 | rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); | |
1306 | if (rdev->mode_info.afmt[1]) { | |
1307 | rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; | |
1308 | rdev->mode_info.afmt[1]->id = 1; | |
1309 | } | |
1310 | } | |
1311 | } | |
1312 | } | |
1313 | ||
1314 | static void radeon_afmt_fini(struct radeon_device *rdev) | |
1315 | { | |
1316 | int i; | |
1317 | ||
1318 | for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { | |
1319 | kfree(rdev->mode_info.afmt[i]); | |
1320 | rdev->mode_info.afmt[i] = NULL; | |
1321 | } | |
1322 | } | |
1323 | ||
771fe6b9 JG |
1324 | int radeon_modeset_init(struct radeon_device *rdev) |
1325 | { | |
18917b60 | 1326 | int i; |
771fe6b9 JG |
1327 | int ret; |
1328 | ||
1329 | drm_mode_config_init(rdev->ddev); | |
1330 | rdev->mode_info.mode_config_initialized = true; | |
1331 | ||
e6ecefaa | 1332 | rdev->ddev->mode_config.funcs = &radeon_mode_funcs; |
771fe6b9 | 1333 | |
881dd74e AD |
1334 | if (ASIC_IS_DCE5(rdev)) { |
1335 | rdev->ddev->mode_config.max_width = 16384; | |
1336 | rdev->ddev->mode_config.max_height = 16384; | |
1337 | } else if (ASIC_IS_AVIVO(rdev)) { | |
771fe6b9 JG |
1338 | rdev->ddev->mode_config.max_width = 8192; |
1339 | rdev->ddev->mode_config.max_height = 8192; | |
1340 | } else { | |
1341 | rdev->ddev->mode_config.max_width = 4096; | |
1342 | rdev->ddev->mode_config.max_height = 4096; | |
1343 | } | |
1344 | ||
019d96cb DA |
1345 | rdev->ddev->mode_config.preferred_depth = 24; |
1346 | rdev->ddev->mode_config.prefer_shadow = 1; | |
1347 | ||
771fe6b9 JG |
1348 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; |
1349 | ||
445282db DA |
1350 | ret = radeon_modeset_create_props(rdev); |
1351 | if (ret) { | |
1352 | return ret; | |
1353 | } | |
dfee5614 | 1354 | |
f376b94f AD |
1355 | /* init i2c buses */ |
1356 | radeon_i2c_init(rdev); | |
1357 | ||
3c537889 AD |
1358 | /* check combios for a valid hardcoded EDID - Sun servers */ |
1359 | if (!rdev->is_atom_bios) { | |
1360 | /* check for hardcoded EDID in BIOS */ | |
1361 | radeon_combios_check_hardcoded_edid(rdev); | |
1362 | } | |
1363 | ||
dfee5614 | 1364 | /* allocate crtcs */ |
18917b60 | 1365 | for (i = 0; i < rdev->num_crtc; i++) { |
771fe6b9 JG |
1366 | radeon_crtc_init(rdev->ddev, i); |
1367 | } | |
1368 | ||
1369 | /* okay we should have all the bios connectors */ | |
1370 | ret = radeon_setup_enc_conn(rdev->ddev); | |
1371 | if (!ret) { | |
1372 | return ret; | |
1373 | } | |
ac89af1e | 1374 | |
3fa47d9e AD |
1375 | /* init dig PHYs, disp eng pll */ |
1376 | if (rdev->is_atom_bios) { | |
ac89af1e | 1377 | radeon_atom_encoder_init(rdev); |
f3f1f03e | 1378 | radeon_atom_disp_eng_pll_init(rdev); |
3fa47d9e | 1379 | } |
ac89af1e | 1380 | |
d4877cf2 AD |
1381 | /* initialize hpd */ |
1382 | radeon_hpd_init(rdev); | |
38651674 | 1383 | |
0783986a AD |
1384 | /* setup afmt */ |
1385 | radeon_afmt_init(rdev); | |
1386 | ||
ce8f5370 AD |
1387 | /* Initialize power management */ |
1388 | radeon_pm_init(rdev); | |
1389 | ||
38651674 | 1390 | radeon_fbdev_init(rdev); |
eb1f8e4f DA |
1391 | drm_kms_helper_poll_init(rdev->ddev); |
1392 | ||
771fe6b9 JG |
1393 | return 0; |
1394 | } | |
1395 | ||
1396 | void radeon_modeset_fini(struct radeon_device *rdev) | |
1397 | { | |
38651674 | 1398 | radeon_fbdev_fini(rdev); |
3c537889 | 1399 | kfree(rdev->mode_info.bios_hardcoded_edid); |
ce8f5370 | 1400 | radeon_pm_fini(rdev); |
3c537889 | 1401 | |
771fe6b9 | 1402 | if (rdev->mode_info.mode_config_initialized) { |
0783986a | 1403 | radeon_afmt_fini(rdev); |
eb1f8e4f | 1404 | drm_kms_helper_poll_fini(rdev->ddev); |
d4877cf2 | 1405 | radeon_hpd_fini(rdev); |
771fe6b9 JG |
1406 | drm_mode_config_cleanup(rdev->ddev); |
1407 | rdev->mode_info.mode_config_initialized = false; | |
1408 | } | |
f376b94f AD |
1409 | /* free i2c buses */ |
1410 | radeon_i2c_fini(rdev); | |
771fe6b9 JG |
1411 | } |
1412 | ||
e811f5ae | 1413 | static bool is_hdtv_mode(const struct drm_display_mode *mode) |
039ed2d9 AD |
1414 | { |
1415 | /* try and guess if this is a tv or a monitor */ | |
1416 | if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ | |
1417 | (mode->vdisplay == 576) || /* 576p */ | |
1418 | (mode->vdisplay == 720) || /* 720p */ | |
1419 | (mode->vdisplay == 1080)) /* 1080p */ | |
1420 | return true; | |
1421 | else | |
1422 | return false; | |
1423 | } | |
1424 | ||
c93bb85b | 1425 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
e811f5ae | 1426 | const struct drm_display_mode *mode, |
c93bb85b | 1427 | struct drm_display_mode *adjusted_mode) |
771fe6b9 | 1428 | { |
c93bb85b | 1429 | struct drm_device *dev = crtc->dev; |
5b1714d3 | 1430 | struct radeon_device *rdev = dev->dev_private; |
c93bb85b JG |
1431 | struct drm_encoder *encoder; |
1432 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1433 | struct radeon_encoder *radeon_encoder; | |
5b1714d3 AD |
1434 | struct drm_connector *connector; |
1435 | struct radeon_connector *radeon_connector; | |
c93bb85b | 1436 | bool first = true; |
d65d65b1 AD |
1437 | u32 src_v = 1, dst_v = 1; |
1438 | u32 src_h = 1, dst_h = 1; | |
771fe6b9 | 1439 | |
5b1714d3 AD |
1440 | radeon_crtc->h_border = 0; |
1441 | radeon_crtc->v_border = 0; | |
1442 | ||
c93bb85b | 1443 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
c93bb85b JG |
1444 | if (encoder->crtc != crtc) |
1445 | continue; | |
d65d65b1 | 1446 | radeon_encoder = to_radeon_encoder(encoder); |
5b1714d3 AD |
1447 | connector = radeon_get_connector_for_encoder(encoder); |
1448 | radeon_connector = to_radeon_connector(connector); | |
1449 | ||
c93bb85b | 1450 | if (first) { |
80297e87 AD |
1451 | /* set scaling */ |
1452 | if (radeon_encoder->rmx_type == RMX_OFF) | |
1453 | radeon_crtc->rmx_type = RMX_OFF; | |
1454 | else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || | |
1455 | mode->vdisplay < radeon_encoder->native_mode.vdisplay) | |
1456 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; | |
1457 | else | |
1458 | radeon_crtc->rmx_type = RMX_OFF; | |
1459 | /* copy native mode */ | |
c93bb85b | 1460 | memcpy(&radeon_crtc->native_mode, |
80297e87 | 1461 | &radeon_encoder->native_mode, |
de2103e4 | 1462 | sizeof(struct drm_display_mode)); |
ff32a59d AD |
1463 | src_v = crtc->mode.vdisplay; |
1464 | dst_v = radeon_crtc->native_mode.vdisplay; | |
1465 | src_h = crtc->mode.hdisplay; | |
1466 | dst_h = radeon_crtc->native_mode.hdisplay; | |
5b1714d3 AD |
1467 | |
1468 | /* fix up for overscan on hdmi */ | |
1469 | if (ASIC_IS_AVIVO(rdev) && | |
e6db0da0 | 1470 | (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && |
5b1714d3 AD |
1471 | ((radeon_encoder->underscan_type == UNDERSCAN_ON) || |
1472 | ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && | |
039ed2d9 AD |
1473 | drm_detect_hdmi_monitor(radeon_connector->edid) && |
1474 | is_hdtv_mode(mode)))) { | |
5bccf5e3 MG |
1475 | if (radeon_encoder->underscan_hborder != 0) |
1476 | radeon_crtc->h_border = radeon_encoder->underscan_hborder; | |
1477 | else | |
1478 | radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; | |
1479 | if (radeon_encoder->underscan_vborder != 0) | |
1480 | radeon_crtc->v_border = radeon_encoder->underscan_vborder; | |
1481 | else | |
1482 | radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; | |
5b1714d3 AD |
1483 | radeon_crtc->rmx_type = RMX_FULL; |
1484 | src_v = crtc->mode.vdisplay; | |
1485 | dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); | |
1486 | src_h = crtc->mode.hdisplay; | |
1487 | dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); | |
1488 | } | |
c93bb85b JG |
1489 | first = false; |
1490 | } else { | |
1491 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { | |
1492 | /* WARNING: Right now this can't happen but | |
1493 | * in the future we need to check that scaling | |
d65d65b1 | 1494 | * are consistent across different encoder |
c93bb85b JG |
1495 | * (ie all encoder can work with the same |
1496 | * scaling). | |
1497 | */ | |
d65d65b1 | 1498 | DRM_ERROR("Scaling not consistent across encoder.\n"); |
c93bb85b JG |
1499 | return false; |
1500 | } | |
771fe6b9 JG |
1501 | } |
1502 | } | |
c93bb85b JG |
1503 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1504 | fixed20_12 a, b; | |
d65d65b1 AD |
1505 | a.full = dfixed_const(src_v); |
1506 | b.full = dfixed_const(dst_v); | |
68adac5e | 1507 | radeon_crtc->vsc.full = dfixed_div(a, b); |
d65d65b1 AD |
1508 | a.full = dfixed_const(src_h); |
1509 | b.full = dfixed_const(dst_h); | |
68adac5e | 1510 | radeon_crtc->hsc.full = dfixed_div(a, b); |
771fe6b9 | 1511 | } else { |
68adac5e BS |
1512 | radeon_crtc->vsc.full = dfixed_const(1); |
1513 | radeon_crtc->hsc.full = dfixed_const(1); | |
771fe6b9 | 1514 | } |
c93bb85b | 1515 | return true; |
771fe6b9 | 1516 | } |
6383cf7d MK |
1517 | |
1518 | /* | |
1519 | * Retrieve current video scanout position of crtc on a given gpu. | |
1520 | * | |
f5a80209 | 1521 | * \param dev Device to query. |
6383cf7d MK |
1522 | * \param crtc Crtc to query. |
1523 | * \param *vpos Location where vertical scanout position should be stored. | |
1524 | * \param *hpos Location where horizontal scanout position should go. | |
1525 | * | |
1526 | * Returns vpos as a positive number while in active scanout area. | |
1527 | * Returns vpos as a negative number inside vblank, counting the number | |
1528 | * of scanlines to go until end of vblank, e.g., -1 means "one scanline | |
1529 | * until start of active scanout / end of vblank." | |
1530 | * | |
1531 | * \return Flags, or'ed together as follows: | |
1532 | * | |
25985edc | 1533 | * DRM_SCANOUTPOS_VALID = Query successful. |
f5a80209 MK |
1534 | * DRM_SCANOUTPOS_INVBL = Inside vblank. |
1535 | * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of | |
6383cf7d MK |
1536 | * this flag means that returned position may be offset by a constant but |
1537 | * unknown small number of scanlines wrt. real scanout position. | |
1538 | * | |
1539 | */ | |
f5a80209 | 1540 | int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos) |
6383cf7d MK |
1541 | { |
1542 | u32 stat_crtc = 0, vbl = 0, position = 0; | |
1543 | int vbl_start, vbl_end, vtotal, ret = 0; | |
1544 | bool in_vbl = true; | |
1545 | ||
f5a80209 MK |
1546 | struct radeon_device *rdev = dev->dev_private; |
1547 | ||
6383cf7d MK |
1548 | if (ASIC_IS_DCE4(rdev)) { |
1549 | if (crtc == 0) { | |
1550 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1551 | EVERGREEN_CRTC0_REGISTER_OFFSET); | |
1552 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1553 | EVERGREEN_CRTC0_REGISTER_OFFSET); | |
f5a80209 | 1554 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1555 | } |
1556 | if (crtc == 1) { | |
1557 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1558 | EVERGREEN_CRTC1_REGISTER_OFFSET); | |
1559 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1560 | EVERGREEN_CRTC1_REGISTER_OFFSET); | |
f5a80209 | 1561 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1562 | } |
1563 | if (crtc == 2) { | |
1564 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1565 | EVERGREEN_CRTC2_REGISTER_OFFSET); | |
1566 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1567 | EVERGREEN_CRTC2_REGISTER_OFFSET); | |
f5a80209 | 1568 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1569 | } |
1570 | if (crtc == 3) { | |
1571 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1572 | EVERGREEN_CRTC3_REGISTER_OFFSET); | |
1573 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1574 | EVERGREEN_CRTC3_REGISTER_OFFSET); | |
f5a80209 | 1575 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1576 | } |
1577 | if (crtc == 4) { | |
1578 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1579 | EVERGREEN_CRTC4_REGISTER_OFFSET); | |
1580 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1581 | EVERGREEN_CRTC4_REGISTER_OFFSET); | |
f5a80209 | 1582 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1583 | } |
1584 | if (crtc == 5) { | |
1585 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1586 | EVERGREEN_CRTC5_REGISTER_OFFSET); | |
1587 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1588 | EVERGREEN_CRTC5_REGISTER_OFFSET); | |
f5a80209 | 1589 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1590 | } |
1591 | } else if (ASIC_IS_AVIVO(rdev)) { | |
1592 | if (crtc == 0) { | |
1593 | vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); | |
1594 | position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); | |
f5a80209 | 1595 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1596 | } |
1597 | if (crtc == 1) { | |
1598 | vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); | |
1599 | position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); | |
f5a80209 | 1600 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1601 | } |
1602 | } else { | |
1603 | /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ | |
1604 | if (crtc == 0) { | |
1605 | /* Assume vbl_end == 0, get vbl_start from | |
1606 | * upper 16 bits. | |
1607 | */ | |
1608 | vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & | |
1609 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; | |
1610 | /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ | |
1611 | position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; | |
1612 | stat_crtc = RREG32(RADEON_CRTC_STATUS); | |
1613 | if (!(stat_crtc & 1)) | |
1614 | in_vbl = false; | |
1615 | ||
f5a80209 | 1616 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1617 | } |
1618 | if (crtc == 1) { | |
1619 | vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & | |
1620 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; | |
1621 | position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; | |
1622 | stat_crtc = RREG32(RADEON_CRTC2_STATUS); | |
1623 | if (!(stat_crtc & 1)) | |
1624 | in_vbl = false; | |
1625 | ||
f5a80209 | 1626 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1627 | } |
1628 | } | |
1629 | ||
1630 | /* Decode into vertical and horizontal scanout position. */ | |
1631 | *vpos = position & 0x1fff; | |
1632 | *hpos = (position >> 16) & 0x1fff; | |
1633 | ||
1634 | /* Valid vblank area boundaries from gpu retrieved? */ | |
1635 | if (vbl > 0) { | |
1636 | /* Yes: Decode. */ | |
f5a80209 | 1637 | ret |= DRM_SCANOUTPOS_ACCURATE; |
6383cf7d MK |
1638 | vbl_start = vbl & 0x1fff; |
1639 | vbl_end = (vbl >> 16) & 0x1fff; | |
1640 | } | |
1641 | else { | |
1642 | /* No: Fake something reasonable which gives at least ok results. */ | |
f5a80209 | 1643 | vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; |
6383cf7d MK |
1644 | vbl_end = 0; |
1645 | } | |
1646 | ||
1647 | /* Test scanout position against vblank region. */ | |
1648 | if ((*vpos < vbl_start) && (*vpos >= vbl_end)) | |
1649 | in_vbl = false; | |
1650 | ||
1651 | /* Check if inside vblank area and apply corrective offsets: | |
1652 | * vpos will then be >=0 in video scanout area, but negative | |
1653 | * within vblank area, counting down the number of lines until | |
1654 | * start of scanout. | |
1655 | */ | |
1656 | ||
1657 | /* Inside "upper part" of vblank area? Apply corrective offset if so: */ | |
1658 | if (in_vbl && (*vpos >= vbl_start)) { | |
f5a80209 | 1659 | vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; |
6383cf7d MK |
1660 | *vpos = *vpos - vtotal; |
1661 | } | |
1662 | ||
1663 | /* Correct for shifted end of vbl at vbl_end. */ | |
1664 | *vpos = *vpos - vbl_end; | |
1665 | ||
1666 | /* In vblank? */ | |
1667 | if (in_vbl) | |
f5a80209 | 1668 | ret |= DRM_SCANOUTPOS_INVBL; |
6383cf7d MK |
1669 | |
1670 | return ret; | |
1671 | } |