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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include "drmP.h" | |
27 | #include "radeon_drm.h" | |
28 | #include "radeon.h" | |
29 | ||
30 | #include "atom.h" | |
31 | #include <asm/div64.h> | |
32 | ||
33 | #include "drm_crtc_helper.h" | |
34 | #include "drm_edid.h" | |
35 | ||
36 | static int radeon_ddc_dump(struct drm_connector *connector); | |
37 | ||
38 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) | |
39 | { | |
40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
41 | struct drm_device *dev = crtc->dev; | |
42 | struct radeon_device *rdev = dev->dev_private; | |
43 | int i; | |
44 | ||
45 | DRM_DEBUG("%d\n", radeon_crtc->crtc_id); | |
46 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); | |
47 | ||
48 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); | |
49 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); | |
50 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); | |
51 | ||
52 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); | |
53 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); | |
54 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); | |
55 | ||
56 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); | |
57 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); | |
58 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); | |
59 | ||
60 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); | |
61 | for (i = 0; i < 256; i++) { | |
62 | WREG32(AVIVO_DC_LUT_30_COLOR, | |
63 | (radeon_crtc->lut_r[i] << 20) | | |
64 | (radeon_crtc->lut_g[i] << 10) | | |
65 | (radeon_crtc->lut_b[i] << 0)); | |
66 | } | |
67 | ||
68 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); | |
69 | } | |
70 | ||
71 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) | |
72 | { | |
73 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
74 | struct drm_device *dev = crtc->dev; | |
75 | struct radeon_device *rdev = dev->dev_private; | |
76 | int i; | |
77 | uint32_t dac2_cntl; | |
78 | ||
79 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); | |
80 | if (radeon_crtc->crtc_id == 0) | |
81 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; | |
82 | else | |
83 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; | |
84 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); | |
85 | ||
86 | WREG8(RADEON_PALETTE_INDEX, 0); | |
87 | for (i = 0; i < 256; i++) { | |
88 | WREG32(RADEON_PALETTE_30_DATA, | |
89 | (radeon_crtc->lut_r[i] << 20) | | |
90 | (radeon_crtc->lut_g[i] << 10) | | |
91 | (radeon_crtc->lut_b[i] << 0)); | |
92 | } | |
93 | } | |
94 | ||
95 | void radeon_crtc_load_lut(struct drm_crtc *crtc) | |
96 | { | |
97 | struct drm_device *dev = crtc->dev; | |
98 | struct radeon_device *rdev = dev->dev_private; | |
99 | ||
100 | if (!crtc->enabled) | |
101 | return; | |
102 | ||
103 | if (ASIC_IS_AVIVO(rdev)) | |
104 | avivo_crtc_load_lut(crtc); | |
105 | else | |
106 | legacy_crtc_load_lut(crtc); | |
107 | } | |
108 | ||
b8c00ac5 | 109 | /** Sets the color ramps on behalf of fbcon */ |
771fe6b9 JG |
110 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
111 | u16 blue, int regno) | |
112 | { | |
113 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
114 | ||
771fe6b9 JG |
115 | radeon_crtc->lut_r[regno] = red >> 6; |
116 | radeon_crtc->lut_g[regno] = green >> 6; | |
117 | radeon_crtc->lut_b[regno] = blue >> 6; | |
118 | } | |
119 | ||
b8c00ac5 DA |
120 | /** Gets the color ramps on behalf of fbcon */ |
121 | void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, | |
122 | u16 *blue, int regno) | |
123 | { | |
124 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
125 | ||
126 | *red = radeon_crtc->lut_r[regno] << 6; | |
127 | *green = radeon_crtc->lut_g[regno] << 6; | |
128 | *blue = radeon_crtc->lut_b[regno] << 6; | |
129 | } | |
130 | ||
771fe6b9 JG |
131 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
132 | u16 *blue, uint32_t size) | |
133 | { | |
134 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
b8c00ac5 | 135 | int i; |
771fe6b9 JG |
136 | |
137 | if (size != 256) { | |
138 | return; | |
139 | } | |
771fe6b9 | 140 | |
b8c00ac5 DA |
141 | /* userspace palettes are always correct as is */ |
142 | for (i = 0; i < 256; i++) { | |
143 | radeon_crtc->lut_r[i] = red[i] >> 6; | |
144 | radeon_crtc->lut_g[i] = green[i] >> 6; | |
145 | radeon_crtc->lut_b[i] = blue[i] >> 6; | |
771fe6b9 | 146 | } |
771fe6b9 JG |
147 | radeon_crtc_load_lut(crtc); |
148 | } | |
149 | ||
150 | static void radeon_crtc_destroy(struct drm_crtc *crtc) | |
151 | { | |
152 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
153 | ||
771fe6b9 JG |
154 | drm_crtc_cleanup(crtc); |
155 | kfree(radeon_crtc); | |
156 | } | |
157 | ||
158 | static const struct drm_crtc_funcs radeon_crtc_funcs = { | |
159 | .cursor_set = radeon_crtc_cursor_set, | |
160 | .cursor_move = radeon_crtc_cursor_move, | |
161 | .gamma_set = radeon_crtc_gamma_set, | |
162 | .set_config = drm_crtc_helper_set_config, | |
163 | .destroy = radeon_crtc_destroy, | |
164 | }; | |
165 | ||
166 | static void radeon_crtc_init(struct drm_device *dev, int index) | |
167 | { | |
168 | struct radeon_device *rdev = dev->dev_private; | |
169 | struct radeon_crtc *radeon_crtc; | |
170 | int i; | |
171 | ||
172 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
173 | if (radeon_crtc == NULL) | |
174 | return; | |
175 | ||
176 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); | |
177 | ||
178 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); | |
179 | radeon_crtc->crtc_id = index; | |
c93bb85b | 180 | rdev->mode_info.crtcs[index] = radeon_crtc; |
771fe6b9 | 181 | |
785b93ef | 182 | #if 0 |
771fe6b9 JG |
183 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
184 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); | |
185 | radeon_crtc->mode_set.num_connectors = 0; | |
785b93ef | 186 | #endif |
771fe6b9 JG |
187 | |
188 | for (i = 0; i < 256; i++) { | |
189 | radeon_crtc->lut_r[i] = i << 2; | |
190 | radeon_crtc->lut_g[i] = i << 2; | |
191 | radeon_crtc->lut_b[i] = i << 2; | |
192 | } | |
193 | ||
194 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) | |
195 | radeon_atombios_init_crtc(dev, radeon_crtc); | |
196 | else | |
197 | radeon_legacy_init_crtc(dev, radeon_crtc); | |
198 | } | |
199 | ||
200 | static const char *encoder_names[34] = { | |
201 | "NONE", | |
202 | "INTERNAL_LVDS", | |
203 | "INTERNAL_TMDS1", | |
204 | "INTERNAL_TMDS2", | |
205 | "INTERNAL_DAC1", | |
206 | "INTERNAL_DAC2", | |
207 | "INTERNAL_SDVOA", | |
208 | "INTERNAL_SDVOB", | |
209 | "SI170B", | |
210 | "CH7303", | |
211 | "CH7301", | |
212 | "INTERNAL_DVO1", | |
213 | "EXTERNAL_SDVOA", | |
214 | "EXTERNAL_SDVOB", | |
215 | "TITFP513", | |
216 | "INTERNAL_LVTM1", | |
217 | "VT1623", | |
218 | "HDMI_SI1930", | |
219 | "HDMI_INTERNAL", | |
220 | "INTERNAL_KLDSCP_TMDS1", | |
221 | "INTERNAL_KLDSCP_DVO1", | |
222 | "INTERNAL_KLDSCP_DAC1", | |
223 | "INTERNAL_KLDSCP_DAC2", | |
224 | "SI178", | |
225 | "MVPU_FPGA", | |
226 | "INTERNAL_DDI", | |
227 | "VT1625", | |
228 | "HDMI_SI1932", | |
229 | "DP_AN9801", | |
230 | "DP_DP501", | |
231 | "INTERNAL_UNIPHY", | |
232 | "INTERNAL_KLDSCP_LVTMA", | |
233 | "INTERNAL_UNIPHY1", | |
234 | "INTERNAL_UNIPHY2", | |
235 | }; | |
236 | ||
237 | static const char *connector_names[13] = { | |
238 | "Unknown", | |
239 | "VGA", | |
240 | "DVI-I", | |
241 | "DVI-D", | |
242 | "DVI-A", | |
243 | "Composite", | |
244 | "S-video", | |
245 | "LVDS", | |
246 | "Component", | |
247 | "DIN", | |
248 | "DisplayPort", | |
249 | "HDMI-A", | |
250 | "HDMI-B", | |
251 | }; | |
252 | ||
253 | static void radeon_print_display_setup(struct drm_device *dev) | |
254 | { | |
255 | struct drm_connector *connector; | |
256 | struct radeon_connector *radeon_connector; | |
257 | struct drm_encoder *encoder; | |
258 | struct radeon_encoder *radeon_encoder; | |
259 | uint32_t devices; | |
260 | int i = 0; | |
261 | ||
262 | DRM_INFO("Radeon Display Connectors\n"); | |
263 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
264 | radeon_connector = to_radeon_connector(connector); | |
265 | DRM_INFO("Connector %d:\n", i); | |
266 | DRM_INFO(" %s\n", connector_names[connector->connector_type]); | |
267 | if (radeon_connector->ddc_bus) | |
268 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", | |
269 | radeon_connector->ddc_bus->rec.mask_clk_reg, | |
270 | radeon_connector->ddc_bus->rec.mask_data_reg, | |
271 | radeon_connector->ddc_bus->rec.a_clk_reg, | |
272 | radeon_connector->ddc_bus->rec.a_data_reg, | |
9b9fe724 AD |
273 | radeon_connector->ddc_bus->rec.en_clk_reg, |
274 | radeon_connector->ddc_bus->rec.en_data_reg, | |
275 | radeon_connector->ddc_bus->rec.y_clk_reg, | |
276 | radeon_connector->ddc_bus->rec.y_data_reg); | |
771fe6b9 JG |
277 | DRM_INFO(" Encoders:\n"); |
278 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
279 | radeon_encoder = to_radeon_encoder(encoder); | |
280 | devices = radeon_encoder->devices & radeon_connector->devices; | |
281 | if (devices) { | |
282 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) | |
283 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
284 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) | |
285 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
286 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) | |
287 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
288 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) | |
289 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
290 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) | |
291 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
292 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) | |
293 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
294 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) | |
295 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
296 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) | |
297 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
298 | if (devices & ATOM_DEVICE_TV1_SUPPORT) | |
299 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
300 | if (devices & ATOM_DEVICE_CV_SUPPORT) | |
301 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
302 | } | |
303 | } | |
304 | i++; | |
305 | } | |
306 | } | |
307 | ||
4ce001ab | 308 | static bool radeon_setup_enc_conn(struct drm_device *dev) |
771fe6b9 JG |
309 | { |
310 | struct radeon_device *rdev = dev->dev_private; | |
311 | struct drm_connector *drm_connector; | |
312 | bool ret = false; | |
313 | ||
314 | if (rdev->bios) { | |
315 | if (rdev->is_atom_bios) { | |
316 | if (rdev->family >= CHIP_R600) | |
317 | ret = radeon_get_atom_connector_info_from_object_table(dev); | |
318 | else | |
319 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); | |
320 | } else | |
321 | ret = radeon_get_legacy_connector_info_from_bios(dev); | |
322 | } else { | |
323 | if (!ASIC_IS_AVIVO(rdev)) | |
324 | ret = radeon_get_legacy_connector_info_from_table(dev); | |
325 | } | |
326 | if (ret) { | |
1f3b6a45 | 327 | radeon_setup_encoder_clones(dev); |
771fe6b9 JG |
328 | radeon_print_display_setup(dev); |
329 | list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) | |
330 | radeon_ddc_dump(drm_connector); | |
331 | } | |
332 | ||
333 | return ret; | |
334 | } | |
335 | ||
336 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) | |
337 | { | |
771fe6b9 JG |
338 | int ret = 0; |
339 | ||
746c1aa4 DA |
340 | if (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) { |
341 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; | |
9fa05c98 AD |
342 | if (dig->dp_i2c_bus) |
343 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); | |
746c1aa4 | 344 | } |
771fe6b9 JG |
345 | if (!radeon_connector->ddc_bus) |
346 | return -1; | |
4ce001ab | 347 | if (!radeon_connector->edid) { |
ab1e9ea0 | 348 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); |
0294cf4f | 349 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); |
ab1e9ea0 | 350 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); |
0294cf4f AD |
351 | } |
352 | ||
353 | if (radeon_connector->edid) { | |
354 | drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); | |
355 | ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); | |
771fe6b9 JG |
356 | return ret; |
357 | } | |
358 | drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); | |
42dea5dd | 359 | return 0; |
771fe6b9 JG |
360 | } |
361 | ||
362 | static int radeon_ddc_dump(struct drm_connector *connector) | |
363 | { | |
364 | struct edid *edid; | |
365 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
366 | int ret = 0; | |
367 | ||
368 | if (!radeon_connector->ddc_bus) | |
369 | return -1; | |
ab1e9ea0 | 370 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); |
771fe6b9 | 371 | edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); |
ab1e9ea0 | 372 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); |
771fe6b9 JG |
373 | if (edid) { |
374 | kfree(edid); | |
375 | } | |
376 | return ret; | |
377 | } | |
378 | ||
379 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) | |
380 | { | |
381 | uint64_t mod; | |
382 | ||
383 | n += d / 2; | |
384 | ||
385 | mod = do_div(n, d); | |
386 | return n; | |
387 | } | |
388 | ||
389 | void radeon_compute_pll(struct radeon_pll *pll, | |
390 | uint64_t freq, | |
391 | uint32_t *dot_clock_p, | |
392 | uint32_t *fb_div_p, | |
393 | uint32_t *frac_fb_div_p, | |
394 | uint32_t *ref_div_p, | |
395 | uint32_t *post_div_p, | |
396 | int flags) | |
397 | { | |
398 | uint32_t min_ref_div = pll->min_ref_div; | |
399 | uint32_t max_ref_div = pll->max_ref_div; | |
400 | uint32_t min_fractional_feed_div = 0; | |
401 | uint32_t max_fractional_feed_div = 0; | |
402 | uint32_t best_vco = pll->best_vco; | |
403 | uint32_t best_post_div = 1; | |
404 | uint32_t best_ref_div = 1; | |
405 | uint32_t best_feedback_div = 1; | |
406 | uint32_t best_frac_feedback_div = 0; | |
407 | uint32_t best_freq = -1; | |
408 | uint32_t best_error = 0xffffffff; | |
409 | uint32_t best_vco_diff = 1; | |
410 | uint32_t post_div; | |
411 | ||
412 | DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); | |
413 | freq = freq * 1000; | |
414 | ||
415 | if (flags & RADEON_PLL_USE_REF_DIV) | |
416 | min_ref_div = max_ref_div = pll->reference_div; | |
417 | else { | |
418 | while (min_ref_div < max_ref_div-1) { | |
419 | uint32_t mid = (min_ref_div + max_ref_div) / 2; | |
420 | uint32_t pll_in = pll->reference_freq / mid; | |
421 | if (pll_in < pll->pll_in_min) | |
422 | max_ref_div = mid; | |
423 | else if (pll_in > pll->pll_in_max) | |
424 | min_ref_div = mid; | |
425 | else | |
426 | break; | |
427 | } | |
428 | } | |
429 | ||
430 | if (flags & RADEON_PLL_USE_FRAC_FB_DIV) { | |
431 | min_fractional_feed_div = pll->min_frac_feedback_div; | |
432 | max_fractional_feed_div = pll->max_frac_feedback_div; | |
433 | } | |
434 | ||
435 | for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { | |
436 | uint32_t ref_div; | |
437 | ||
438 | if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) | |
439 | continue; | |
440 | ||
441 | /* legacy radeons only have a few post_divs */ | |
442 | if (flags & RADEON_PLL_LEGACY) { | |
443 | if ((post_div == 5) || | |
444 | (post_div == 7) || | |
445 | (post_div == 9) || | |
446 | (post_div == 10) || | |
447 | (post_div == 11) || | |
448 | (post_div == 13) || | |
449 | (post_div == 14) || | |
450 | (post_div == 15)) | |
451 | continue; | |
452 | } | |
453 | ||
454 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { | |
455 | uint32_t feedback_div, current_freq = 0, error, vco_diff; | |
456 | uint32_t pll_in = pll->reference_freq / ref_div; | |
457 | uint32_t min_feed_div = pll->min_feedback_div; | |
458 | uint32_t max_feed_div = pll->max_feedback_div + 1; | |
459 | ||
460 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) | |
461 | continue; | |
462 | ||
463 | while (min_feed_div < max_feed_div) { | |
464 | uint32_t vco; | |
465 | uint32_t min_frac_feed_div = min_fractional_feed_div; | |
466 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; | |
467 | uint32_t frac_feedback_div; | |
468 | uint64_t tmp; | |
469 | ||
470 | feedback_div = (min_feed_div + max_feed_div) / 2; | |
471 | ||
472 | tmp = (uint64_t)pll->reference_freq * feedback_div; | |
473 | vco = radeon_div(tmp, ref_div); | |
474 | ||
475 | if (vco < pll->pll_out_min) { | |
476 | min_feed_div = feedback_div + 1; | |
477 | continue; | |
478 | } else if (vco > pll->pll_out_max) { | |
479 | max_feed_div = feedback_div; | |
480 | continue; | |
481 | } | |
482 | ||
483 | while (min_frac_feed_div < max_frac_feed_div) { | |
484 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; | |
485 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; | |
486 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; | |
487 | current_freq = radeon_div(tmp, ref_div * post_div); | |
488 | ||
d0e275a9 AD |
489 | if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
490 | error = freq - current_freq; | |
491 | error = error < 0 ? 0xffffffff : error; | |
492 | } else | |
493 | error = abs(current_freq - freq); | |
771fe6b9 JG |
494 | vco_diff = abs(vco - best_vco); |
495 | ||
496 | if ((best_vco == 0 && error < best_error) || | |
497 | (best_vco != 0 && | |
498 | (error < best_error - 100 || | |
499 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { | |
500 | best_post_div = post_div; | |
501 | best_ref_div = ref_div; | |
502 | best_feedback_div = feedback_div; | |
503 | best_frac_feedback_div = frac_feedback_div; | |
504 | best_freq = current_freq; | |
505 | best_error = error; | |
506 | best_vco_diff = vco_diff; | |
507 | } else if (current_freq == freq) { | |
508 | if (best_freq == -1) { | |
509 | best_post_div = post_div; | |
510 | best_ref_div = ref_div; | |
511 | best_feedback_div = feedback_div; | |
512 | best_frac_feedback_div = frac_feedback_div; | |
513 | best_freq = current_freq; | |
514 | best_error = error; | |
515 | best_vco_diff = vco_diff; | |
516 | } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || | |
517 | ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || | |
518 | ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || | |
519 | ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || | |
520 | ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || | |
521 | ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { | |
522 | best_post_div = post_div; | |
523 | best_ref_div = ref_div; | |
524 | best_feedback_div = feedback_div; | |
525 | best_frac_feedback_div = frac_feedback_div; | |
526 | best_freq = current_freq; | |
527 | best_error = error; | |
528 | best_vco_diff = vco_diff; | |
529 | } | |
530 | } | |
531 | if (current_freq < freq) | |
532 | min_frac_feed_div = frac_feedback_div + 1; | |
533 | else | |
534 | max_frac_feed_div = frac_feedback_div; | |
535 | } | |
536 | if (current_freq < freq) | |
537 | min_feed_div = feedback_div + 1; | |
538 | else | |
539 | max_feed_div = feedback_div; | |
540 | } | |
541 | } | |
542 | } | |
543 | ||
544 | *dot_clock_p = best_freq / 10000; | |
545 | *fb_div_p = best_feedback_div; | |
546 | *frac_fb_div_p = best_frac_feedback_div; | |
547 | *ref_div_p = best_ref_div; | |
548 | *post_div_p = best_post_div; | |
549 | } | |
550 | ||
551 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
552 | { | |
553 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); | |
554 | struct drm_device *dev = fb->dev; | |
555 | ||
556 | if (fb->fbdev) | |
557 | radeonfb_remove(dev, fb); | |
558 | ||
559 | if (radeon_fb->obj) { | |
560 | radeon_gem_object_unpin(radeon_fb->obj); | |
561 | mutex_lock(&dev->struct_mutex); | |
562 | drm_gem_object_unreference(radeon_fb->obj); | |
563 | mutex_unlock(&dev->struct_mutex); | |
564 | } | |
565 | drm_framebuffer_cleanup(fb); | |
566 | kfree(radeon_fb); | |
567 | } | |
568 | ||
569 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
570 | struct drm_file *file_priv, | |
571 | unsigned int *handle) | |
572 | { | |
573 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); | |
574 | ||
575 | return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); | |
576 | } | |
577 | ||
578 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { | |
579 | .destroy = radeon_user_framebuffer_destroy, | |
580 | .create_handle = radeon_user_framebuffer_create_handle, | |
581 | }; | |
582 | ||
583 | struct drm_framebuffer * | |
584 | radeon_framebuffer_create(struct drm_device *dev, | |
585 | struct drm_mode_fb_cmd *mode_cmd, | |
586 | struct drm_gem_object *obj) | |
587 | { | |
588 | struct radeon_framebuffer *radeon_fb; | |
589 | ||
590 | radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); | |
591 | if (radeon_fb == NULL) { | |
592 | return NULL; | |
593 | } | |
594 | drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs); | |
595 | drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd); | |
596 | radeon_fb->obj = obj; | |
597 | return &radeon_fb->base; | |
598 | } | |
599 | ||
600 | static struct drm_framebuffer * | |
601 | radeon_user_framebuffer_create(struct drm_device *dev, | |
602 | struct drm_file *file_priv, | |
603 | struct drm_mode_fb_cmd *mode_cmd) | |
604 | { | |
605 | struct drm_gem_object *obj; | |
606 | ||
607 | obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); | |
608 | ||
609 | return radeon_framebuffer_create(dev, mode_cmd, obj); | |
610 | } | |
611 | ||
612 | static const struct drm_mode_config_funcs radeon_mode_funcs = { | |
613 | .fb_create = radeon_user_framebuffer_create, | |
614 | .fb_changed = radeonfb_probe, | |
615 | }; | |
616 | ||
445282db DA |
617 | struct drm_prop_enum_list { |
618 | int type; | |
619 | char *name; | |
620 | }; | |
621 | ||
622 | static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = | |
623 | { { 0, "driver" }, | |
624 | { 1, "bios" }, | |
625 | }; | |
626 | ||
627 | static struct drm_prop_enum_list radeon_tv_std_enum_list[] = | |
628 | { { TV_STD_NTSC, "ntsc" }, | |
629 | { TV_STD_PAL, "pal" }, | |
630 | { TV_STD_PAL_M, "pal-m" }, | |
631 | { TV_STD_PAL_60, "pal-60" }, | |
632 | { TV_STD_NTSC_J, "ntsc-j" }, | |
633 | { TV_STD_SCART_PAL, "scart-pal" }, | |
634 | { TV_STD_PAL_CN, "pal-cn" }, | |
635 | { TV_STD_SECAM, "secam" }, | |
636 | }; | |
637 | ||
638 | int radeon_modeset_create_props(struct radeon_device *rdev) | |
639 | { | |
640 | int i, sz; | |
641 | ||
642 | if (rdev->is_atom_bios) { | |
643 | rdev->mode_info.coherent_mode_property = | |
644 | drm_property_create(rdev->ddev, | |
645 | DRM_MODE_PROP_RANGE, | |
646 | "coherent", 2); | |
647 | if (!rdev->mode_info.coherent_mode_property) | |
648 | return -ENOMEM; | |
649 | ||
650 | rdev->mode_info.coherent_mode_property->values[0] = 0; | |
651 | rdev->mode_info.coherent_mode_property->values[0] = 1; | |
652 | } | |
653 | ||
654 | if (!ASIC_IS_AVIVO(rdev)) { | |
655 | sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); | |
656 | rdev->mode_info.tmds_pll_property = | |
657 | drm_property_create(rdev->ddev, | |
658 | DRM_MODE_PROP_ENUM, | |
659 | "tmds_pll", sz); | |
660 | for (i = 0; i < sz; i++) { | |
661 | drm_property_add_enum(rdev->mode_info.tmds_pll_property, | |
662 | i, | |
663 | radeon_tmds_pll_enum_list[i].type, | |
664 | radeon_tmds_pll_enum_list[i].name); | |
665 | } | |
666 | } | |
667 | ||
668 | rdev->mode_info.load_detect_property = | |
669 | drm_property_create(rdev->ddev, | |
670 | DRM_MODE_PROP_RANGE, | |
671 | "load detection", 2); | |
672 | if (!rdev->mode_info.load_detect_property) | |
673 | return -ENOMEM; | |
674 | rdev->mode_info.load_detect_property->values[0] = 0; | |
675 | rdev->mode_info.load_detect_property->values[0] = 1; | |
676 | ||
677 | drm_mode_create_scaling_mode_property(rdev->ddev); | |
678 | ||
679 | sz = ARRAY_SIZE(radeon_tv_std_enum_list); | |
680 | rdev->mode_info.tv_std_property = | |
681 | drm_property_create(rdev->ddev, | |
682 | DRM_MODE_PROP_ENUM, | |
683 | "tv standard", sz); | |
684 | for (i = 0; i < sz; i++) { | |
685 | drm_property_add_enum(rdev->mode_info.tv_std_property, | |
686 | i, | |
687 | radeon_tv_std_enum_list[i].type, | |
688 | radeon_tv_std_enum_list[i].name); | |
689 | } | |
690 | ||
691 | return 0; | |
692 | } | |
693 | ||
771fe6b9 JG |
694 | int radeon_modeset_init(struct radeon_device *rdev) |
695 | { | |
696 | int num_crtc = 2, i; | |
697 | int ret; | |
698 | ||
699 | drm_mode_config_init(rdev->ddev); | |
700 | rdev->mode_info.mode_config_initialized = true; | |
701 | ||
702 | rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; | |
703 | ||
704 | if (ASIC_IS_AVIVO(rdev)) { | |
705 | rdev->ddev->mode_config.max_width = 8192; | |
706 | rdev->ddev->mode_config.max_height = 8192; | |
707 | } else { | |
708 | rdev->ddev->mode_config.max_width = 4096; | |
709 | rdev->ddev->mode_config.max_height = 4096; | |
710 | } | |
711 | ||
712 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; | |
713 | ||
445282db DA |
714 | ret = radeon_modeset_create_props(rdev); |
715 | if (ret) { | |
716 | return ret; | |
717 | } | |
dfee5614 DA |
718 | |
719 | if (rdev->flags & RADEON_SINGLE_CRTC) | |
720 | num_crtc = 1; | |
721 | ||
722 | /* allocate crtcs */ | |
771fe6b9 JG |
723 | for (i = 0; i < num_crtc; i++) { |
724 | radeon_crtc_init(rdev->ddev, i); | |
725 | } | |
726 | ||
727 | /* okay we should have all the bios connectors */ | |
728 | ret = radeon_setup_enc_conn(rdev->ddev); | |
729 | if (!ret) { | |
730 | return ret; | |
731 | } | |
732 | drm_helper_initial_config(rdev->ddev); | |
733 | return 0; | |
734 | } | |
735 | ||
736 | void radeon_modeset_fini(struct radeon_device *rdev) | |
737 | { | |
738 | if (rdev->mode_info.mode_config_initialized) { | |
739 | drm_mode_config_cleanup(rdev->ddev); | |
740 | rdev->mode_info.mode_config_initialized = false; | |
741 | } | |
742 | } | |
743 | ||
c93bb85b JG |
744 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
745 | struct drm_display_mode *mode, | |
746 | struct drm_display_mode *adjusted_mode) | |
771fe6b9 | 747 | { |
c93bb85b JG |
748 | struct drm_device *dev = crtc->dev; |
749 | struct drm_encoder *encoder; | |
750 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
751 | struct radeon_encoder *radeon_encoder; | |
752 | bool first = true; | |
771fe6b9 | 753 | |
c93bb85b JG |
754 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
755 | radeon_encoder = to_radeon_encoder(encoder); | |
756 | if (encoder->crtc != crtc) | |
757 | continue; | |
758 | if (first) { | |
80297e87 AD |
759 | /* set scaling */ |
760 | if (radeon_encoder->rmx_type == RMX_OFF) | |
761 | radeon_crtc->rmx_type = RMX_OFF; | |
762 | else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || | |
763 | mode->vdisplay < radeon_encoder->native_mode.vdisplay) | |
764 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; | |
765 | else | |
766 | radeon_crtc->rmx_type = RMX_OFF; | |
767 | /* copy native mode */ | |
c93bb85b | 768 | memcpy(&radeon_crtc->native_mode, |
80297e87 | 769 | &radeon_encoder->native_mode, |
de2103e4 | 770 | sizeof(struct drm_display_mode)); |
c93bb85b JG |
771 | first = false; |
772 | } else { | |
773 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { | |
774 | /* WARNING: Right now this can't happen but | |
775 | * in the future we need to check that scaling | |
776 | * are consistent accross different encoder | |
777 | * (ie all encoder can work with the same | |
778 | * scaling). | |
779 | */ | |
780 | DRM_ERROR("Scaling not consistent accross encoder.\n"); | |
781 | return false; | |
782 | } | |
771fe6b9 JG |
783 | } |
784 | } | |
c93bb85b JG |
785 | if (radeon_crtc->rmx_type != RMX_OFF) { |
786 | fixed20_12 a, b; | |
787 | a.full = rfixed_const(crtc->mode.vdisplay); | |
de2103e4 | 788 | b.full = rfixed_const(radeon_crtc->native_mode.hdisplay); |
c93bb85b JG |
789 | radeon_crtc->vsc.full = rfixed_div(a, b); |
790 | a.full = rfixed_const(crtc->mode.hdisplay); | |
de2103e4 | 791 | b.full = rfixed_const(radeon_crtc->native_mode.vdisplay); |
c93bb85b | 792 | radeon_crtc->hsc.full = rfixed_div(a, b); |
771fe6b9 | 793 | } else { |
c93bb85b JG |
794 | radeon_crtc->vsc.full = rfixed_const(1); |
795 | radeon_crtc->hsc.full = rfixed_const(1); | |
771fe6b9 | 796 | } |
c93bb85b | 797 | return true; |
771fe6b9 | 798 | } |