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drm/radeon/kms: enable underscan option for digital connectors
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_display.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include <asm/div64.h>
32
33#include "drm_crtc_helper.h"
34#include "drm_edid.h"
35
36static int radeon_ddc_dump(struct drm_connector *connector);
37
38static void avivo_crtc_load_lut(struct drm_crtc *crtc)
39{
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
43 int i;
44
d9fdaafb 45 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
771fe6b9
JG		 46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
47
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
51
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
55
56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
59
60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61 for (i = 0; i < 256; i++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR,
63 (radeon_crtc->lut_r[i] << 20) |
64 (radeon_crtc->lut_g[i] << 10) |
65 (radeon_crtc->lut_b[i] << 0));
66 }
67
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69}
70
bcc1c2a1
AD		 71static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
72{
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev;
75 struct radeon_device *rdev = dev->dev_private;
76 int i;
77
d9fdaafb 78 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
bcc1c2a1
AD		 79 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
80
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
84
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
88
677d0768
AD		 89 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
bcc1c2a1 91
677d0768 92 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
bcc1c2a1 93 for (i = 0; i < 256; i++) {
677d0768 94 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
bcc1c2a1
AD		 95 (radeon_crtc->lut_r[i] << 20) |
96 (radeon_crtc->lut_g[i] << 10) |
97 (radeon_crtc->lut_b[i] << 0));
98 }
99}
100
771fe6b9
JG		 101static void legacy_crtc_load_lut(struct drm_crtc *crtc)
102{
103 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
104 struct drm_device *dev = crtc->dev;
105 struct radeon_device *rdev = dev->dev_private;
106 int i;
107 uint32_t dac2_cntl;
108
109 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
110 if (radeon_crtc->crtc_id == 0)
111 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
112 else
113 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
114 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
115
116 WREG8(RADEON_PALETTE_INDEX, 0);
117 for (i = 0; i < 256; i++) {
118 WREG32(RADEON_PALETTE_30_DATA,
119 (radeon_crtc->lut_r[i] << 20) |
120 (radeon_crtc->lut_g[i] << 10) |
121 (radeon_crtc->lut_b[i] << 0));
122 }
123}
124
125void radeon_crtc_load_lut(struct drm_crtc *crtc)
126{
127 struct drm_device *dev = crtc->dev;
128 struct radeon_device *rdev = dev->dev_private;
129
130 if (!crtc->enabled)
131 return;
132
bcc1c2a1
AD		 133 if (ASIC_IS_DCE4(rdev))
134 evergreen_crtc_load_lut(crtc);
135 else if (ASIC_IS_AVIVO(rdev))
771fe6b9
JG		 136 avivo_crtc_load_lut(crtc);
137 else
138 legacy_crtc_load_lut(crtc);
139}
140
b8c00ac5 141/** Sets the color ramps on behalf of fbcon */
771fe6b9
JG		 142void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
143 u16 blue, int regno)
144{
145 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
146
771fe6b9
JG		 147 radeon_crtc->lut_r[regno] = red >> 6;
148 radeon_crtc->lut_g[regno] = green >> 6;
149 radeon_crtc->lut_b[regno] = blue >> 6;
150}
151
b8c00ac5
DA		 152/** Gets the color ramps on behalf of fbcon */
153void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
154 u16 *blue, int regno)
155{
156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
157
158 *red = radeon_crtc->lut_r[regno] << 6;
159 *green = radeon_crtc->lut_g[regno] << 6;
160 *blue = radeon_crtc->lut_b[regno] << 6;
161}
162
771fe6b9
JG		 163static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
164 u16 *blue, uint32_t size)
165{
166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
b8c00ac5 167 int i;
771fe6b9
JG		 168
169 if (size != 256) {
170 return;
171 }
771fe6b9 172
b8c00ac5
DA		 173 /* userspace palettes are always correct as is */
174 for (i = 0; i < 256; i++) {
175 radeon_crtc->lut_r[i] = red[i] >> 6;
176 radeon_crtc->lut_g[i] = green[i] >> 6;
177 radeon_crtc->lut_b[i] = blue[i] >> 6;
771fe6b9 178 }
771fe6b9
JG		 179 radeon_crtc_load_lut(crtc);
180}
181
182static void radeon_crtc_destroy(struct drm_crtc *crtc)
183{
184 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
185
771fe6b9
JG		 186 drm_crtc_cleanup(crtc);
187 kfree(radeon_crtc);
188}
189
190static const struct drm_crtc_funcs radeon_crtc_funcs = {
191 .cursor_set = radeon_crtc_cursor_set,
192 .cursor_move = radeon_crtc_cursor_move,
193 .gamma_set = radeon_crtc_gamma_set,
194 .set_config = drm_crtc_helper_set_config,
195 .destroy = radeon_crtc_destroy,
196};
197
198static void radeon_crtc_init(struct drm_device *dev, int index)
199{
200 struct radeon_device *rdev = dev->dev_private;
201 struct radeon_crtc *radeon_crtc;
202 int i;
203
204 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
205 if (radeon_crtc == NULL)
206 return;
207
208 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
209
210 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
211 radeon_crtc->crtc_id = index;
c93bb85b 212 rdev->mode_info.crtcs[index] = radeon_crtc;
771fe6b9 213
785b93ef 214#if 0
771fe6b9
JG		 215 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
216 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
217 radeon_crtc->mode_set.num_connectors = 0;
785b93ef 218#endif
771fe6b9
JG		 219
220 for (i = 0; i < 256; i++) {
221 radeon_crtc->lut_r[i] = i << 2;
222 radeon_crtc->lut_g[i] = i << 2;
223 radeon_crtc->lut_b[i] = i << 2;
224 }
225
226 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
227 radeon_atombios_init_crtc(dev, radeon_crtc);
228 else
229 radeon_legacy_init_crtc(dev, radeon_crtc);
230}
231
232static const char *encoder_names[34] = {
233 "NONE",
234 "INTERNAL_LVDS",
235 "INTERNAL_TMDS1",
236 "INTERNAL_TMDS2",
237 "INTERNAL_DAC1",
238 "INTERNAL_DAC2",
239 "INTERNAL_SDVOA",
240 "INTERNAL_SDVOB",
241 "SI170B",
242 "CH7303",
243 "CH7301",
244 "INTERNAL_DVO1",
245 "EXTERNAL_SDVOA",
246 "EXTERNAL_SDVOB",
247 "TITFP513",
248 "INTERNAL_LVTM1",
249 "VT1623",
250 "HDMI_SI1930",
251 "HDMI_INTERNAL",
252 "INTERNAL_KLDSCP_TMDS1",
253 "INTERNAL_KLDSCP_DVO1",
254 "INTERNAL_KLDSCP_DAC1",
255 "INTERNAL_KLDSCP_DAC2",
256 "SI178",
257 "MVPU_FPGA",
258 "INTERNAL_DDI",
259 "VT1625",
260 "HDMI_SI1932",
261 "DP_AN9801",
262 "DP_DP501",
263 "INTERNAL_UNIPHY",
264 "INTERNAL_KLDSCP_LVTMA",
265 "INTERNAL_UNIPHY1",
266 "INTERNAL_UNIPHY2",
267};
268
196c58d2 269static const char *connector_names[15] = {
771fe6b9
JG		 270 "Unknown",
271 "VGA",
272 "DVI-I",
273 "DVI-D",
274 "DVI-A",
275 "Composite",
276 "S-video",
277 "LVDS",
278 "Component",
279 "DIN",
280 "DisplayPort",
281 "HDMI-A",
282 "HDMI-B",
196c58d2
AD		 283 "TV",
284 "eDP",
771fe6b9
JG		 285};
286
cbd4623d 287static const char *hpd_names[6] = {
eed45b30
AD		 288 "HPD1",
289 "HPD2",
290 "HPD3",
291 "HPD4",
292 "HPD5",
293 "HPD6",
294};
295
771fe6b9
JG		 296static void radeon_print_display_setup(struct drm_device *dev)
297{
298 struct drm_connector *connector;
299 struct radeon_connector *radeon_connector;
300 struct drm_encoder *encoder;
301 struct radeon_encoder *radeon_encoder;
302 uint32_t devices;
303 int i = 0;
304
305 DRM_INFO("Radeon Display Connectors\n");
306 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
307 radeon_connector = to_radeon_connector(connector);
308 DRM_INFO("Connector %d:\n", i);
309 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
eed45b30
AD		 310 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
311 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
4b9d2a21 312 if (radeon_connector->ddc_bus) {
771fe6b9
JG		 313 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
314 radeon_connector->ddc_bus->rec.mask_clk_reg,
315 radeon_connector->ddc_bus->rec.mask_data_reg,
316 radeon_connector->ddc_bus->rec.a_clk_reg,
317 radeon_connector->ddc_bus->rec.a_data_reg,
9b9fe724
AD		 318 radeon_connector->ddc_bus->rec.en_clk_reg,
319 radeon_connector->ddc_bus->rec.en_data_reg,
320 radeon_connector->ddc_bus->rec.y_clk_reg,
321 radeon_connector->ddc_bus->rec.y_data_reg);
4b9d2a21
DA		 322 } else {
323 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
324 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
325 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
326 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
327 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
328 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
329 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
330 }
771fe6b9
JG		 331 DRM_INFO(" Encoders:\n");
332 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
333 radeon_encoder = to_radeon_encoder(encoder);
334 devices = radeon_encoder->devices & radeon_connector->devices;
335 if (devices) {
336 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
337 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
338 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
339 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
340 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
341 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
342 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
343 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
344 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
345 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
346 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
347 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
348 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
349 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
350 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
351 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
352 if (devices & ATOM_DEVICE_TV1_SUPPORT)
353 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
354 if (devices & ATOM_DEVICE_CV_SUPPORT)
355 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
356 }
357 }
358 i++;
359 }
360}
361
4ce001ab 362static bool radeon_setup_enc_conn(struct drm_device *dev)
771fe6b9
JG		 363{
364 struct radeon_device *rdev = dev->dev_private;
365 struct drm_connector *drm_connector;
366 bool ret = false;
367
368 if (rdev->bios) {
369 if (rdev->is_atom_bios) {
a084e6ee
AD		 370 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
371 if (ret == false)
771fe6b9 372 ret = radeon_get_atom_connector_info_from_object_table(dev);
b9597a1c 373 } else {
771fe6b9 374 ret = radeon_get_legacy_connector_info_from_bios(dev);
b9597a1c
AD		 375 if (ret == false)
376 ret = radeon_get_legacy_connector_info_from_table(dev);
377 }
771fe6b9
JG		 378 } else {
379 if (!ASIC_IS_AVIVO(rdev))
380 ret = radeon_get_legacy_connector_info_from_table(dev);
381 }
382 if (ret) {
1f3b6a45 383 radeon_setup_encoder_clones(dev);
771fe6b9
JG		 384 radeon_print_display_setup(dev);
385 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
386 radeon_ddc_dump(drm_connector);
387 }
388
389 return ret;
390}
391
392int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
393{
3c537889
AD		 394 struct drm_device *dev = radeon_connector->base.dev;
395 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 396 int ret = 0;
397
196c58d2
AD		 398 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
399 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
746c1aa4 400 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
7a15cbd4
DA		 401 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
402 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
9fa05c98 403 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
746c1aa4 404 }
771fe6b9
JG		 405 if (!radeon_connector->ddc_bus)
406 return -1;
4ce001ab 407 if (!radeon_connector->edid) {
0294cf4f 408 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
0294cf4f 409 }
3c537889
AD		 410 /* some servers provide a hardcoded edid in rom for KVMs */
411 if (!radeon_connector->edid)
412 radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev);
0294cf4f
AD		 413 if (radeon_connector->edid) {
414 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
415 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
771fe6b9
JG		 416 return ret;
417 }
418 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
42dea5dd 419 return 0;
771fe6b9
JG		 420}
421
422static int radeon_ddc_dump(struct drm_connector *connector)
423{
424 struct edid *edid;
425 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
426 int ret = 0;
427
428 if (!radeon_connector->ddc_bus)
429 return -1;
771fe6b9 430 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
771fe6b9
JG		 431 if (edid) {
432 kfree(edid);
433 }
434 return ret;
435}
436
437static inline uint32_t radeon_div(uint64_t n, uint32_t d)
438{
439 uint64_t mod;
440
441 n += d / 2;
442
443 mod = do_div(n, d);
444 return n;
445}
446
7c27f87d
AD		 447static void radeon_compute_pll_legacy(struct radeon_pll *pll,
448 uint64_t freq,
449 uint32_t *dot_clock_p,
450 uint32_t *fb_div_p,
451 uint32_t *frac_fb_div_p,
452 uint32_t *ref_div_p,
453 uint32_t *post_div_p)
771fe6b9
JG		 454{
455 uint32_t min_ref_div = pll->min_ref_div;
456 uint32_t max_ref_div = pll->max_ref_div;
fc10332b
AD		 457 uint32_t min_post_div = pll->min_post_div;
458 uint32_t max_post_div = pll->max_post_div;
771fe6b9
JG		 459 uint32_t min_fractional_feed_div = 0;
460 uint32_t max_fractional_feed_div = 0;
461 uint32_t best_vco = pll->best_vco;
462 uint32_t best_post_div = 1;
463 uint32_t best_ref_div = 1;
464 uint32_t best_feedback_div = 1;
465 uint32_t best_frac_feedback_div = 0;
466 uint32_t best_freq = -1;
467 uint32_t best_error = 0xffffffff;
468 uint32_t best_vco_diff = 1;
469 uint32_t post_div;
86cb2bbf 470 u32 pll_out_min, pll_out_max;
771fe6b9 471
d9fdaafb 472 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
771fe6b9
JG		 473 freq = freq * 1000;
474
86cb2bbf
AD		 475 if (pll->flags & RADEON_PLL_IS_LCD) {
476 pll_out_min = pll->lcd_pll_out_min;
477 pll_out_max = pll->lcd_pll_out_max;
478 } else {
479 pll_out_min = pll->pll_out_min;
480 pll_out_max = pll->pll_out_max;
481 }
482
fc10332b 483 if (pll->flags & RADEON_PLL_USE_REF_DIV)
771fe6b9
JG		 484 min_ref_div = max_ref_div = pll->reference_div;
485 else {
486 while (min_ref_div < max_ref_div-1) {
487 uint32_t mid = (min_ref_div + max_ref_div) / 2;
488 uint32_t pll_in = pll->reference_freq / mid;
489 if (pll_in < pll->pll_in_min)
490 max_ref_div = mid;
491 else if (pll_in > pll->pll_in_max)
492 min_ref_div = mid;
493 else
494 break;
495 }
496 }
497
fc10332b
AD		 498 if (pll->flags & RADEON_PLL_USE_POST_DIV)
499 min_post_div = max_post_div = pll->post_div;
500
501 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
771fe6b9
JG		 502 min_fractional_feed_div = pll->min_frac_feedback_div;
503 max_fractional_feed_div = pll->max_frac_feedback_div;
504 }
505
fc10332b 506 for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
771fe6b9
JG		 507 uint32_t ref_div;
508
fc10332b 509 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
771fe6b9
JG		 510 continue;
511
512 /* legacy radeons only have a few post_divs */
fc10332b 513 if (pll->flags & RADEON_PLL_LEGACY) {
771fe6b9
JG		 514 if ((post_div == 5) ||
515 (post_div == 7) ||
516 (post_div == 9) ||
517 (post_div == 10) ||
518 (post_div == 11) ||
519 (post_div == 13) ||
520 (post_div == 14) ||
521 (post_div == 15))
522 continue;
523 }
524
525 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
526 uint32_t feedback_div, current_freq = 0, error, vco_diff;
527 uint32_t pll_in = pll->reference_freq / ref_div;
528 uint32_t min_feed_div = pll->min_feedback_div;
529 uint32_t max_feed_div = pll->max_feedback_div + 1;
530
531 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
532 continue;
533
534 while (min_feed_div < max_feed_div) {
535 uint32_t vco;
536 uint32_t min_frac_feed_div = min_fractional_feed_div;
537 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
538 uint32_t frac_feedback_div;
539 uint64_t tmp;
540
541 feedback_div = (min_feed_div + max_feed_div) / 2;
542
543 tmp = (uint64_t)pll->reference_freq * feedback_div;
544 vco = radeon_div(tmp, ref_div);
545
86cb2bbf 546 if (vco < pll_out_min) {
771fe6b9
JG		 547 min_feed_div = feedback_div + 1;
548 continue;
86cb2bbf 549 } else if (vco > pll_out_max) {
771fe6b9
JG		 550 max_feed_div = feedback_div;
551 continue;
552 }
553
554 while (min_frac_feed_div < max_frac_feed_div) {
555 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
556 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
557 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
558 current_freq = radeon_div(tmp, ref_div * post_div);
559
fc10332b 560 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
167ffc44
DC		 561 if (freq < current_freq)
562 error = 0xffffffff;
563 else
564 error = freq - current_freq;
d0e275a9
AD		 565 } else
566 error = abs(current_freq - freq);
771fe6b9
JG		 567 vco_diff = abs(vco - best_vco);
568
569 if ((best_vco == 0 && error < best_error) ||
570 (best_vco != 0 &&
167ffc44 571 ((best_error > 100 && error < best_error - 100) ||
771fe6b9
JG		 572 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
573 best_post_div = post_div;
574 best_ref_div = ref_div;
575 best_feedback_div = feedback_div;
576 best_frac_feedback_div = frac_feedback_div;
577 best_freq = current_freq;
578 best_error = error;
579 best_vco_diff = vco_diff;
580 } else if (current_freq == freq) {
581 if (best_freq == -1) {
582 best_post_div = post_div;
583 best_ref_div = ref_div;
584 best_feedback_div = feedback_div;
585 best_frac_feedback_div = frac_feedback_div;
586 best_freq = current_freq;
587 best_error = error;
588 best_vco_diff = vco_diff;
fc10332b
AD		 589 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
590 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
591 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
592 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
593 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
594 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
771fe6b9
JG		 595 best_post_div = post_div;
596 best_ref_div = ref_div;
597 best_feedback_div = feedback_div;
598 best_frac_feedback_div = frac_feedback_div;
599 best_freq = current_freq;
600 best_error = error;
601 best_vco_diff = vco_diff;
602 }
603 }
604 if (current_freq < freq)
605 min_frac_feed_div = frac_feedback_div + 1;
606 else
607 max_frac_feed_div = frac_feedback_div;
608 }
609 if (current_freq < freq)
610 min_feed_div = feedback_div + 1;
611 else
612 max_feed_div = feedback_div;
613 }
614 }
615 }
616
617 *dot_clock_p = best_freq / 10000;
618 *fb_div_p = best_feedback_div;
619 *frac_fb_div_p = best_frac_feedback_div;
620 *ref_div_p = best_ref_div;
621 *post_div_p = best_post_div;
622}
623
383be5d1
AD		 624static bool
625calc_fb_div(struct radeon_pll *pll,
626 uint32_t freq,
627 uint32_t post_div,
628 uint32_t ref_div,
629 uint32_t *fb_div,
630 uint32_t *fb_div_frac)
b27b6375 631{
383be5d1
AD		 632 fixed20_12 feedback_divider, a, b;
633 u32 vco_freq;
b27b6375 634
383be5d1
AD		 635 vco_freq = freq * post_div;
636 /* feedback_divider = vco_freq * ref_div / pll->reference_freq; */
68adac5e
BS		 637 a.full = dfixed_const(pll->reference_freq);
638 feedback_divider.full = dfixed_const(vco_freq);
639 feedback_divider.full = dfixed_div(feedback_divider, a);
640 a.full = dfixed_const(ref_div);
641 feedback_divider.full = dfixed_mul(feedback_divider, a);
b27b6375 642
383be5d1
AD		 643 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
644 /* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */
68adac5e
BS		 645 a.full = dfixed_const(10);
646 feedback_divider.full = dfixed_mul(feedback_divider, a);
647 feedback_divider.full += dfixed_const_half(0);
648 feedback_divider.full = dfixed_floor(feedback_divider);
649 feedback_divider.full = dfixed_div(feedback_divider, a);
383be5d1
AD		 650
651 /* *fb_div = floor(feedback_divider); */
68adac5e
BS		 652 a.full = dfixed_floor(feedback_divider);
653 *fb_div = dfixed_trunc(a);
383be5d1 654 /* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */
68adac5e
BS		 655 a.full = dfixed_const(10);
656 b.full = dfixed_mul(feedback_divider, a);
383be5d1 657
68adac5e
BS		 658 feedback_divider.full = dfixed_floor(feedback_divider);
659 feedback_divider.full = dfixed_mul(feedback_divider, a);
383be5d1 660 feedback_divider.full = b.full - feedback_divider.full;
68adac5e 661 *fb_div_frac = dfixed_trunc(feedback_divider);
383be5d1
AD		 662 } else {
663 /* *fb_div = floor(feedback_divider + 0.5); */
68adac5e
BS		 664 feedback_divider.full += dfixed_const_half(0);
665 feedback_divider.full = dfixed_floor(feedback_divider);
b27b6375 666
68adac5e 667 *fb_div = dfixed_trunc(feedback_divider);
383be5d1
AD		 668 *fb_div_frac = 0;
669 }
b27b6375 670
383be5d1
AD		 671 if (((*fb_div) < pll->min_feedback_div) || ((*fb_div) > pll->max_feedback_div))
672 return false;
673 else
674 return true;
675}
b27b6375 676
383be5d1
AD		 677static bool
678calc_fb_ref_div(struct radeon_pll *pll,
679 uint32_t freq,
680 uint32_t post_div,
681 uint32_t *fb_div,
682 uint32_t *fb_div_frac,
683 uint32_t *ref_div)
684{
685 fixed20_12 ffreq, max_error, error, pll_out, a;
686 u32 vco;
86cb2bbf
AD		 687 u32 pll_out_min, pll_out_max;
688
689 if (pll->flags & RADEON_PLL_IS_LCD) {
690 pll_out_min = pll->lcd_pll_out_min;
691 pll_out_max = pll->lcd_pll_out_max;
692 } else {
693 pll_out_min = pll->pll_out_min;
694 pll_out_max = pll->pll_out_max;
695 }
b27b6375 696
68adac5e 697 ffreq.full = dfixed_const(freq);
383be5d1 698 /* max_error = ffreq * 0.0025; */
68adac5e
BS		 699 a.full = dfixed_const(400);
700 max_error.full = dfixed_div(ffreq, a);
b27b6375 701
383be5d1
AD		 702 for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) {
703 if (calc_fb_div(pll, freq, post_div, (*ref_div), fb_div, fb_div_frac)) {
704 vco = pll->reference_freq * (((*fb_div) * 10) + (*fb_div_frac));
705 vco = vco / ((*ref_div) * 10);
b27b6375 706
86cb2bbf 707 if ((vco < pll_out_min) || (vco > pll_out_max))
383be5d1 708 continue;
b27b6375 709
383be5d1 710 /* pll_out = vco / post_div; */
68adac5e
BS		 711 a.full = dfixed_const(post_div);
712 pll_out.full = dfixed_const(vco);
713 pll_out.full = dfixed_div(pll_out, a);
b27b6375 714
383be5d1
AD		 715 if (pll_out.full >= ffreq.full) {
716 error.full = pll_out.full - ffreq.full;
717 if (error.full <= max_error.full)
718 return true;
719 }
720 }
721 }
722 return false;
723}
b27b6375 724
383be5d1
AD		 725static void radeon_compute_pll_new(struct radeon_pll *pll,
726 uint64_t freq,
727 uint32_t *dot_clock_p,
728 uint32_t *fb_div_p,
729 uint32_t *frac_fb_div_p,
730 uint32_t *ref_div_p,
731 uint32_t *post_div_p)
732{
733 u32 fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0;
734 u32 best_freq = 0, vco_frequency;
86cb2bbf
AD		 735 u32 pll_out_min, pll_out_max;
736
737 if (pll->flags & RADEON_PLL_IS_LCD) {
738 pll_out_min = pll->lcd_pll_out_min;
739 pll_out_max = pll->lcd_pll_out_max;
740 } else {
741 pll_out_min = pll->pll_out_min;
742 pll_out_max = pll->pll_out_max;
743 }
b27b6375 744
383be5d1
AD		 745 /* freq = freq / 10; */
746 do_div(freq, 10);
b27b6375 747
383be5d1
AD		 748 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
749 post_div = pll->post_div;
750 if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div))
751 goto done;
752
753 vco_frequency = freq * post_div;
86cb2bbf 754 if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
383be5d1
AD		 755 goto done;
756
757 if (pll->flags & RADEON_PLL_USE_REF_DIV) {
758 ref_div = pll->reference_div;
759 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
760 goto done;
761 if (!calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
762 goto done;
763 }
764 } else {
765 for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) {
766 if (pll->flags & RADEON_PLL_LEGACY) {
767 if ((post_div == 5) ||
768 (post_div == 7) ||
769 (post_div == 9) ||
770 (post_div == 10) ||
771 (post_div == 11))
772 continue;
773 }
774
775 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
776 continue;
777
778 vco_frequency = freq * post_div;
86cb2bbf 779 if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
383be5d1
AD		 780 continue;
781 if (pll->flags & RADEON_PLL_USE_REF_DIV) {
782 ref_div = pll->reference_div;
783 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
784 goto done;
785 if (calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
786 break;
787 } else {
788 if (calc_fb_ref_div(pll, freq, post_div, &fb_div, &fb_div_frac, &ref_div))
789 break;
790 }
b27b6375
AD		 791 }
792 }
793
383be5d1
AD		 794 best_freq = pll->reference_freq * 10 * fb_div;
795 best_freq += pll->reference_freq * fb_div_frac;
796 best_freq = best_freq / (ref_div * post_div);
b27b6375 797
383be5d1
AD		 798done:
799 if (best_freq == 0)
800 DRM_ERROR("Couldn't find valid PLL dividers\n");
b27b6375 801
383be5d1
AD		 802 *dot_clock_p = best_freq / 10;
803 *fb_div_p = fb_div;
804 *frac_fb_div_p = fb_div_frac;
805 *ref_div_p = ref_div;
806 *post_div_p = post_div;
b27b6375 807
d9fdaafb 808 DRM_DEBUG_KMS("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
b27b6375
AD		 809}
810
7c27f87d
AD		 811void radeon_compute_pll(struct radeon_pll *pll,
812 uint64_t freq,
813 uint32_t *dot_clock_p,
814 uint32_t *fb_div_p,
815 uint32_t *frac_fb_div_p,
816 uint32_t *ref_div_p,
817 uint32_t *post_div_p)
818{
819 switch (pll->algo) {
383be5d1
AD		 820 case PLL_ALGO_NEW:
821 radeon_compute_pll_new(pll, freq, dot_clock_p, fb_div_p,
822 frac_fb_div_p, ref_div_p, post_div_p);
7c27f87d
AD		 823 break;
824 case PLL_ALGO_LEGACY:
825 default:
826 radeon_compute_pll_legacy(pll, freq, dot_clock_p, fb_div_p,
827 frac_fb_div_p, ref_div_p, post_div_p);
828 break;
829 }
b27b6375
AD		 830}
831
771fe6b9
JG		 832static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
833{
834 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
771fe6b9 835
bc9025bd
LB		 836 if (radeon_fb->obj)
837 drm_gem_object_unreference_unlocked(radeon_fb->obj);
771fe6b9
JG		 838 drm_framebuffer_cleanup(fb);
839 kfree(radeon_fb);
840}
841
842static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
843 struct drm_file *file_priv,
844 unsigned int *handle)
845{
846 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
847
848 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
849}
850
851static const struct drm_framebuffer_funcs radeon_fb_funcs = {
852 .destroy = radeon_user_framebuffer_destroy,
853 .create_handle = radeon_user_framebuffer_create_handle,
854};
855
38651674
DA		 856void
857radeon_framebuffer_init(struct drm_device *dev,
858 struct radeon_framebuffer *rfb,
859 struct drm_mode_fb_cmd *mode_cmd,
860 struct drm_gem_object *obj)
771fe6b9 861{
38651674
DA		 862 rfb->obj = obj;
863 drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
864 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
771fe6b9
JG		 865}
866
867static struct drm_framebuffer *
868radeon_user_framebuffer_create(struct drm_device *dev,
869 struct drm_file *file_priv,
870 struct drm_mode_fb_cmd *mode_cmd)
871{
872 struct drm_gem_object *obj;
38651674 873 struct radeon_framebuffer *radeon_fb;
771fe6b9
JG		 874
875 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
7e71c9e2
JG		 876 if (obj == NULL) {
877 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
878 "can't create framebuffer\n", mode_cmd->handle);
879 return NULL;
880 }
38651674
DA		 881
882 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
883 if (radeon_fb == NULL) {
884 return NULL;
885 }
886
887 radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
888
889 return &radeon_fb->base;
771fe6b9
JG		 890}
891
eb1f8e4f
DA		 892static void radeon_output_poll_changed(struct drm_device *dev)
893{
894 struct radeon_device *rdev = dev->dev_private;
895 radeon_fb_output_poll_changed(rdev);
896}
897
771fe6b9
JG		 898static const struct drm_mode_config_funcs radeon_mode_funcs = {
899 .fb_create = radeon_user_framebuffer_create,
eb1f8e4f 900 .output_poll_changed = radeon_output_poll_changed
771fe6b9
JG		 901};
902
445282db
DA		 903struct drm_prop_enum_list {
904 int type;
905 char *name;
906};
907
908static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
909{ { 0, "driver" },
910 { 1, "bios" },
911};
912
913static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
914{ { TV_STD_NTSC, "ntsc" },
915 { TV_STD_PAL, "pal" },
916 { TV_STD_PAL_M, "pal-m" },
917 { TV_STD_PAL_60, "pal-60" },
918 { TV_STD_NTSC_J, "ntsc-j" },
919 { TV_STD_SCART_PAL, "scart-pal" },
920 { TV_STD_PAL_CN, "pal-cn" },
921 { TV_STD_SECAM, "secam" },
922};
923
5b1714d3
AD		 924static struct drm_prop_enum_list radeon_underscan_enum_list[] =
925{ { UNDERSCAN_OFF, "off" },
926 { UNDERSCAN_ON, "on" },
927 { UNDERSCAN_AUTO, "auto" },
928};
929
d79766fa 930static int radeon_modeset_create_props(struct radeon_device *rdev)
445282db
DA		 931{
932 int i, sz;
933
934 if (rdev->is_atom_bios) {
935 rdev->mode_info.coherent_mode_property =
936 drm_property_create(rdev->ddev,
937 DRM_MODE_PROP_RANGE,
938 "coherent", 2);
939 if (!rdev->mode_info.coherent_mode_property)
940 return -ENOMEM;
941
942 rdev->mode_info.coherent_mode_property->values[0] = 0;
390d0bbe 943 rdev->mode_info.coherent_mode_property->values[1] = 1;
445282db
DA		 944 }
945
946 if (!ASIC_IS_AVIVO(rdev)) {
947 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
948 rdev->mode_info.tmds_pll_property =
949 drm_property_create(rdev->ddev,
950 DRM_MODE_PROP_ENUM,
951 "tmds_pll", sz);
952 for (i = 0; i < sz; i++) {
953 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
954 i,
955 radeon_tmds_pll_enum_list[i].type,
956 radeon_tmds_pll_enum_list[i].name);
957 }
958 }
959
960 rdev->mode_info.load_detect_property =
961 drm_property_create(rdev->ddev,
962 DRM_MODE_PROP_RANGE,
963 "load detection", 2);
964 if (!rdev->mode_info.load_detect_property)
965 return -ENOMEM;
966 rdev->mode_info.load_detect_property->values[0] = 0;
390d0bbe 967 rdev->mode_info.load_detect_property->values[1] = 1;
445282db
DA		 968
969 drm_mode_create_scaling_mode_property(rdev->ddev);
970
971 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
972 rdev->mode_info.tv_std_property =
973 drm_property_create(rdev->ddev,
974 DRM_MODE_PROP_ENUM,
975 "tv standard", sz);
976 for (i = 0; i < sz; i++) {
977 drm_property_add_enum(rdev->mode_info.tv_std_property,
978 i,
979 radeon_tv_std_enum_list[i].type,
980 radeon_tv_std_enum_list[i].name);
981 }
982
5b1714d3
AD		 983 sz = ARRAY_SIZE(radeon_underscan_enum_list);
984 rdev->mode_info.underscan_property =
985 drm_property_create(rdev->ddev,
986 DRM_MODE_PROP_ENUM,
987 "underscan", sz);
988 for (i = 0; i < sz; i++) {
989 drm_property_add_enum(rdev->mode_info.underscan_property,
990 i,
991 radeon_underscan_enum_list[i].type,
992 radeon_underscan_enum_list[i].name);
993 }
994
445282db
DA		 995 return 0;
996}
997
f46c0120
AD		 998void radeon_update_display_priority(struct radeon_device *rdev)
999{
1000 /* adjustment options for the display watermarks */
1001 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1002 /* set display priority to high for r3xx, rv515 chips
1003 * this avoids flickering due to underflow to the
1004 * display controllers during heavy acceleration.
45737447
AD		 1005 * Don't force high on rs4xx igp chips as it seems to
1006 * affect the sound card. See kernel bug 15982.
f46c0120 1007 */
45737447
AD		 1008 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1009 !(rdev->flags & RADEON_IS_IGP))
f46c0120
AD		 1010 rdev->disp_priority = 2;
1011 else
1012 rdev->disp_priority = 0;
1013 } else
1014 rdev->disp_priority = radeon_disp_priority;
1015
1016}
1017
771fe6b9
JG		 1018int radeon_modeset_init(struct radeon_device *rdev)
1019{
18917b60 1020 int i;
771fe6b9
JG		 1021 int ret;
1022
1023 drm_mode_config_init(rdev->ddev);
1024 rdev->mode_info.mode_config_initialized = true;
1025
1026 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1027
1028 if (ASIC_IS_AVIVO(rdev)) {
1029 rdev->ddev->mode_config.max_width = 8192;
1030 rdev->ddev->mode_config.max_height = 8192;
1031 } else {
1032 rdev->ddev->mode_config.max_width = 4096;
1033 rdev->ddev->mode_config.max_height = 4096;
1034 }
1035
1036 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1037
445282db
DA		 1038 ret = radeon_modeset_create_props(rdev);
1039 if (ret) {
1040 return ret;
1041 }
dfee5614 1042
3c537889
AD		 1043 /* check combios for a valid hardcoded EDID - Sun servers */
1044 if (!rdev->is_atom_bios) {
1045 /* check for hardcoded EDID in BIOS */
1046 radeon_combios_check_hardcoded_edid(rdev);
1047 }
1048
dfee5614 1049 /* allocate crtcs */
18917b60 1050 for (i = 0; i < rdev->num_crtc; i++) {
771fe6b9
JG		 1051 radeon_crtc_init(rdev->ddev, i);
1052 }
1053
1054 /* okay we should have all the bios connectors */
1055 ret = radeon_setup_enc_conn(rdev->ddev);
1056 if (!ret) {
1057 return ret;
1058 }
d4877cf2
AD		 1059 /* initialize hpd */
1060 radeon_hpd_init(rdev);
38651674 1061
ce8f5370
AD		 1062 /* Initialize power management */
1063 radeon_pm_init(rdev);
1064
38651674 1065 radeon_fbdev_init(rdev);
eb1f8e4f
DA		 1066 drm_kms_helper_poll_init(rdev->ddev);
1067
771fe6b9
JG		 1068 return 0;
1069}
1070
1071void radeon_modeset_fini(struct radeon_device *rdev)
1072{
38651674 1073 radeon_fbdev_fini(rdev);
3c537889 1074 kfree(rdev->mode_info.bios_hardcoded_edid);
ce8f5370 1075 radeon_pm_fini(rdev);
3c537889 1076
771fe6b9 1077 if (rdev->mode_info.mode_config_initialized) {
eb1f8e4f 1078 drm_kms_helper_poll_fini(rdev->ddev);
d4877cf2 1079 radeon_hpd_fini(rdev);
771fe6b9
JG		 1080 drm_mode_config_cleanup(rdev->ddev);
1081 rdev->mode_info.mode_config_initialized = false;
1082 }
1083}
1084
c93bb85b
JG		 1085bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1086 struct drm_display_mode *mode,
1087 struct drm_display_mode *adjusted_mode)
771fe6b9 1088{
c93bb85b 1089 struct drm_device *dev = crtc->dev;
5b1714d3 1090 struct radeon_device *rdev = dev->dev_private;
c93bb85b
JG		 1091 struct drm_encoder *encoder;
1092 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1093 struct radeon_encoder *radeon_encoder;
5b1714d3
AD		 1094 struct drm_connector *connector;
1095 struct radeon_connector *radeon_connector;
c93bb85b 1096 bool first = true;
d65d65b1
AD		 1097 u32 src_v = 1, dst_v = 1;
1098 u32 src_h = 1, dst_h = 1;
771fe6b9 1099
5b1714d3
AD		 1100 radeon_crtc->h_border = 0;
1101 radeon_crtc->v_border = 0;
1102
c93bb85b 1103 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
c93bb85b
JG		 1104 if (encoder->crtc != crtc)
1105 continue;
d65d65b1 1106 radeon_encoder = to_radeon_encoder(encoder);
5b1714d3
AD		 1107 connector = radeon_get_connector_for_encoder(encoder);
1108 radeon_connector = to_radeon_connector(connector);
1109
c93bb85b 1110 if (first) {
80297e87
AD		 1111 /* set scaling */
1112 if (radeon_encoder->rmx_type == RMX_OFF)
1113 radeon_crtc->rmx_type = RMX_OFF;
1114 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1115 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1116 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1117 else
1118 radeon_crtc->rmx_type = RMX_OFF;
d65d65b1
AD		 1119 src_v = crtc->mode.vdisplay;
1120 dst_v = radeon_crtc->native_mode.vdisplay;
1121 src_h = crtc->mode.hdisplay;
1122 dst_h = radeon_crtc->native_mode.vdisplay;
80297e87 1123 /* copy native mode */
c93bb85b 1124 memcpy(&radeon_crtc->native_mode,
80297e87 1125 &radeon_encoder->native_mode,
de2103e4 1126 sizeof(struct drm_display_mode));
5b1714d3
AD		 1127
1128 /* fix up for overscan on hdmi */
1129 if (ASIC_IS_AVIVO(rdev) &&
1130 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1131 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1132 drm_detect_hdmi_monitor(radeon_connector->edid)))) {
1133 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1134 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1135 radeon_crtc->rmx_type = RMX_FULL;
1136 src_v = crtc->mode.vdisplay;
1137 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1138 src_h = crtc->mode.hdisplay;
1139 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1140 }
c93bb85b
JG		 1141 first = false;
1142 } else {
1143 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1144 /* WARNING: Right now this can't happen but
1145 * in the future we need to check that scaling
d65d65b1 1146 * are consistent across different encoder
c93bb85b
JG		 1147 * (ie all encoder can work with the same
1148 * scaling).
1149 */
d65d65b1 1150 DRM_ERROR("Scaling not consistent across encoder.\n");
c93bb85b
JG		 1151 return false;
1152 }
771fe6b9
JG		 1153 }
1154 }
c93bb85b
JG		 1155 if (radeon_crtc->rmx_type != RMX_OFF) {
1156 fixed20_12 a, b;
d65d65b1
AD		 1157 a.full = dfixed_const(src_v);
1158 b.full = dfixed_const(dst_v);
68adac5e 1159 radeon_crtc->vsc.full = dfixed_div(a, b);
d65d65b1
AD		 1160 a.full = dfixed_const(src_h);
1161 b.full = dfixed_const(dst_h);
68adac5e 1162 radeon_crtc->hsc.full = dfixed_div(a, b);
771fe6b9 1163 } else {
68adac5e
BS		 1164 radeon_crtc->vsc.full = dfixed_const(1);
1165 radeon_crtc->hsc.full = dfixed_const(1);
771fe6b9 1166 }
c93bb85b 1167 return true;
771fe6b9 1168}
Linux kernel - Deliverables
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