projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon/kms/pm: move pm state update to crtc functions
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_encoders.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "drm_crtc_helper.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32extern int atom_debug;
33
5a9bcacc
AD		 34/* evil but including atombios.h is much worse */
35bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
1f3b6a45
DA		 38static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
39{
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
45 int count;
46
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
49 return index_mask;
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
52 return index_mask;
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
55 return index_mask;
bcc1c2a1 56
1f3b6a45
DA		 57 count = -1;
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
60 count++;
61
62 if (clone_encoder == encoder)
63 continue;
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
65 continue;
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
67 continue;
68 else
69 index_mask |= (1 << count);
70 }
71 return index_mask;
72}
73
74void radeon_setup_encoder_clones(struct drm_device *dev)
75{
76 struct drm_encoder *encoder;
77
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
80 }
81}
82
771fe6b9
JG		 83uint32_t
84radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
85{
86 struct radeon_device *rdev = dev->dev_private;
87 uint32_t ret = 0;
88
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
95 switch (dac) {
96 case 1: /* dac a */
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
103 else
104 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
105 break;
106 case 2: /* dac b */
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
109 else {
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
112 else*/
113 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
114 }
115 break;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
119 else
120 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
121 break;
122 }
123 break;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
127 else
128 ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
129 break;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
137 else
138 ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
139 break;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
148 else
149 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
150 break;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
153 break;
154 }
155
156 return ret;
157}
158
f28cf339
DA		 159static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
160{
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
174 return true;
175 default:
176 return false;
177 }
178}
771fe6b9
JG		 179void
180radeon_link_encoder_connector(struct drm_device *dev)
181{
182 struct drm_connector *connector;
183 struct radeon_connector *radeon_connector;
184 struct drm_encoder *encoder;
185 struct radeon_encoder *radeon_encoder;
186
187 /* walk the list and link encoders to connectors */
188 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
189 radeon_connector = to_radeon_connector(connector);
190 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
191 radeon_encoder = to_radeon_encoder(encoder);
192 if (radeon_encoder->devices & radeon_connector->devices)
193 drm_mode_connector_attach_encoder(connector, encoder);
194 }
195 }
196}
197
4ce001ab
DA		 198void radeon_encoder_set_active_device(struct drm_encoder *encoder)
199{
200 struct drm_device *dev = encoder->dev;
201 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
202 struct drm_connector *connector;
203
204 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
205 if (connector->encoder == encoder) {
206 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
207 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
f641e51e
DA		 208 DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
209 radeon_encoder->active_device, radeon_encoder->devices,
210 radeon_connector->devices, encoder->encoder_type);
4ce001ab
DA		 211 }
212 }
213}
214
771fe6b9
JG		 215static struct drm_connector *
216radeon_get_connector_for_encoder(struct drm_encoder *encoder)
217{
218 struct drm_device *dev = encoder->dev;
219 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
220 struct drm_connector *connector;
221 struct radeon_connector *radeon_connector;
222
223 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
224 radeon_connector = to_radeon_connector(connector);
43c33ed8 225 if (radeon_encoder->active_device & radeon_connector->devices)
771fe6b9
JG		 226 return connector;
227 }
228 return NULL;
229}
230
9ae47867
AD		 231static struct radeon_connector_atom_dig *
232radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
233{
234 struct drm_device *dev = encoder->dev;
235 struct radeon_device *rdev = dev->dev_private;
236 struct drm_connector *connector;
237 struct radeon_connector *radeon_connector;
238 struct radeon_connector_atom_dig *dig_connector;
239
240 if (!rdev->is_atom_bios)
241 return NULL;
242
243 connector = radeon_get_connector_for_encoder(encoder);
244 if (!connector)
245 return NULL;
246
247 radeon_connector = to_radeon_connector(connector);
248
249 if (!radeon_connector->con_priv)
250 return NULL;
251
252 dig_connector = radeon_connector->con_priv;
253
254 return dig_connector;
255}
256
771fe6b9
JG		 257static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
258 struct drm_display_mode *mode,
259 struct drm_display_mode *adjusted_mode)
260{
771fe6b9 261 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
5a9bcacc
AD		 262 struct drm_device *dev = encoder->dev;
263 struct radeon_device *rdev = dev->dev_private;
771fe6b9 264
8c2a6d73
AD		 265 /* set the active encoder to connector routing */
266 radeon_encoder_set_active_device(encoder);
771fe6b9
JG		 267 drm_mode_set_crtcinfo(adjusted_mode, 0);
268
771fe6b9
JG		 269 /* hw bug */
270 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
271 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
272 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
273
80297e87
AD		 274 /* get the native mode for LVDS */
275 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
276 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
277 int mode_id = adjusted_mode->base.id;
278 *adjusted_mode = *native_mode;
279 if (!ASIC_IS_AVIVO(rdev)) {
280 adjusted_mode->hdisplay = mode->hdisplay;
281 adjusted_mode->vdisplay = mode->vdisplay;
310a82c8
AD		 282 adjusted_mode->crtc_hdisplay = mode->hdisplay;
283 adjusted_mode->crtc_vdisplay = mode->vdisplay;
80297e87
AD		 284 }
285 adjusted_mode->base.id = mode_id;
286 }
287
288 /* get the native mode for TV */
ceefedd8 289 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
5a9bcacc
AD		 290 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
291 if (tv_dac) {
292 if (tv_dac->tv_std == TV_STD_NTSC ||
293 tv_dac->tv_std == TV_STD_NTSC_J ||
294 tv_dac->tv_std == TV_STD_PAL_M)
295 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
296 else
297 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
298 }
299 }
300
5801ead6 301 if (ASIC_IS_DCE3(rdev) &&
9f998ad7 302 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
5801ead6
AD		 303 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
304 radeon_dp_set_link_config(connector, mode);
305 }
306
771fe6b9
JG		 307 return true;
308}
309
310static void
311atombios_dac_setup(struct drm_encoder *encoder, int action)
312{
313 struct drm_device *dev = encoder->dev;
314 struct radeon_device *rdev = dev->dev_private;
315 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
316 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
affd8589 317 int index = 0;
445282db 318 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
445282db 319
771fe6b9
JG		 320 memset(&args, 0, sizeof(args));
321
322 switch (radeon_encoder->encoder_id) {
323 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
324 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
325 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
771fe6b9
JG		 326 break;
327 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
328 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
329 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
771fe6b9
JG		 330 break;
331 }
332
333 args.ucAction = action;
334
4ce001ab 335 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
771fe6b9 336 args.ucDacStandard = ATOM_DAC1_PS2;
4ce001ab 337 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 338 args.ucDacStandard = ATOM_DAC1_CV;
339 else {
affd8589 340 switch (dac_info->tv_std) {
771fe6b9
JG		 341 case TV_STD_PAL:
342 case TV_STD_PAL_M:
343 case TV_STD_SCART_PAL:
344 case TV_STD_SECAM:
345 case TV_STD_PAL_CN:
346 args.ucDacStandard = ATOM_DAC1_PAL;
347 break;
348 case TV_STD_NTSC:
349 case TV_STD_NTSC_J:
350 case TV_STD_PAL_60:
351 default:
352 args.ucDacStandard = ATOM_DAC1_NTSC;
353 break;
354 }
355 }
356 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
357
358 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
359
360}
361
362static void
363atombios_tv_setup(struct drm_encoder *encoder, int action)
364{
365 struct drm_device *dev = encoder->dev;
366 struct radeon_device *rdev = dev->dev_private;
367 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
368 TV_ENCODER_CONTROL_PS_ALLOCATION args;
369 int index = 0;
445282db 370 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
445282db 371
771fe6b9
JG		 372 memset(&args, 0, sizeof(args));
373
374 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
375
376 args.sTVEncoder.ucAction = action;
377
4ce001ab 378 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 379 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
380 else {
affd8589 381 switch (dac_info->tv_std) {
771fe6b9
JG		 382 case TV_STD_NTSC:
383 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
384 break;
385 case TV_STD_PAL:
386 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
387 break;
388 case TV_STD_PAL_M:
389 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
390 break;
391 case TV_STD_PAL_60:
392 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
393 break;
394 case TV_STD_NTSC_J:
395 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
396 break;
397 case TV_STD_SCART_PAL:
398 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
399 break;
400 case TV_STD_SECAM:
401 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
402 break;
403 case TV_STD_PAL_CN:
404 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
405 break;
406 default:
407 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
408 break;
409 }
410 }
411
412 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
413
414 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
415
416}
417
418void
419atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
420{
421 struct drm_device *dev = encoder->dev;
422 struct radeon_device *rdev = dev->dev_private;
423 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
424 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
425 int index = 0;
426
427 memset(&args, 0, sizeof(args));
428
429 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
430
431 args.sXTmdsEncoder.ucEnable = action;
432
433 if (radeon_encoder->pixel_clock > 165000)
434 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
435
436 /*if (pScrn->rgbBits == 8)*/
437 args.sXTmdsEncoder.ucMisc |= (1 << 1);
438
439 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
440
441}
442
443static void
444atombios_ddia_setup(struct drm_encoder *encoder, int action)
445{
446 struct drm_device *dev = encoder->dev;
447 struct radeon_device *rdev = dev->dev_private;
448 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
449 DVO_ENCODER_CONTROL_PS_ALLOCATION args;
450 int index = 0;
451
452 memset(&args, 0, sizeof(args));
453
454 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
455
456 args.sDVOEncoder.ucAction = action;
457 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
458
459 if (radeon_encoder->pixel_clock > 165000)
460 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
461
462 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
463
464}
465
466union lvds_encoder_control {
467 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
468 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
469};
470
32f48ffe 471void
771fe6b9
JG		 472atombios_digital_setup(struct drm_encoder *encoder, int action)
473{
474 struct drm_device *dev = encoder->dev;
475 struct radeon_device *rdev = dev->dev_private;
476 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
9ae47867
AD		 477 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
478 struct radeon_connector_atom_dig *dig_connector =
479 radeon_get_atom_connector_priv_from_encoder(encoder);
771fe6b9
JG		 480 union lvds_encoder_control args;
481 int index = 0;
dafc3bd5 482 int hdmi_detected = 0;
771fe6b9 483 uint8_t frev, crev;
771fe6b9 484
9ae47867 485 if (!dig || !dig_connector)
771fe6b9
JG		 486 return;
487
9ae47867 488 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
dafc3bd5
CK		 489 hdmi_detected = 1;
490
771fe6b9
JG		 491 memset(&args, 0, sizeof(args));
492
493 switch (radeon_encoder->encoder_id) {
494 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
495 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
496 break;
497 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
498 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
499 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
500 break;
501 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
502 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
503 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
504 else
505 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
506 break;
507 }
508
a084e6ee
AD		 509 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
510 return;
771fe6b9
JG		 511
512 switch (frev) {
513 case 1:
514 case 2:
515 switch (crev) {
516 case 1:
517 args.v1.ucMisc = 0;
518 args.v1.ucAction = action;
dafc3bd5 519 if (hdmi_detected)
771fe6b9
JG		 520 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
521 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
522 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
edc664e3 523 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
771fe6b9 524 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
edc664e3 525 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
771fe6b9
JG		 526 args.v1.ucMisc |= (1 << 1);
527 } else {
528 if (dig_connector->linkb)
529 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
530 if (radeon_encoder->pixel_clock > 165000)
531 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
532 /*if (pScrn->rgbBits == 8) */
533 args.v1.ucMisc |= (1 << 1);
534 }
535 break;
536 case 2:
537 case 3:
538 args.v2.ucMisc = 0;
539 args.v2.ucAction = action;
540 if (crev == 3) {
541 if (dig->coherent_mode)
542 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
543 }
dafc3bd5 544 if (hdmi_detected)
771fe6b9
JG		 545 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
546 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
547 args.v2.ucTruncate = 0;
548 args.v2.ucSpatial = 0;
549 args.v2.ucTemporal = 0;
550 args.v2.ucFRC = 0;
551 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
edc664e3 552 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
771fe6b9 553 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
edc664e3 554 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
771fe6b9 555 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
edc664e3 556 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
771fe6b9
JG		 557 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
558 }
edc664e3 559 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
771fe6b9 560 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
edc664e3 561 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
771fe6b9 562 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
edc664e3 563 if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
771fe6b9
JG		 564 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
565 }
566 } else {
567 if (dig_connector->linkb)
568 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
569 if (radeon_encoder->pixel_clock > 165000)
570 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
571 }
572 break;
573 default:
574 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
575 break;
576 }
577 break;
578 default:
579 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
580 break;
581 }
582
583 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 584}
585
586int
587atombios_get_encoder_mode(struct drm_encoder *encoder)
588{
589 struct drm_connector *connector;
590 struct radeon_connector *radeon_connector;
9ae47867 591 struct radeon_connector_atom_dig *dig_connector;
771fe6b9
JG		 592
593 connector = radeon_get_connector_for_encoder(encoder);
594 if (!connector)
595 return 0;
596
597 radeon_connector = to_radeon_connector(connector);
598
599 switch (connector->connector_type) {
600 case DRM_MODE_CONNECTOR_DVII:
705af9c7 601 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
0294cf4f 602 if (drm_detect_hdmi_monitor(radeon_connector->edid))
771fe6b9
JG		 603 return ATOM_ENCODER_MODE_HDMI;
604 else if (radeon_connector->use_digital)
605 return ATOM_ENCODER_MODE_DVI;
606 else
607 return ATOM_ENCODER_MODE_CRT;
608 break;
609 case DRM_MODE_CONNECTOR_DVID:
610 case DRM_MODE_CONNECTOR_HDMIA:
771fe6b9 611 default:
0294cf4f 612 if (drm_detect_hdmi_monitor(radeon_connector->edid))
771fe6b9
JG		 613 return ATOM_ENCODER_MODE_HDMI;
614 else
615 return ATOM_ENCODER_MODE_DVI;
616 break;
617 case DRM_MODE_CONNECTOR_LVDS:
618 return ATOM_ENCODER_MODE_LVDS;
619 break;
620 case DRM_MODE_CONNECTOR_DisplayPort:
196c58d2 621 case DRM_MODE_CONNECTOR_eDP:
9ae47867
AD		 622 dig_connector = radeon_connector->con_priv;
623 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
624 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
f92a8b67
AD		 625 return ATOM_ENCODER_MODE_DP;
626 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
771fe6b9
JG		 627 return ATOM_ENCODER_MODE_HDMI;
628 else
629 return ATOM_ENCODER_MODE_DVI;
630 break;
a5899fcc
AD		 631 case DRM_MODE_CONNECTOR_DVIA:
632 case DRM_MODE_CONNECTOR_VGA:
771fe6b9
JG		 633 return ATOM_ENCODER_MODE_CRT;
634 break;
a5899fcc
AD		 635 case DRM_MODE_CONNECTOR_Composite:
636 case DRM_MODE_CONNECTOR_SVIDEO:
637 case DRM_MODE_CONNECTOR_9PinDIN:
771fe6b9
JG		 638 /* fix me */
639 return ATOM_ENCODER_MODE_TV;
640 /*return ATOM_ENCODER_MODE_CV;*/
641 break;
642 }
643}
644
1a66c95a
AD		 645/*
646 * DIG Encoder/Transmitter Setup
647 *
648 * DCE 3.0/3.1
649 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
650 * Supports up to 3 digital outputs
651 * - 2 DIG encoder blocks.
652 * DIG1 can drive UNIPHY link A or link B
653 * DIG2 can drive UNIPHY link B or LVTMA
654 *
655 * DCE 3.2
656 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
657 * Supports up to 5 digital outputs
658 * - 2 DIG encoder blocks.
659 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
660 *
bcc1c2a1
AD		 661 * DCE 4.0
662 * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
663 * Supports up to 6 digital outputs
664 * - 6 DIG encoder blocks.
665 * - DIG to PHY mapping is hardcoded
666 * DIG1 drives UNIPHY0 link A, A+B
667 * DIG2 drives UNIPHY0 link B
668 * DIG3 drives UNIPHY1 link A, A+B
669 * DIG4 drives UNIPHY1 link B
670 * DIG5 drives UNIPHY2 link A, A+B
671 * DIG6 drives UNIPHY2 link B
672 *
1a66c95a
AD		 673 * Routing
674 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
675 * Examples:
676 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
677 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
678 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
679 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
680 */
bcc1c2a1
AD		 681
682union dig_encoder_control {
683 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
684 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
685 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
686};
687
688void
771fe6b9
JG		 689atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
690{
691 struct drm_device *dev = encoder->dev;
692 struct radeon_device *rdev = dev->dev_private;
693 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
9ae47867
AD		 694 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
695 struct radeon_connector_atom_dig *dig_connector =
696 radeon_get_atom_connector_priv_from_encoder(encoder);
bcc1c2a1 697 union dig_encoder_control args;
d9c9fe36 698 int index = 0;
771fe6b9 699 uint8_t frev, crev;
771fe6b9 700
9ae47867 701 if (!dig || !dig_connector)
771fe6b9
JG		 702 return;
703
771fe6b9
JG		 704 memset(&args, 0, sizeof(args));
705
bcc1c2a1
AD		 706 if (ASIC_IS_DCE4(rdev))
707 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
708 else {
709 if (dig->dig_encoder)
710 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
711 else
712 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
713 }
771fe6b9 714
a084e6ee
AD		 715 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
716 return;
771fe6b9 717
bcc1c2a1
AD		 718 args.v1.ucAction = action;
719 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
720 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
771fe6b9 721
bcc1c2a1
AD		 722 if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
723 if (dig_connector->dp_clock == 270000)
724 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
725 args.v1.ucLaneNum = dig_connector->dp_lane_count;
726 } else if (radeon_encoder->pixel_clock > 165000)
727 args.v1.ucLaneNum = 8;
728 else
729 args.v1.ucLaneNum = 4;
730
731 if (ASIC_IS_DCE4(rdev)) {
732 args.v3.acConfig.ucDigSel = dig->dig_encoder;
733 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
734 } else {
771fe6b9
JG		 735 switch (radeon_encoder->encoder_id) {
736 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
bcc1c2a1 737 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
771fe6b9
JG		 738 break;
739 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
bcc1c2a1
AD		 740 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
741 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
771fe6b9
JG		 742 break;
743 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
bcc1c2a1 744 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
771fe6b9
JG		 745 break;
746 }
bcc1c2a1
AD		 747 if (dig_connector->linkb)
748 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
749 else
750 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
771fe6b9
JG		 751 }
752
771fe6b9
JG		 753 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
754
755}
756
757union dig_transmitter_control {
758 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
759 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
bcc1c2a1 760 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
771fe6b9
JG		 761};
762
5801ead6 763void
1a66c95a 764atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
771fe6b9
JG		 765{
766 struct drm_device *dev = encoder->dev;
767 struct radeon_device *rdev = dev->dev_private;
768 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
9ae47867
AD		 769 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
770 struct radeon_connector_atom_dig *dig_connector =
771 radeon_get_atom_connector_priv_from_encoder(encoder);
772 struct drm_connector *connector;
773 struct radeon_connector *radeon_connector;
771fe6b9 774 union dig_transmitter_control args;
d9c9fe36 775 int index = 0;
771fe6b9 776 uint8_t frev, crev;
f92a8b67 777 bool is_dp = false;
bcc1c2a1 778 int pll_id = 0;
771fe6b9 779
9ae47867 780 if (!dig || !dig_connector)
771fe6b9
JG		 781 return;
782
9ae47867 783 connector = radeon_get_connector_for_encoder(encoder);
771fe6b9
JG		 784 radeon_connector = to_radeon_connector(connector);
785
f92a8b67
AD		 786 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
787 is_dp = true;
788
771fe6b9
JG		 789 memset(&args, 0, sizeof(args));
790
bcc1c2a1 791 if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev))
771fe6b9
JG		 792 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
793 else {
794 switch (radeon_encoder->encoder_id) {
795 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
796 index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
797 break;
798 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
799 index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
800 break;
801 }
802 }
803
a084e6ee
AD		 804 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
805 return;
771fe6b9
JG		 806
807 args.v1.ucAction = action;
f95a9f0b
AD		 808 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
809 args.v1.usInitInfo = radeon_connector->connector_object_id;
1a66c95a
AD		 810 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
811 args.v1.asMode.ucLaneSel = lane_num;
812 args.v1.asMode.ucLaneSet = lane_set;
f95a9f0b 813 } else {
f92a8b67
AD		 814 if (is_dp)
815 args.v1.usPixelClock =
5801ead6 816 cpu_to_le16(dig_connector->dp_clock / 10);
f92a8b67 817 else if (radeon_encoder->pixel_clock > 165000)
f95a9f0b
AD		 818 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
819 else
820 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
821 }
bcc1c2a1
AD		 822 if (ASIC_IS_DCE4(rdev)) {
823 if (is_dp)
824 args.v3.ucLaneNum = dig_connector->dp_lane_count;
825 else if (radeon_encoder->pixel_clock > 165000)
826 args.v3.ucLaneNum = 8;
827 else
828 args.v3.ucLaneNum = 4;
829
830 if (dig_connector->linkb) {
831 args.v3.acConfig.ucLinkSel = 1;
832 args.v3.acConfig.ucEncoderSel = 1;
833 }
834
835 /* Select the PLL for the PHY
836 * DP PHY should be clocked from external src if there is
837 * one.
838 */
839 if (encoder->crtc) {
840 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
841 pll_id = radeon_crtc->pll_id;
842 }
843 if (is_dp && rdev->clock.dp_extclk)
844 args.v3.acConfig.ucRefClkSource = 2; /* external src */
845 else
846 args.v3.acConfig.ucRefClkSource = pll_id;
847
848 switch (radeon_encoder->encoder_id) {
849 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
850 args.v3.acConfig.ucTransmitterSel = 0;
bcc1c2a1
AD		 851 break;
852 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
853 args.v3.acConfig.ucTransmitterSel = 1;
bcc1c2a1
AD		 854 break;
855 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
856 args.v3.acConfig.ucTransmitterSel = 2;
bcc1c2a1
AD		 857 break;
858 }
859
860 if (is_dp)
861 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
862 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
863 if (dig->coherent_mode)
864 args.v3.acConfig.fCoherentMode = 1;
b317a9ce
AD		 865 if (radeon_encoder->pixel_clock > 165000)
866 args.v3.acConfig.fDualLinkConnector = 1;
bcc1c2a1
AD		 867 }
868 } else if (ASIC_IS_DCE32(rdev)) {
d9c9fe36 869 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
1a66c95a
AD		 870 if (dig_connector->linkb)
871 args.v2.acConfig.ucLinkSel = 1;
771fe6b9
JG		 872
873 switch (radeon_encoder->encoder_id) {
874 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
875 args.v2.acConfig.ucTransmitterSel = 0;
771fe6b9
JG		 876 break;
877 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
878 args.v2.acConfig.ucTransmitterSel = 1;
771fe6b9
JG		 879 break;
880 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
881 args.v2.acConfig.ucTransmitterSel = 2;
771fe6b9
JG		 882 break;
883 }
884
f92a8b67
AD		 885 if (is_dp)
886 args.v2.acConfig.fCoherentMode = 1;
887 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
771fe6b9
JG		 888 if (dig->coherent_mode)
889 args.v2.acConfig.fCoherentMode = 1;
b317a9ce
AD		 890 if (radeon_encoder->pixel_clock > 165000)
891 args.v2.acConfig.fDualLinkConnector = 1;
771fe6b9
JG		 892 }
893 } else {
894 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
771fe6b9 895
f28cf339
DA		 896 if (dig->dig_encoder)
897 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
898 else
899 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
900
d9c9fe36
AD		 901 if ((rdev->flags & RADEON_IS_IGP) &&
902 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
903 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
904 if (dig_connector->igp_lane_info & 0x1)
905 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
906 else if (dig_connector->igp_lane_info & 0x2)
907 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
908 else if (dig_connector->igp_lane_info & 0x4)
909 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
910 else if (dig_connector->igp_lane_info & 0x8)
911 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
912 } else {
913 if (dig_connector->igp_lane_info & 0x3)
914 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
915 else if (dig_connector->igp_lane_info & 0xc)
916 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
771fe6b9 917 }
771fe6b9
JG		 918 }
919
1a66c95a
AD		 920 if (dig_connector->linkb)
921 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
922 else
923 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
924
f92a8b67
AD		 925 if (is_dp)
926 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
927 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
771fe6b9
JG		 928 if (dig->coherent_mode)
929 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
d9c9fe36
AD		 930 if (radeon_encoder->pixel_clock > 165000)
931 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
771fe6b9
JG		 932 }
933 }
934
935 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 936}
937
771fe6b9
JG		 938static void
939atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
940{
941 struct drm_device *dev = encoder->dev;
942 struct radeon_device *rdev = dev->dev_private;
943 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
944 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
945 ENABLE_YUV_PS_ALLOCATION args;
946 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
947 uint32_t temp, reg;
948
949 memset(&args, 0, sizeof(args));
950
951 if (rdev->family >= CHIP_R600)
952 reg = R600_BIOS_3_SCRATCH;
953 else
954 reg = RADEON_BIOS_3_SCRATCH;
955
956 /* XXX: fix up scratch reg handling */
957 temp = RREG32(reg);
4ce001ab 958 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9
JG		 959 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
960 (radeon_crtc->crtc_id << 18)));
4ce001ab 961 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 962 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
963 else
964 WREG32(reg, 0);
965
966 if (enable)
967 args.ucEnable = ATOM_ENABLE;
968 args.ucCRTC = radeon_crtc->crtc_id;
969
970 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
971
972 WREG32(reg, temp);
973}
974
771fe6b9
JG		 975static void
976radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
977{
978 struct drm_device *dev = encoder->dev;
979 struct radeon_device *rdev = dev->dev_private;
980 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
981 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
982 int index = 0;
983 bool is_dig = false;
984
985 memset(&args, 0, sizeof(args));
986
f641e51e
DA		 987 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
988 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
989 radeon_encoder->active_device);
771fe6b9
JG		 990 switch (radeon_encoder->encoder_id) {
991 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
992 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
993 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
994 break;
995 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
996 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
997 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
998 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
999 is_dig = true;
1000 break;
1001 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1002 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1003 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1004 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1005 break;
1006 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1007 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1008 break;
1009 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1010 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1011 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1012 else
1013 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1014 break;
1015 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1016 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
8c2a6d73 1017 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1018 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
8c2a6d73 1019 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1020 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1021 else
1022 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1023 break;
1024 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1025 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
8c2a6d73 1026 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1027 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
8c2a6d73 1028 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1029 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1030 else
1031 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1032 break;
1033 }
1034
1035 if (is_dig) {
1036 switch (mode) {
1037 case DRM_MODE_DPMS_ON:
fb668c2f 1038 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
58682f10 1039 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
fb668c2f 1040
58682f10 1041 dp_link_train(encoder, connector);
fb668c2f
AD		 1042 if (ASIC_IS_DCE4(rdev))
1043 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
58682f10 1044 }
fb668c2f
AD		 1045 if (!ASIC_IS_DCE4(rdev))
1046 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
771fe6b9
JG		 1047 break;
1048 case DRM_MODE_DPMS_STANDBY:
1049 case DRM_MODE_DPMS_SUSPEND:
1050 case DRM_MODE_DPMS_OFF:
fb668c2f
AD		 1051 if (!ASIC_IS_DCE4(rdev))
1052 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1053 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1054 if (ASIC_IS_DCE4(rdev))
1055 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1056 }
771fe6b9
JG		 1057 break;
1058 }
1059 } else {
1060 switch (mode) {
1061 case DRM_MODE_DPMS_ON:
1062 args.ucAction = ATOM_ENABLE;
1063 break;
1064 case DRM_MODE_DPMS_STANDBY:
1065 case DRM_MODE_DPMS_SUSPEND:
1066 case DRM_MODE_DPMS_OFF:
1067 args.ucAction = ATOM_DISABLE;
1068 break;
1069 }
1070 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1071 }
1072 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
c913e23a 1073
771fe6b9
JG		 1074}
1075
9ae47867 1076union crtc_source_param {
771fe6b9
JG		 1077 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1078 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1079};
1080
1081static void
1082atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1083{
1084 struct drm_device *dev = encoder->dev;
1085 struct radeon_device *rdev = dev->dev_private;
1086 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1087 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
9ae47867 1088 union crtc_source_param args;
771fe6b9
JG		 1089 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1090 uint8_t frev, crev;
f28cf339 1091 struct radeon_encoder_atom_dig *dig;
771fe6b9
JG		 1092
1093 memset(&args, 0, sizeof(args));
1094
a084e6ee
AD		 1095 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1096 return;
771fe6b9
JG		 1097
1098 switch (frev) {
1099 case 1:
1100 switch (crev) {
1101 case 1:
1102 default:
1103 if (ASIC_IS_AVIVO(rdev))
1104 args.v1.ucCRTC = radeon_crtc->crtc_id;
1105 else {
1106 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1107 args.v1.ucCRTC = radeon_crtc->crtc_id;
1108 } else {
1109 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1110 }
1111 }
1112 switch (radeon_encoder->encoder_id) {
1113 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1114 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1115 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1116 break;
1117 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1118 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1119 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1120 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1121 else
1122 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1123 break;
1124 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1125 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1126 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1127 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1128 break;
1129 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1130 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
4ce001ab 1131 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1132 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
4ce001ab 1133 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1134 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1135 else
1136 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1137 break;
1138 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1139 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
4ce001ab 1140 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1141 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
4ce001ab 1142 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1143 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1144 else
1145 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1146 break;
1147 }
1148 break;
1149 case 2:
1150 args.v2.ucCRTC = radeon_crtc->crtc_id;
1151 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1152 switch (radeon_encoder->encoder_id) {
1153 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1154 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1155 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
f28cf339
DA		 1156 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1157 dig = radeon_encoder->enc_priv;
bcc1c2a1
AD		 1158 switch (dig->dig_encoder) {
1159 case 0:
f28cf339 1160 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
bcc1c2a1
AD		 1161 break;
1162 case 1:
1163 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1164 break;
1165 case 2:
1166 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1167 break;
1168 case 3:
1169 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1170 break;
1171 case 4:
1172 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1173 break;
1174 case 5:
1175 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1176 break;
1177 }
771fe6b9
JG		 1178 break;
1179 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1180 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1181 break;
771fe6b9 1182 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
4ce001ab 1183 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1184 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
4ce001ab 1185 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1186 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1187 else
1188 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1189 break;
1190 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
4ce001ab 1191 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1192 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
4ce001ab 1193 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1194 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1195 else
1196 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1197 break;
1198 }
1199 break;
1200 }
1201 break;
1202 default:
1203 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1204 break;
1205 }
1206
1207 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
267364ac
AD		 1208
1209 /* update scratch regs with new routing */
1210 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
771fe6b9
JG		 1211}
1212
1213static void
1214atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1215 struct drm_display_mode *mode)
1216{
1217 struct drm_device *dev = encoder->dev;
1218 struct radeon_device *rdev = dev->dev_private;
1219 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1221
1222 /* Funky macbooks */
1223 if ((dev->pdev->device == 0x71C5) &&
1224 (dev->pdev->subsystem_vendor == 0x106b) &&
1225 (dev->pdev->subsystem_device == 0x0080)) {
1226 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1227 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1228
1229 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1230 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1231
1232 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1233 }
1234 }
1235
1236 /* set scaler clears this on some chips */
bcc1c2a1 1237 /* XXX check DCE4 */
ceefedd8
AD		 1238 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1239 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1240 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1241 AVIVO_D1MODE_INTERLEAVE_EN);
1242 }
771fe6b9
JG		 1243}
1244
f28cf339
DA		 1245static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1246{
1247 struct drm_device *dev = encoder->dev;
1248 struct radeon_device *rdev = dev->dev_private;
1249 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1250 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1251 struct drm_encoder *test_encoder;
1252 struct radeon_encoder_atom_dig *dig;
1253 uint32_t dig_enc_in_use = 0;
bcc1c2a1
AD		 1254
1255 if (ASIC_IS_DCE4(rdev)) {
1256 struct radeon_connector_atom_dig *dig_connector =
1257 radeon_get_atom_connector_priv_from_encoder(encoder);
1258
1259 switch (radeon_encoder->encoder_id) {
1260 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1261 if (dig_connector->linkb)
1262 return 1;
1263 else
1264 return 0;
1265 break;
1266 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1267 if (dig_connector->linkb)
1268 return 3;
1269 else
1270 return 2;
1271 break;
1272 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1273 if (dig_connector->linkb)
1274 return 5;
1275 else
1276 return 4;
1277 break;
1278 }
1279 }
1280
f28cf339
DA		 1281 /* on DCE32 and encoder can driver any block so just crtc id */
1282 if (ASIC_IS_DCE32(rdev)) {
1283 return radeon_crtc->crtc_id;
1284 }
1285
1286 /* on DCE3 - LVTMA can only be driven by DIGB */
1287 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1288 struct radeon_encoder *radeon_test_encoder;
1289
1290 if (encoder == test_encoder)
1291 continue;
1292
1293 if (!radeon_encoder_is_digital(test_encoder))
1294 continue;
1295
1296 radeon_test_encoder = to_radeon_encoder(test_encoder);
1297 dig = radeon_test_encoder->enc_priv;
1298
1299 if (dig->dig_encoder >= 0)
1300 dig_enc_in_use |= (1 << dig->dig_encoder);
1301 }
1302
1303 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1304 if (dig_enc_in_use & 0x2)
1305 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1306 return 1;
1307 }
1308 if (!(dig_enc_in_use & 1))
1309 return 0;
1310 return 1;
1311}
1312
771fe6b9
JG		 1313static void
1314radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1315 struct drm_display_mode *mode,
1316 struct drm_display_mode *adjusted_mode)
1317{
1318 struct drm_device *dev = encoder->dev;
1319 struct radeon_device *rdev = dev->dev_private;
1320 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
771fe6b9 1321
771fe6b9
JG		 1322 radeon_encoder->pixel_clock = adjusted_mode->clock;
1323
771fe6b9 1324 if (ASIC_IS_AVIVO(rdev)) {
4ce001ab 1325 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
771fe6b9
JG		 1326 atombios_yuv_setup(encoder, true);
1327 else
1328 atombios_yuv_setup(encoder, false);
1329 }
1330
1331 switch (radeon_encoder->encoder_id) {
1332 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1333 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1334 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1335 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1336 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1337 break;
1338 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1339 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1340 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1341 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
bcc1c2a1
AD		 1342 if (ASIC_IS_DCE4(rdev)) {
1343 /* disable the transmitter */
1344 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1345 /* setup and enable the encoder */
1346 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1347
1348 /* init and enable the transmitter */
1349 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1350 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1351 } else {
1352 /* disable the encoder and transmitter */
1353 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1354 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1355
1356 /* setup and enable the encoder and transmitter */
1357 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1358 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1359 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1360 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1361 }
771fe6b9
JG		 1362 break;
1363 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1364 atombios_ddia_setup(encoder, ATOM_ENABLE);
1365 break;
1366 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1367 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1368 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1369 break;
1370 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1371 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1372 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1373 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1374 atombios_dac_setup(encoder, ATOM_ENABLE);
d3a67a43
AD		 1375 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1376 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1377 atombios_tv_setup(encoder, ATOM_ENABLE);
1378 else
1379 atombios_tv_setup(encoder, ATOM_DISABLE);
1380 }
771fe6b9
JG		 1381 break;
1382 }
1383 atombios_apply_encoder_quirks(encoder, adjusted_mode);
dafc3bd5 1384
2cd6218c
RM		 1385 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1386 r600_hdmi_enable(encoder);
bcc1c2a1 1387 r600_hdmi_setmode(encoder, adjusted_mode);
2cd6218c 1388 }
771fe6b9
JG		 1389}
1390
1391static bool
4ce001ab 1392atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
771fe6b9
JG		 1393{
1394 struct drm_device *dev = encoder->dev;
1395 struct radeon_device *rdev = dev->dev_private;
1396 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4ce001ab 1397 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
771fe6b9
JG		 1398
1399 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1400 ATOM_DEVICE_CV_SUPPORT |
1401 ATOM_DEVICE_CRT_SUPPORT)) {
1402 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1403 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1404 uint8_t frev, crev;
1405
1406 memset(&args, 0, sizeof(args));
1407
a084e6ee
AD		 1408 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1409 return false;
771fe6b9
JG		 1410
1411 args.sDacload.ucMisc = 0;
1412
1413 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1414 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1415 args.sDacload.ucDacType = ATOM_DAC_A;
1416 else
1417 args.sDacload.ucDacType = ATOM_DAC_B;
1418
4ce001ab 1419 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
771fe6b9 1420 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
4ce001ab 1421 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
771fe6b9 1422 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
4ce001ab 1423 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
771fe6b9
JG		 1424 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1425 if (crev >= 3)
1426 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
4ce001ab 1427 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
771fe6b9
JG		 1428 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1429 if (crev >= 3)
1430 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1431 }
1432
1433 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1434
1435 return true;
1436 } else
1437 return false;
1438}
1439
1440static enum drm_connector_status
1441radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1442{
1443 struct drm_device *dev = encoder->dev;
1444 struct radeon_device *rdev = dev->dev_private;
1445 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4ce001ab 1446 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
771fe6b9
JG		 1447 uint32_t bios_0_scratch;
1448
4ce001ab 1449 if (!atombios_dac_load_detect(encoder, connector)) {
771fe6b9
JG		 1450 DRM_DEBUG("detect returned false \n");
1451 return connector_status_unknown;
1452 }
1453
1454 if (rdev->family >= CHIP_R600)
1455 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1456 else
1457 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1458
4ce001ab
DA		 1459 DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1460 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
771fe6b9
JG		 1461 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1462 return connector_status_connected;
4ce001ab
DA		 1463 }
1464 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
771fe6b9
JG		 1465 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1466 return connector_status_connected;
4ce001ab
DA		 1467 }
1468 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
771fe6b9
JG		 1469 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1470 return connector_status_connected;
4ce001ab
DA		 1471 }
1472 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
771fe6b9
JG		 1473 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1474 return connector_status_connected; /* CTV */
1475 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1476 return connector_status_connected; /* STV */
1477 }
1478 return connector_status_disconnected;
1479}
1480
1481static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1482{
267364ac
AD		 1483 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1484
1485 if (radeon_encoder->active_device &
1486 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1487 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1488 if (dig)
1489 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1490 }
1491
771fe6b9
JG		 1492 radeon_atom_output_lock(encoder, true);
1493 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
267364ac
AD		 1494
1495 /* this is needed for the pll/ss setup to work correctly in some cases */
1496 atombios_set_encoder_crtc_source(encoder);
771fe6b9
JG		 1497}
1498
1499static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1500{
1501 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1502 radeon_atom_output_lock(encoder, false);
1503}
1504
4ce001ab
DA		 1505static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1506{
aa961391
AD		 1507 struct drm_device *dev = encoder->dev;
1508 struct radeon_device *rdev = dev->dev_private;
4ce001ab 1509 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f28cf339 1510 struct radeon_encoder_atom_dig *dig;
4ce001ab 1511 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
f28cf339 1512
aa961391
AD		 1513 switch (radeon_encoder->encoder_id) {
1514 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1515 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1516 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1517 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1518 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1519 break;
1520 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1521 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1522 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1523 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1524 if (ASIC_IS_DCE4(rdev))
1525 /* disable the transmitter */
1526 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1527 else {
1528 /* disable the encoder and transmitter */
1529 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1530 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1531 }
1532 break;
1533 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1534 atombios_ddia_setup(encoder, ATOM_DISABLE);
1535 break;
1536 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1537 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1538 atombios_external_tmds_setup(encoder, ATOM_DISABLE);
1539 break;
1540 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1541 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1542 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1543 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1544 atombios_dac_setup(encoder, ATOM_DISABLE);
8bf3aae6 1545 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
aa961391
AD		 1546 atombios_tv_setup(encoder, ATOM_DISABLE);
1547 break;
1548 }
1549
f28cf339 1550 if (radeon_encoder_is_digital(encoder)) {
2cd6218c
RM		 1551 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1552 r600_hdmi_disable(encoder);
f28cf339
DA		 1553 dig = radeon_encoder->enc_priv;
1554 dig->dig_encoder = -1;
1555 }
4ce001ab
DA		 1556 radeon_encoder->active_device = 0;
1557}
1558
771fe6b9
JG		 1559static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1560 .dpms = radeon_atom_encoder_dpms,
1561 .mode_fixup = radeon_atom_mode_fixup,
1562 .prepare = radeon_atom_encoder_prepare,
1563 .mode_set = radeon_atom_encoder_mode_set,
1564 .commit = radeon_atom_encoder_commit,
4ce001ab 1565 .disable = radeon_atom_encoder_disable,
771fe6b9
JG		 1566 /* no detect for TMDS/LVDS yet */
1567};
1568
1569static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1570 .dpms = radeon_atom_encoder_dpms,
1571 .mode_fixup = radeon_atom_mode_fixup,
1572 .prepare = radeon_atom_encoder_prepare,
1573 .mode_set = radeon_atom_encoder_mode_set,
1574 .commit = radeon_atom_encoder_commit,
1575 .detect = radeon_atom_dac_detect,
1576};
1577
1578void radeon_enc_destroy(struct drm_encoder *encoder)
1579{
1580 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1581 kfree(radeon_encoder->enc_priv);
1582 drm_encoder_cleanup(encoder);
1583 kfree(radeon_encoder);
1584}
1585
1586static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1587 .destroy = radeon_enc_destroy,
1588};
1589
4ce001ab
DA		 1590struct radeon_encoder_atom_dac *
1591radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1592{
affd8589
AD		 1593 struct drm_device *dev = radeon_encoder->base.dev;
1594 struct radeon_device *rdev = dev->dev_private;
4ce001ab
DA		 1595 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1596
1597 if (!dac)
1598 return NULL;
1599
affd8589 1600 dac->tv_std = radeon_atombios_get_tv_info(rdev);
4ce001ab
DA		 1601 return dac;
1602}
1603
771fe6b9
JG		 1604struct radeon_encoder_atom_dig *
1605radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1606{
1607 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1608
1609 if (!dig)
1610 return NULL;
1611
1612 /* coherent mode by default */
1613 dig->coherent_mode = true;
f28cf339 1614 dig->dig_encoder = -1;
771fe6b9
JG		 1615
1616 return dig;
1617}
1618
1619void
1620radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1621{
dfee5614 1622 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 1623 struct drm_encoder *encoder;
1624 struct radeon_encoder *radeon_encoder;
1625
1626 /* see if we already added it */
1627 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1628 radeon_encoder = to_radeon_encoder(encoder);
1629 if (radeon_encoder->encoder_id == encoder_id) {
1630 radeon_encoder->devices |= supported_device;
1631 return;
1632 }
1633
1634 }
1635
1636 /* add a new one */
1637 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1638 if (!radeon_encoder)
1639 return;
1640
1641 encoder = &radeon_encoder->base;
bcc1c2a1
AD		 1642 switch (rdev->num_crtc) {
1643 case 1:
dfee5614 1644 encoder->possible_crtcs = 0x1;
bcc1c2a1
AD		 1645 break;
1646 case 2:
1647 default:
dfee5614 1648 encoder->possible_crtcs = 0x3;
bcc1c2a1
AD		 1649 break;
1650 case 6:
1651 encoder->possible_crtcs = 0x3f;
1652 break;
1653 }
771fe6b9
JG		 1654
1655 radeon_encoder->enc_priv = NULL;
1656
1657 radeon_encoder->encoder_id = encoder_id;
1658 radeon_encoder->devices = supported_device;
c93bb85b 1659 radeon_encoder->rmx_type = RMX_OFF;
771fe6b9
JG		 1660
1661 switch (radeon_encoder->encoder_id) {
1662 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1663 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1664 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1665 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1666 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1667 radeon_encoder->rmx_type = RMX_FULL;
1668 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1669 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1670 } else {
1671 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1672 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1673 }
1674 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1675 break;
1676 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1677 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
affd8589 1678 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
771fe6b9
JG		 1679 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1680 break;
1681 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1682 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1683 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1684 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
4ce001ab 1685 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
771fe6b9
JG		 1686 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1687 break;
1688 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1689 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1690 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1691 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1692 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1693 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1694 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
60d15f55
AD		 1695 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1696 radeon_encoder->rmx_type = RMX_FULL;
1697 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1698 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1699 } else {
1700 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1701 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1702 }
771fe6b9
JG		 1703 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1704 break;
1705 }
1706}
Linux kernel - Deliverables
This page took 0.152282 seconds and 5 git commands to generate.