[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_fb.c

/*
 * Copyright © 2007 David Airlie
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *     David Airlie
 */
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/fb.h>

#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "radeon_drm.h"
#include "radeon.h"

#include "drm_fb_helper.h"

#include <linux/vga_switcheroo.h>

/* object hierarchy -
   this contains a helper + a radeon fb
   the helper contains a pointer to radeon framebuffer baseclass.
*/
struct radeon_fbdev {
	struct drm_fb_helper helper;
	struct radeon_framebuffer rfb;
	struct list_head fbdev_list;
	struct radeon_device *rdev;
};

static struct fb_ops radeonfb_ops = {
	.owner = THIS_MODULE,
	.fb_check_var = drm_fb_helper_check_var,
	.fb_set_par = drm_fb_helper_set_par,
	.fb_fillrect = cfb_fillrect,
	.fb_copyarea = cfb_copyarea,
	.fb_imageblit = cfb_imageblit,
	.fb_pan_display = drm_fb_helper_pan_display,
	.fb_blank = drm_fb_helper_blank,
	.fb_setcmap = drm_fb_helper_setcmap,
	.fb_debug_enter = drm_fb_helper_debug_enter,
	.fb_debug_leave = drm_fb_helper_debug_leave,
};


static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
{
	int aligned = width;
	int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
	int pitch_mask = 0;

	switch (bpp / 8) {
	case 1:
		pitch_mask = align_large ? 255 : 127;
		break;
	case 2:
		pitch_mask = align_large ? 127 : 31;
		break;
	case 3:
	case 4:
		pitch_mask = align_large ? 63 : 15;
		break;
	}

	aligned += pitch_mask;
	aligned &= ~pitch_mask;
	return aligned;
}

static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
{
	struct radeon_bo *rbo = gobj->driver_private;
	int ret;

	ret = radeon_bo_reserve(rbo, false);
	if (likely(ret == 0)) {
		radeon_bo_kunmap(rbo);
		radeon_bo_unpin(rbo);
		radeon_bo_unreserve(rbo);
	}
	drm_gem_object_unreference_unlocked(gobj);
}

static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
					 struct drm_mode_fb_cmd *mode_cmd,
					 struct drm_gem_object **gobj_p)
{
	struct radeon_device *rdev = rfbdev->rdev;
	struct drm_gem_object *gobj = NULL;
	struct radeon_bo *rbo = NULL;
	bool fb_tiled = false; /* useful for testing */
	u32 tiling_flags = 0;
	int ret;
	int aligned_size, size;

	/* need to align pitch with crtc limits */
	mode_cmd->pitch = radeon_align_pitch(rdev, mode_cmd->width, mode_cmd->bpp, fb_tiled) * ((mode_cmd->bpp + 1) / 8);

	size = mode_cmd->pitch * mode_cmd->height;
	aligned_size = ALIGN(size, PAGE_SIZE);
	ret = radeon_gem_object_create(rdev, aligned_size, 0,
				       RADEON_GEM_DOMAIN_VRAM,
				       false, true,
				       &gobj);
	if (ret) {
		printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
		       aligned_size);
		return -ENOMEM;
	}
	rbo = gobj->driver_private;

	if (fb_tiled)
		tiling_flags = RADEON_TILING_MACRO;

#ifdef __BIG_ENDIAN
	switch (mode_cmd->bpp) {
	case 32:
		tiling_flags |= RADEON_TILING_SWAP_32BIT;
		break;
	case 16:
		tiling_flags |= RADEON_TILING_SWAP_16BIT;
	default:
		break;
	}
#endif

	if (tiling_flags) {
		ret = radeon_bo_set_tiling_flags(rbo,
						 tiling_flags | RADEON_TILING_SURFACE,
						 mode_cmd->pitch);
		if (ret)
			dev_err(rdev->dev, "FB failed to set tiling flags\n");
	}


	ret = radeon_bo_reserve(rbo, false);
	if (unlikely(ret != 0))
		goto out_unref;
	ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, NULL);
	if (ret) {
		radeon_bo_unreserve(rbo);
		goto out_unref;
	}
	if (fb_tiled)
		radeon_bo_check_tiling(rbo, 0, 0);
	ret = radeon_bo_kmap(rbo, NULL);
	radeon_bo_unreserve(rbo);
	if (ret) {
		goto out_unref;
	}

	*gobj_p = gobj;
	return 0;
out_unref:
	radeonfb_destroy_pinned_object(gobj);
	*gobj_p = NULL;
	return ret;
}

static int radeonfb_create(struct radeon_fbdev *rfbdev,
			   struct drm_fb_helper_surface_size *sizes)
{
	struct radeon_device *rdev = rfbdev->rdev;
	struct fb_info *info;
	struct drm_framebuffer *fb = NULL;
	struct drm_mode_fb_cmd mode_cmd;
	struct drm_gem_object *gobj = NULL;
	struct radeon_bo *rbo = NULL;
	struct device *device = &rdev->pdev->dev;
	int ret;
	unsigned long tmp;

	mode_cmd.width = sizes->surface_width;
	mode_cmd.height = sizes->surface_height;

	/* avivo can't scanout real 24bpp */
	if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
		sizes->surface_bpp = 32;

	mode_cmd.bpp = sizes->surface_bpp;
	mode_cmd.depth = sizes->surface_depth;

	ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
	rbo = gobj->driver_private;

	/* okay we have an object now allocate the framebuffer */
	info = framebuffer_alloc(0, device);
	if (info == NULL) {
		ret = -ENOMEM;
		goto out_unref;
	}

	info->par = rfbdev;

	radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);

	fb = &rfbdev->rfb.base;

	/* setup helper */
	rfbdev->helper.fb = fb;
	rfbdev->helper.fbdev = info;

	memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));

	strcpy(info->fix.id, "radeondrmfb");

	drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);

	info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
	info->fbops = &radeonfb_ops;

	tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
	info->fix.smem_start = rdev->mc.aper_base + tmp;
	info->fix.smem_len = radeon_bo_size(rbo);
	info->screen_base = rbo->kptr;
	info->screen_size = radeon_bo_size(rbo);

	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);

	/* setup aperture base/size for vesafb takeover */
	info->apertures = alloc_apertures(1);
	if (!info->apertures) {
		ret = -ENOMEM;
		goto out_unref;
	}
	info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
	info->apertures->ranges[0].size = rdev->mc.real_vram_size;

	info->fix.mmio_start = 0;
	info->fix.mmio_len = 0;
	info->pixmap.size = 64*1024;
	info->pixmap.buf_align = 8;
	info->pixmap.access_align = 32;
	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	info->pixmap.scan_align = 1;

	if (info->screen_base == NULL) {
		ret = -ENOSPC;
		goto out_unref;
	}

	ret = fb_alloc_cmap(&info->cmap, 256, 0);
	if (ret) {
		ret = -ENOMEM;
		goto out_unref;
	}

	DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
	DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)rdev->mc.aper_base);
	DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
	DRM_INFO("fb depth is %d\n", fb->depth);
	DRM_INFO("   pitch is %d\n", fb->pitch);

	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
	return 0;

out_unref:
	if (rbo) {

	}
	if (fb && ret) {
		drm_gem_object_unreference(gobj);
		drm_framebuffer_cleanup(fb);
		kfree(fb);
	}
	return ret;
}

static int radeon_fb_find_or_create_single(struct drm_fb_helper *helper,
					   struct drm_fb_helper_surface_size *sizes)
{
	struct radeon_fbdev *rfbdev = (struct radeon_fbdev *)helper;
	int new_fb = 0;
	int ret;

	if (!helper->fb) {
		ret = radeonfb_create(rfbdev, sizes);
		if (ret)
			return ret;
		new_fb = 1;
	}
	return new_fb;
}

static char *mode_option;
int radeon_parse_options(char *options)
{
	char *this_opt;

	if (!options || !*options)
		return 0;

	while ((this_opt = strsep(&options, ",")) != NULL) {
		if (!*this_opt)
			continue;
		mode_option = this_opt;
	}
	return 0;
}

void radeon_fb_output_poll_changed(struct radeon_device *rdev)
{
	drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper);
}

static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev)
{
	struct fb_info *info;
	struct radeon_framebuffer *rfb = &rfbdev->rfb;

	if (rfbdev->helper.fbdev) {
		info = rfbdev->helper.fbdev;

		unregister_framebuffer(info);
		if (info->cmap.len)
			fb_dealloc_cmap(&info->cmap);
		framebuffer_release(info);
	}

	if (rfb->obj) {
		radeonfb_destroy_pinned_object(rfb->obj);
		rfb->obj = NULL;
	}
	drm_fb_helper_fini(&rfbdev->helper);
	drm_framebuffer_cleanup(&rfb->base);

	return 0;
}

static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
	.gamma_set = radeon_crtc_fb_gamma_set,
	.gamma_get = radeon_crtc_fb_gamma_get,
	.fb_probe = radeon_fb_find_or_create_single,
};

int radeon_fbdev_init(struct radeon_device *rdev)
{
	struct radeon_fbdev *rfbdev;
	int bpp_sel = 32;
	int ret;

	/* select 8 bpp console on RN50 or 16MB cards */
	if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024))
		bpp_sel = 8;

	rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL);
	if (!rfbdev)
		return -ENOMEM;

	rfbdev->rdev = rdev;
	rdev->mode_info.rfbdev = rfbdev;
	rfbdev->helper.funcs = &radeon_fb_helper_funcs;

	ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper,
				 rdev->num_crtc,
				 RADEONFB_CONN_LIMIT);
	if (ret) {
		kfree(rfbdev);
		return ret;
	}

	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
	return 0;
}

void radeon_fbdev_fini(struct radeon_device *rdev)
{
	if (!rdev->mode_info.rfbdev)
		return;

	radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
	kfree(rdev->mode_info.rfbdev);
	rdev->mode_info.rfbdev = NULL;
}

void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
{
	fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state);
}

int radeon_fbdev_total_size(struct radeon_device *rdev)
{
	struct radeon_bo *robj;
	int size = 0;

	robj = rdev->mode_info.rfbdev->rfb.obj->driver_private;
	size += radeon_bo_size(robj);
	return size;
}

bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
{
	if (robj == rdev->mode_info.rfbdev->rfb.obj->driver_private)
		return true;
	return false;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright © 2007 David Airlie
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* David Airlie
	25	*/
771fe6b9	26	#include <linux/module.h>
5a0e3ad6	27	#include <linux/slab.h>
771fe6b9	28	#include <linux/fb.h>
771fe6b9 JG	29
	30	#include "drmP.h"
	31	#include "drm.h"
	32	#include "drm_crtc.h"
	33	#include "drm_crtc_helper.h"
	34	#include "radeon_drm.h"
	35	#include "radeon.h"
	36
785b93ef DA	37	#include "drm_fb_helper.h"
785b93ef DA	38
6a9ee8af DA	39	#include <linux/vga_switcheroo.h>
6a9ee8af DA	40
38651674 DA	41	/* object hierarchy -
	42	this contains a helper + a radeon fb
	43	the helper contains a pointer to radeon framebuffer baseclass.
	44	*/
8be48d92	45	struct radeon_fbdev {
785b93ef	46	struct drm_fb_helper helper;
38651674 DA	47	struct radeon_framebuffer rfb;
	48	struct list_head fbdev_list;
	49	struct radeon_device *rdev;
771fe6b9 JG	50	};
771fe6b9 JG	51
771fe6b9 JG	52	static struct fb_ops radeonfb_ops = {
771fe6b9 JG	53	.owner = THIS_MODULE,
c88f9f0c	54	.fb_check_var = drm_fb_helper_check_var,
785b93ef	55	.fb_set_par = drm_fb_helper_set_par,
771fe6b9 JG	56	.fb_fillrect = cfb_fillrect,
	57	.fb_copyarea = cfb_copyarea,
	58	.fb_imageblit = cfb_imageblit,
785b93ef DA	59	.fb_pan_display = drm_fb_helper_pan_display,
785b93ef DA	60	.fb_blank = drm_fb_helper_blank,
068143d3	61	.fb_setcmap = drm_fb_helper_setcmap,
4dd19b0d CB	62	.fb_debug_enter = drm_fb_helper_debug_enter,
4dd19b0d CB	63	.fb_debug_leave = drm_fb_helper_debug_leave,
771fe6b9 JG	64	};
771fe6b9 JG	65
771fe6b9	66
e024e110	67	static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
771fe6b9 JG	68	{
771fe6b9 JG	69	int aligned = width;
e024e110	70	int align_large = (ASIC_IS_AVIVO(rdev)) \|\| tiled;
771fe6b9 JG	71	int pitch_mask = 0;
	72
	73	switch (bpp / 8) {
	74	case 1:
	75	pitch_mask = align_large ? 255 : 127;
	76	break;
	77	case 2:
	78	pitch_mask = align_large ? 127 : 31;
	79	break;
	80	case 3:
	81	case 4:
	82	pitch_mask = align_large ? 63 : 15;
	83	break;
	84	}
	85
	86	aligned += pitch_mask;
	87	aligned &= ~pitch_mask;
	88	return aligned;
	89	}
	90
8be48d92	91	static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
771fe6b9	92	{
8be48d92 DA	93	struct radeon_bo *rbo = gobj->driver_private;
	94	int ret;
	95
	96	ret = radeon_bo_reserve(rbo, false);
	97	if (likely(ret == 0)) {
	98	radeon_bo_kunmap(rbo);
29d08b3e	99	radeon_bo_unpin(rbo);
8be48d92 DA	100	radeon_bo_unreserve(rbo);
	101	}
	102	drm_gem_object_unreference_unlocked(gobj);
	103	}
785b93ef	104
8be48d92 DA	105	static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
	106	struct drm_mode_fb_cmd *mode_cmd,
	107	struct drm_gem_object **gobj_p)
771fe6b9	108	{
8be48d92	109	struct radeon_device *rdev = rfbdev->rdev;
771fe6b9	110	struct drm_gem_object *gobj = NULL;
4c788679	111	struct radeon_bo *rbo = NULL;
e024e110	112	bool fb_tiled = false; /* useful for testing */
c88f9f0c	113	u32 tiling_flags = 0;
8be48d92 DA	114	int ret;
8be48d92 DA	115	int aligned_size, size;
771fe6b9	116
771fe6b9	117	/* need to align pitch with crtc limits */
8be48d92	118	mode_cmd->pitch = radeon_align_pitch(rdev, mode_cmd->width, mode_cmd->bpp, fb_tiled) * ((mode_cmd->bpp + 1) / 8);
771fe6b9	119
8be48d92	120	size = mode_cmd->pitch * mode_cmd->height;
771fe6b9	121	aligned_size = ALIGN(size, PAGE_SIZE);
771fe6b9	122	ret = radeon_gem_object_create(rdev, aligned_size, 0,
8be48d92	123	RADEON_GEM_DOMAIN_VRAM,
4dfe947e	124	false, true,
8be48d92	125	&gobj);
771fe6b9	126	if (ret) {
8be48d92 DA	127	printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
	128	aligned_size);
	129	return -ENOMEM;
771fe6b9	130	}
4c788679	131	rbo = gobj->driver_private;
771fe6b9	132
e024e110	133	if (fb_tiled)
c88f9f0c MD	134	tiling_flags = RADEON_TILING_MACRO;
	135
	136	#ifdef __BIG_ENDIAN
8be48d92	137	switch (mode_cmd->bpp) {
c88f9f0c MD	138	case 32:
	139	tiling_flags \|= RADEON_TILING_SWAP_32BIT;
	140	break;
	141	case 16:
	142	tiling_flags \|= RADEON_TILING_SWAP_16BIT;
	143	default:
	144	break;
	145	}
	146	#endif
	147
4c788679 JG	148	if (tiling_flags) {
4c788679 JG	149	ret = radeon_bo_set_tiling_flags(rbo,
8be48d92 DA	150	tiling_flags \| RADEON_TILING_SURFACE,
8be48d92 DA	151	mode_cmd->pitch);
4c788679 JG	152	if (ret)
	153	dev_err(rdev->dev, "FB failed to set tiling flags\n");
	154	}
8be48d92	155
38651674	156
4c788679 JG	157	ret = radeon_bo_reserve(rbo, false);
	158	if (unlikely(ret != 0))
	159	goto out_unref;
8be48d92	160	ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, NULL);
4c788679 JG	161	if (ret) {
	162	radeon_bo_unreserve(rbo);
	163	goto out_unref;
	164	}
	165	if (fb_tiled)
	166	radeon_bo_check_tiling(rbo, 0, 0);
8be48d92	167	ret = radeon_bo_kmap(rbo, NULL);
4c788679	168	radeon_bo_unreserve(rbo);
f92e93eb	169	if (ret) {
f92e93eb JG	170	goto out_unref;
f92e93eb JG	171	}
771fe6b9	172
8be48d92 DA	173	*gobj_p = gobj;
	174	return 0;
	175	out_unref:
	176	radeonfb_destroy_pinned_object(gobj);
	177	*gobj_p = NULL;
	178	return ret;
	179	}
	180
	181	static int radeonfb_create(struct radeon_fbdev *rfbdev,
	182	struct drm_fb_helper_surface_size *sizes)
	183	{
	184	struct radeon_device *rdev = rfbdev->rdev;
	185	struct fb_info *info;
	186	struct drm_framebuffer *fb = NULL;
	187	struct drm_mode_fb_cmd mode_cmd;
	188	struct drm_gem_object *gobj = NULL;
	189	struct radeon_bo *rbo = NULL;
	190	struct device *device = &rdev->pdev->dev;
	191	int ret;
	192	unsigned long tmp;
	193
	194	mode_cmd.width = sizes->surface_width;
	195	mode_cmd.height = sizes->surface_height;
	196
	197	/* avivo can't scanout real 24bpp */
	198	if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
	199	sizes->surface_bpp = 32;
	200
	201	mode_cmd.bpp = sizes->surface_bpp;
	202	mode_cmd.depth = sizes->surface_depth;
771fe6b9	203
8be48d92 DA	204	ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
8be48d92 DA	205	rbo = gobj->driver_private;
771fe6b9	206
8be48d92 DA	207	/* okay we have an object now allocate the framebuffer */
8be48d92 DA	208	info = framebuffer_alloc(0, device);
771fe6b9 JG	209	if (info == NULL) {
	210	ret = -ENOMEM;
	211	goto out_unref;
	212	}
785b93ef	213
8be48d92	214	info->par = rfbdev;
771fe6b9	215
8be48d92 DA	216	radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
8be48d92 DA	217
38651674 DA	218	fb = &rfbdev->rfb.base;
	219
	220	/* setup helper */
	221	rfbdev->helper.fb = fb;
	222	rfbdev->helper.fbdev = info;
38651674	223
8be48d92	224	memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));
bf8e828b	225
771fe6b9	226	strcpy(info->fix.id, "radeondrmfb");
785b93ef	227
068143d3	228	drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
785b93ef	229
8fd4bd22	230	info->flags = FBINFO_DEFAULT \| FBINFO_CAN_FORCE_OUTPUT;
771fe6b9	231	info->fbops = &radeonfb_ops;
785b93ef	232
8be48d92	233	tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
f92e93eb	234	info->fix.smem_start = rdev->mc.aper_base + tmp;
8be48d92 DA	235	info->fix.smem_len = radeon_bo_size(rbo);
	236	info->screen_base = rbo->kptr;
	237	info->screen_size = radeon_bo_size(rbo);
785b93ef	238
38651674	239	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
ed8f0d9e DA	240
ed8f0d9e DA	241	/* setup aperture base/size for vesafb takeover */
1471ca9a MS	242	info->apertures = alloc_apertures(1);
	243	if (!info->apertures) {
	244	ret = -ENOMEM;
	245	goto out_unref;
	246	}
	247	info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
	248	info->apertures->ranges[0].size = rdev->mc.real_vram_size;
ed8f0d9e	249
696d4df1 MD	250	info->fix.mmio_start = 0;
696d4df1 MD	251	info->fix.mmio_len = 0;
771fe6b9 JG	252	info->pixmap.size = 64*1024;
	253	info->pixmap.buf_align = 8;
	254	info->pixmap.access_align = 32;
	255	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	256	info->pixmap.scan_align = 1;
4abe3520	257
771fe6b9 JG	258	if (info->screen_base == NULL) {
	259	ret = -ENOSPC;
	260	goto out_unref;
	261	}
4abe3520 DA	262
	263	ret = fb_alloc_cmap(&info->cmap, 256, 0);
	264	if (ret) {
	265	ret = -ENOMEM;
	266	goto out_unref;
	267	}
	268
771fe6b9 JG	269	DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
771fe6b9 JG	270	DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base);
8be48d92	271	DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
771fe6b9 JG	272	DRM_INFO("fb depth is %d\n", fb->depth);
	273	DRM_INFO(" pitch is %d\n", fb->pitch);
	274
6a9ee8af	275	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
771fe6b9 JG	276	return 0;
	277
	278	out_unref:
4c788679	279	if (rbo) {
8be48d92	280
771fe6b9	281	}
f92e93eb	282	if (fb && ret) {
771fe6b9 JG	283	drm_gem_object_unreference(gobj);
	284	drm_framebuffer_cleanup(fb);
	285	kfree(fb);
	286	}
771fe6b9 JG	287	return ret;
	288	}
	289
8be48d92 DA	290	static int radeon_fb_find_or_create_single(struct drm_fb_helper *helper,
8be48d92 DA	291	struct drm_fb_helper_surface_size *sizes)
38651674	292	{
8be48d92	293	struct radeon_fbdev rfbdev = (struct radeon_fbdev )helper;
38651674 DA	294	int new_fb = 0;
	295	int ret;
	296
8be48d92 DA	297	if (!helper->fb) {
8be48d92 DA	298	ret = radeonfb_create(rfbdev, sizes);
38651674 DA	299	if (ret)
38651674 DA	300	return ret;
38651674	301	new_fb = 1;
38651674	302	}
38651674 DA	303	return new_fb;
	304	}
	305
d50ba256 DA	306	static char *mode_option;
	307	int radeon_parse_options(char *options)
	308	{
	309	char *this_opt;
	310
	311	if (!options \|\| !*options)
	312	return 0;
	313
	314	while ((this_opt = strsep(&options, ",")) != NULL) {
	315	if (!*this_opt)
	316	continue;
	317	mode_option = this_opt;
	318	}
	319	return 0;
	320	}
	321
eb1f8e4f	322	void radeon_fb_output_poll_changed(struct radeon_device *rdev)
771fe6b9	323	{
eb1f8e4f	324	drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper);
771fe6b9	325	}
771fe6b9	326
8be48d92	327	static int radeon_fbdev_destroy(struct drm_device dev, struct radeon_fbdev rfbdev)
771fe6b9 JG	328	{
771fe6b9 JG	329	struct fb_info *info;
38651674	330	struct radeon_framebuffer *rfb = &rfbdev->rfb;
771fe6b9	331
8be48d92 DA	332	if (rfbdev->helper.fbdev) {
8be48d92 DA	333	info = rfbdev->helper.fbdev;
4abe3520	334
8be48d92	335	unregister_framebuffer(info);
4abe3520 DA	336	if (info->cmap.len)
4abe3520 DA	337	fb_dealloc_cmap(&info->cmap);
8be48d92	338	framebuffer_release(info);
771fe6b9	339	}
771fe6b9	340
8be48d92	341	if (rfb->obj) {
29d08b3e DA	342	radeonfb_destroy_pinned_object(rfb->obj);
29d08b3e DA	343	rfb->obj = NULL;
771fe6b9	344	}
4abe3520	345	drm_fb_helper_fini(&rfbdev->helper);
38651674	346	drm_framebuffer_cleanup(&rfb->base);
771fe6b9	347
771fe6b9 JG	348	return 0;
771fe6b9 JG	349	}
785b93ef	350
4abe3520 DA	351	static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
	352	.gamma_set = radeon_crtc_fb_gamma_set,
	353	.gamma_get = radeon_crtc_fb_gamma_get,
	354	.fb_probe = radeon_fb_find_or_create_single,
4abe3520	355	};
38651674 DA	356
	357	int radeon_fbdev_init(struct radeon_device *rdev)
	358	{
8be48d92	359	struct radeon_fbdev *rfbdev;
4abe3520	360	int bpp_sel = 32;
5a79395b	361	int ret;
4abe3520 DA	362
	363	/* select 8 bpp console on RN50 or 16MB cards */
	364	if (ASIC_IS_RN50(rdev) \|\| rdev->mc.real_vram_size <= (3210241024))
	365	bpp_sel = 8;
8be48d92 DA	366
	367	rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL);
	368	if (!rfbdev)
	369	return -ENOMEM;
	370
	371	rfbdev->rdev = rdev;
	372	rdev->mode_info.rfbdev = rfbdev;
4abe3520	373	rfbdev->helper.funcs = &radeon_fb_helper_funcs;
8be48d92	374
5a79395b CW	375	ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper,
	376	rdev->num_crtc,
	377	RADEONFB_CONN_LIMIT);
	378	if (ret) {
	379	kfree(rfbdev);
	380	return ret;
	381	}
	382
0b4c0f3f	383	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
4abe3520	384	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
771fe6b9	385	return 0;
38651674 DA	386	}
	387
	388	void radeon_fbdev_fini(struct radeon_device *rdev)
	389	{
8be48d92 DA	390	if (!rdev->mode_info.rfbdev)
	391	return;
	392
38651674	393	radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
8be48d92	394	kfree(rdev->mode_info.rfbdev);
38651674 DA	395	rdev->mode_info.rfbdev = NULL;
	396	}
	397
	398	void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
	399	{
	400	fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state);
	401	}
	402
	403	int radeon_fbdev_total_size(struct radeon_device *rdev)
	404	{
	405	struct radeon_bo *robj;
	406	int size = 0;
	407
	408	robj = rdev->mode_info.rfbdev->rfb.obj->driver_private;
	409	size += radeon_bo_size(robj);
	410	return size;
	411	}
	412
	413	bool radeon_fbdev_robj_is_fb(struct radeon_device rdev, struct radeon_bo robj)
	414	{
	415	if (robj == rdev->mode_info.rfbdev->rfb.obj->driver_private)
	416	return true;
	417	return false;
771fe6b9	418	}