Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
2d1a8a48 PG |
26 | #include <linux/export.h> |
27 | ||
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/drm_edid.h> | |
30 | #include <drm/radeon_drm.h> | |
771fe6b9 | 31 | #include "radeon.h" |
40bacf16 | 32 | #include "atom.h" |
771fe6b9 | 33 | |
30388c6e AD |
34 | extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap, |
35 | struct i2c_msg *msgs, int num); | |
36 | extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap); | |
37 | ||
771fe6b9 JG |
38 | /** |
39 | * radeon_ddc_probe | |
40 | * | |
41 | */ | |
0a9069d3 | 42 | bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux) |
771fe6b9 | 43 | { |
e384fab8 TR |
44 | u8 out = 0x0; |
45 | u8 buf[8]; | |
771fe6b9 JG |
46 | int ret; |
47 | struct i2c_msg msgs[] = { | |
48 | { | |
370a53f9 | 49 | .addr = DDC_ADDR, |
771fe6b9 JG |
50 | .flags = 0, |
51 | .len = 1, | |
e384fab8 | 52 | .buf = &out, |
771fe6b9 JG |
53 | }, |
54 | { | |
370a53f9 | 55 | .addr = DDC_ADDR, |
771fe6b9 | 56 | .flags = I2C_M_RD, |
bc1c4dc3 | 57 | .len = 8, |
771fe6b9 JG |
58 | .buf = buf, |
59 | } | |
60 | }; | |
61 | ||
26b5bc98 | 62 | /* on hw with routers, select right port */ |
fb939dfc AD |
63 | if (radeon_connector->router.ddc_valid) |
64 | radeon_router_select_ddc_port(radeon_connector); | |
26b5bc98 | 65 | |
0a9069d3 NOS |
66 | if (use_aux) { |
67 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; | |
68 | ret = i2c_transfer(&dig->dp_i2c_bus->adapter, msgs, 2); | |
69 | } else { | |
70 | ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); | |
71 | } | |
72 | ||
e384fab8 TR |
73 | if (ret != 2) |
74 | /* Couldn't find an accessible DDC on this connector */ | |
75 | return false; | |
bc1c4dc3 AD |
76 | /* Probe also for valid EDID header |
77 | * EDID header starts with: | |
78 | * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. | |
79 | * Only the first 6 bytes must be valid as | |
80 | * drm_edid_block_valid() can fix the last 2 bytes */ | |
81 | if (drm_edid_header_is_valid(buf) < 6) { | |
82 | /* Couldn't find an accessible EDID on this | |
83 | * connector */ | |
84 | return false; | |
e384fab8 TR |
85 | } |
86 | return true; | |
771fe6b9 JG |
87 | } |
88 | ||
ac1aade6 | 89 | /* bit banging i2c */ |
771fe6b9 | 90 | |
43e5f612 | 91 | static int pre_xfer(struct i2c_adapter *i2c_adap) |
771fe6b9 | 92 | { |
43e5f612 | 93 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); |
ab1e9ea0 AD |
94 | struct radeon_device *rdev = i2c->dev->dev_private; |
95 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
771fe6b9 | 96 | uint32_t temp; |
771fe6b9 JG |
97 | |
98 | /* RV410 appears to have a bug where the hw i2c in reset | |
99 | * holds the i2c port in a bad state - switch hw i2c away before | |
100 | * doing DDC - do this for all r200s/r300s/r400s for safety sake | |
101 | */ | |
6a93cb25 AD |
102 | if (rec->hw_capable) { |
103 | if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { | |
40bacf16 AD |
104 | u32 reg; |
105 | ||
106 | if (rdev->family >= CHIP_RV350) | |
107 | reg = RADEON_GPIO_MONID; | |
108 | else if ((rdev->family == CHIP_R300) || | |
109 | (rdev->family == CHIP_R350)) | |
110 | reg = RADEON_GPIO_DVI_DDC; | |
111 | else | |
112 | reg = RADEON_GPIO_CRT2_DDC; | |
113 | ||
114 | mutex_lock(&rdev->dc_hw_i2c_mutex); | |
115 | if (rec->a_clk_reg == reg) { | |
6a93cb25 AD |
116 | WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | |
117 | R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); | |
118 | } else { | |
119 | WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | | |
120 | R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); | |
121 | } | |
40bacf16 | 122 | mutex_unlock(&rdev->dc_hw_i2c_mutex); |
771fe6b9 JG |
123 | } |
124 | } | |
771fe6b9 | 125 | |
5786e2c5 AD |
126 | /* switch the pads to ddc mode */ |
127 | if (ASIC_IS_DCE3(rdev) && rec->hw_capable) { | |
128 | temp = RREG32(rec->mask_clk_reg); | |
129 | temp &= ~(1 << 16); | |
130 | WREG32(rec->mask_clk_reg, temp); | |
131 | } | |
132 | ||
9b9fe724 AD |
133 | /* clear the output pin values */ |
134 | temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; | |
135 | WREG32(rec->a_clk_reg, temp); | |
136 | ||
137 | temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; | |
138 | WREG32(rec->a_data_reg, temp); | |
139 | ||
6a93cb25 AD |
140 | /* set the pins to input */ |
141 | temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; | |
142 | WREG32(rec->en_clk_reg, temp); | |
143 | ||
144 | temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; | |
145 | WREG32(rec->en_data_reg, temp); | |
9b9fe724 AD |
146 | |
147 | /* mask the gpio pins for software use */ | |
43e5f612 | 148 | temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; |
771fe6b9 JG |
149 | WREG32(rec->mask_clk_reg, temp); |
150 | temp = RREG32(rec->mask_clk_reg); | |
151 | ||
43e5f612 JD |
152 | temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; |
153 | WREG32(rec->mask_data_reg, temp); | |
771fe6b9 | 154 | temp = RREG32(rec->mask_data_reg); |
43e5f612 JD |
155 | |
156 | return 0; | |
157 | } | |
158 | ||
159 | static void post_xfer(struct i2c_adapter *i2c_adap) | |
160 | { | |
161 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |
162 | struct radeon_device *rdev = i2c->dev->dev_private; | |
163 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
164 | uint32_t temp; | |
165 | ||
166 | /* unmask the gpio pins for software use */ | |
167 | temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; | |
168 | WREG32(rec->mask_clk_reg, temp); | |
169 | temp = RREG32(rec->mask_clk_reg); | |
170 | ||
171 | temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; | |
771fe6b9 JG |
172 | WREG32(rec->mask_data_reg, temp); |
173 | temp = RREG32(rec->mask_data_reg); | |
174 | } | |
175 | ||
176 | static int get_clock(void *i2c_priv) | |
177 | { | |
178 | struct radeon_i2c_chan *i2c = i2c_priv; | |
179 | struct radeon_device *rdev = i2c->dev->dev_private; | |
180 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
181 | uint32_t val; | |
182 | ||
9b9fe724 AD |
183 | /* read the value off the pin */ |
184 | val = RREG32(rec->y_clk_reg); | |
185 | val &= rec->y_clk_mask; | |
771fe6b9 JG |
186 | |
187 | return (val != 0); | |
188 | } | |
189 | ||
190 | ||
191 | static int get_data(void *i2c_priv) | |
192 | { | |
193 | struct radeon_i2c_chan *i2c = i2c_priv; | |
194 | struct radeon_device *rdev = i2c->dev->dev_private; | |
195 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
196 | uint32_t val; | |
197 | ||
9b9fe724 AD |
198 | /* read the value off the pin */ |
199 | val = RREG32(rec->y_data_reg); | |
200 | val &= rec->y_data_mask; | |
201 | ||
771fe6b9 JG |
202 | return (val != 0); |
203 | } | |
204 | ||
205 | static void set_clock(void *i2c_priv, int clock) | |
206 | { | |
207 | struct radeon_i2c_chan *i2c = i2c_priv; | |
208 | struct radeon_device *rdev = i2c->dev->dev_private; | |
209 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
210 | uint32_t val; | |
211 | ||
9b9fe724 AD |
212 | /* set pin direction */ |
213 | val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; | |
214 | val |= clock ? 0 : rec->en_clk_mask; | |
215 | WREG32(rec->en_clk_reg, val); | |
771fe6b9 JG |
216 | } |
217 | ||
218 | static void set_data(void *i2c_priv, int data) | |
219 | { | |
220 | struct radeon_i2c_chan *i2c = i2c_priv; | |
221 | struct radeon_device *rdev = i2c->dev->dev_private; | |
222 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
223 | uint32_t val; | |
224 | ||
9b9fe724 AD |
225 | /* set pin direction */ |
226 | val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; | |
227 | val |= data ? 0 : rec->en_data_mask; | |
228 | WREG32(rec->en_data_reg, val); | |
771fe6b9 JG |
229 | } |
230 | ||
ac1aade6 AD |
231 | /* hw i2c */ |
232 | ||
9dad76e8 AD |
233 | static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) |
234 | { | |
8807286e | 235 | u32 sclk = rdev->pm.current_sclk; |
9dad76e8 | 236 | u32 prescale = 0; |
96a4c8d5 AD |
237 | u32 nm; |
238 | u8 n, m, loop; | |
9dad76e8 AD |
239 | int i2c_clock; |
240 | ||
241 | switch (rdev->family) { | |
242 | case CHIP_R100: | |
243 | case CHIP_RV100: | |
244 | case CHIP_RS100: | |
245 | case CHIP_RV200: | |
246 | case CHIP_RS200: | |
247 | case CHIP_R200: | |
248 | case CHIP_RV250: | |
249 | case CHIP_RS300: | |
250 | case CHIP_RV280: | |
251 | case CHIP_R300: | |
252 | case CHIP_R350: | |
253 | case CHIP_RV350: | |
96a4c8d5 AD |
254 | i2c_clock = 60; |
255 | nm = (sclk * 10) / (i2c_clock * 4); | |
9dad76e8 | 256 | for (loop = 1; loop < 255; loop++) { |
96a4c8d5 | 257 | if ((nm / loop) < loop) |
9dad76e8 AD |
258 | break; |
259 | } | |
96a4c8d5 AD |
260 | n = loop - 1; |
261 | m = loop - 2; | |
262 | prescale = m | (n << 8); | |
9dad76e8 AD |
263 | break; |
264 | case CHIP_RV380: | |
265 | case CHIP_RS400: | |
266 | case CHIP_RS480: | |
267 | case CHIP_R420: | |
268 | case CHIP_R423: | |
269 | case CHIP_RV410: | |
9dad76e8 AD |
270 | prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; |
271 | break; | |
272 | case CHIP_RS600: | |
273 | case CHIP_RS690: | |
274 | case CHIP_RS740: | |
275 | /* todo */ | |
276 | break; | |
277 | case CHIP_RV515: | |
278 | case CHIP_R520: | |
279 | case CHIP_RV530: | |
280 | case CHIP_RV560: | |
281 | case CHIP_RV570: | |
282 | case CHIP_R580: | |
283 | i2c_clock = 50; | |
9dad76e8 AD |
284 | if (rdev->family == CHIP_R520) |
285 | prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); | |
286 | else | |
287 | prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; | |
288 | break; | |
289 | case CHIP_R600: | |
290 | case CHIP_RV610: | |
291 | case CHIP_RV630: | |
292 | case CHIP_RV670: | |
293 | /* todo */ | |
294 | break; | |
295 | case CHIP_RV620: | |
296 | case CHIP_RV635: | |
297 | case CHIP_RS780: | |
298 | case CHIP_RS880: | |
299 | case CHIP_RV770: | |
300 | case CHIP_RV730: | |
301 | case CHIP_RV710: | |
302 | case CHIP_RV740: | |
303 | /* todo */ | |
304 | break; | |
4c36b678 AD |
305 | case CHIP_CEDAR: |
306 | case CHIP_REDWOOD: | |
307 | case CHIP_JUNIPER: | |
308 | case CHIP_CYPRESS: | |
309 | case CHIP_HEMLOCK: | |
310 | /* todo */ | |
311 | break; | |
9dad76e8 AD |
312 | default: |
313 | DRM_ERROR("i2c: unhandled radeon chip\n"); | |
314 | break; | |
315 | } | |
316 | return prescale; | |
317 | } | |
318 | ||
319 | ||
40bacf16 AD |
320 | /* hw i2c engine for r1xx-4xx hardware |
321 | * hw can buffer up to 15 bytes | |
322 | */ | |
323 | static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, | |
324 | struct i2c_msg *msgs, int num) | |
325 | { | |
326 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |
327 | struct radeon_device *rdev = i2c->dev->dev_private; | |
328 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
329 | struct i2c_msg *p; | |
330 | int i, j, k, ret = num; | |
9dad76e8 | 331 | u32 prescale; |
40bacf16 AD |
332 | u32 i2c_cntl_0, i2c_cntl_1, i2c_data; |
333 | u32 tmp, reg; | |
334 | ||
335 | mutex_lock(&rdev->dc_hw_i2c_mutex); | |
57fcab62 AD |
336 | /* take the pm lock since we need a constant sclk */ |
337 | mutex_lock(&rdev->pm.mutex); | |
338 | ||
9dad76e8 | 339 | prescale = radeon_get_i2c_prescale(rdev); |
40bacf16 AD |
340 | |
341 | reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | | |
ae08819c | 342 | RADEON_I2C_DRIVE_EN | |
40bacf16 AD |
343 | RADEON_I2C_START | |
344 | RADEON_I2C_STOP | | |
345 | RADEON_I2C_GO); | |
346 | ||
347 | if (rdev->is_atom_bios) { | |
348 | tmp = RREG32(RADEON_BIOS_6_SCRATCH); | |
349 | WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); | |
350 | } | |
351 | ||
352 | if (rec->mm_i2c) { | |
353 | i2c_cntl_0 = RADEON_I2C_CNTL_0; | |
354 | i2c_cntl_1 = RADEON_I2C_CNTL_1; | |
355 | i2c_data = RADEON_I2C_DATA; | |
356 | } else { | |
357 | i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; | |
358 | i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; | |
359 | i2c_data = RADEON_DVI_I2C_DATA; | |
360 | ||
361 | switch (rdev->family) { | |
362 | case CHIP_R100: | |
363 | case CHIP_RV100: | |
364 | case CHIP_RS100: | |
365 | case CHIP_RV200: | |
366 | case CHIP_RS200: | |
367 | case CHIP_RS300: | |
368 | switch (rec->mask_clk_reg) { | |
369 | case RADEON_GPIO_DVI_DDC: | |
370 | /* no gpio select bit */ | |
371 | break; | |
372 | default: | |
373 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
374 | ret = -EINVAL; | |
375 | goto done; | |
376 | } | |
377 | break; | |
378 | case CHIP_R200: | |
379 | /* only bit 4 on r200 */ | |
380 | switch (rec->mask_clk_reg) { | |
381 | case RADEON_GPIO_DVI_DDC: | |
382 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); | |
383 | break; | |
384 | case RADEON_GPIO_MONID: | |
385 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); | |
386 | break; | |
387 | default: | |
388 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
389 | ret = -EINVAL; | |
390 | goto done; | |
391 | } | |
392 | break; | |
393 | case CHIP_RV250: | |
394 | case CHIP_RV280: | |
395 | /* bits 3 and 4 */ | |
396 | switch (rec->mask_clk_reg) { | |
397 | case RADEON_GPIO_DVI_DDC: | |
398 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); | |
399 | break; | |
400 | case RADEON_GPIO_VGA_DDC: | |
401 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); | |
402 | break; | |
403 | case RADEON_GPIO_CRT2_DDC: | |
404 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); | |
405 | break; | |
406 | default: | |
407 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
408 | ret = -EINVAL; | |
409 | goto done; | |
410 | } | |
411 | break; | |
412 | case CHIP_R300: | |
413 | case CHIP_R350: | |
414 | /* only bit 4 on r300/r350 */ | |
415 | switch (rec->mask_clk_reg) { | |
416 | case RADEON_GPIO_VGA_DDC: | |
417 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); | |
418 | break; | |
419 | case RADEON_GPIO_DVI_DDC: | |
420 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); | |
421 | break; | |
422 | default: | |
423 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
424 | ret = -EINVAL; | |
425 | goto done; | |
426 | } | |
427 | break; | |
428 | case CHIP_RV350: | |
429 | case CHIP_RV380: | |
430 | case CHIP_R420: | |
431 | case CHIP_R423: | |
432 | case CHIP_RV410: | |
433 | case CHIP_RS400: | |
434 | case CHIP_RS480: | |
435 | /* bits 3 and 4 */ | |
436 | switch (rec->mask_clk_reg) { | |
437 | case RADEON_GPIO_VGA_DDC: | |
438 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); | |
439 | break; | |
440 | case RADEON_GPIO_DVI_DDC: | |
441 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); | |
442 | break; | |
443 | case RADEON_GPIO_MONID: | |
444 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); | |
445 | break; | |
446 | default: | |
447 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
448 | ret = -EINVAL; | |
449 | goto done; | |
450 | } | |
451 | break; | |
452 | default: | |
453 | DRM_ERROR("unsupported asic\n"); | |
454 | ret = -EINVAL; | |
455 | goto done; | |
456 | break; | |
457 | } | |
458 | } | |
459 | ||
460 | /* check for bus probe */ | |
461 | p = &msgs[0]; | |
462 | if ((num == 1) && (p->len == 0)) { | |
463 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE | | |
464 | RADEON_I2C_NACK | | |
465 | RADEON_I2C_HALT | | |
466 | RADEON_I2C_SOFT_RST)); | |
467 | WREG32(i2c_data, (p->addr << 1) & 0xff); | |
468 | WREG32(i2c_data, 0); | |
469 | WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | | |
470 | (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | | |
471 | RADEON_I2C_EN | | |
472 | (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); | |
473 | WREG32(i2c_cntl_0, reg); | |
474 | for (k = 0; k < 32; k++) { | |
475 | udelay(10); | |
476 | tmp = RREG32(i2c_cntl_0); | |
477 | if (tmp & RADEON_I2C_GO) | |
478 | continue; | |
479 | tmp = RREG32(i2c_cntl_0); | |
480 | if (tmp & RADEON_I2C_DONE) | |
481 | break; | |
482 | else { | |
483 | DRM_DEBUG("i2c write error 0x%08x\n", tmp); | |
484 | WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); | |
485 | ret = -EIO; | |
486 | goto done; | |
487 | } | |
488 | } | |
489 | goto done; | |
490 | } | |
491 | ||
492 | for (i = 0; i < num; i++) { | |
493 | p = &msgs[i]; | |
494 | for (j = 0; j < p->len; j++) { | |
495 | if (p->flags & I2C_M_RD) { | |
496 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE | | |
497 | RADEON_I2C_NACK | | |
498 | RADEON_I2C_HALT | | |
499 | RADEON_I2C_SOFT_RST)); | |
500 | WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); | |
501 | WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | | |
502 | (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | | |
503 | RADEON_I2C_EN | | |
504 | (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); | |
505 | WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); | |
506 | for (k = 0; k < 32; k++) { | |
507 | udelay(10); | |
508 | tmp = RREG32(i2c_cntl_0); | |
509 | if (tmp & RADEON_I2C_GO) | |
510 | continue; | |
511 | tmp = RREG32(i2c_cntl_0); | |
512 | if (tmp & RADEON_I2C_DONE) | |
513 | break; | |
514 | else { | |
515 | DRM_DEBUG("i2c read error 0x%08x\n", tmp); | |
516 | WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); | |
517 | ret = -EIO; | |
518 | goto done; | |
519 | } | |
520 | } | |
521 | p->buf[j] = RREG32(i2c_data) & 0xff; | |
522 | } else { | |
523 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE | | |
524 | RADEON_I2C_NACK | | |
525 | RADEON_I2C_HALT | | |
526 | RADEON_I2C_SOFT_RST)); | |
527 | WREG32(i2c_data, (p->addr << 1) & 0xff); | |
528 | WREG32(i2c_data, p->buf[j]); | |
529 | WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | | |
530 | (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | | |
531 | RADEON_I2C_EN | | |
532 | (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); | |
533 | WREG32(i2c_cntl_0, reg); | |
534 | for (k = 0; k < 32; k++) { | |
535 | udelay(10); | |
536 | tmp = RREG32(i2c_cntl_0); | |
537 | if (tmp & RADEON_I2C_GO) | |
538 | continue; | |
539 | tmp = RREG32(i2c_cntl_0); | |
540 | if (tmp & RADEON_I2C_DONE) | |
541 | break; | |
542 | else { | |
543 | DRM_DEBUG("i2c write error 0x%08x\n", tmp); | |
544 | WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); | |
545 | ret = -EIO; | |
546 | goto done; | |
547 | } | |
548 | } | |
549 | } | |
550 | } | |
551 | } | |
552 | ||
553 | done: | |
554 | WREG32(i2c_cntl_0, 0); | |
555 | WREG32(i2c_cntl_1, 0); | |
556 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE | | |
557 | RADEON_I2C_NACK | | |
558 | RADEON_I2C_HALT | | |
559 | RADEON_I2C_SOFT_RST)); | |
560 | ||
561 | if (rdev->is_atom_bios) { | |
562 | tmp = RREG32(RADEON_BIOS_6_SCRATCH); | |
563 | tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; | |
564 | WREG32(RADEON_BIOS_6_SCRATCH, tmp); | |
565 | } | |
566 | ||
57fcab62 | 567 | mutex_unlock(&rdev->pm.mutex); |
40bacf16 AD |
568 | mutex_unlock(&rdev->dc_hw_i2c_mutex); |
569 | ||
570 | return ret; | |
571 | } | |
572 | ||
573 | /* hw i2c engine for r5xx hardware | |
574 | * hw can buffer up to 15 bytes | |
575 | */ | |
576 | static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, | |
577 | struct i2c_msg *msgs, int num) | |
578 | { | |
579 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |
580 | struct radeon_device *rdev = i2c->dev->dev_private; | |
581 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
582 | struct i2c_msg *p; | |
40bacf16 | 583 | int i, j, remaining, current_count, buffer_offset, ret = num; |
9dad76e8 | 584 | u32 prescale; |
40bacf16 AD |
585 | u32 tmp, reg; |
586 | u32 saved1, saved2; | |
587 | ||
588 | mutex_lock(&rdev->dc_hw_i2c_mutex); | |
57fcab62 AD |
589 | /* take the pm lock since we need a constant sclk */ |
590 | mutex_lock(&rdev->pm.mutex); | |
591 | ||
9dad76e8 | 592 | prescale = radeon_get_i2c_prescale(rdev); |
40bacf16 AD |
593 | |
594 | /* clear gpio mask bits */ | |
595 | tmp = RREG32(rec->mask_clk_reg); | |
596 | tmp &= ~rec->mask_clk_mask; | |
597 | WREG32(rec->mask_clk_reg, tmp); | |
598 | tmp = RREG32(rec->mask_clk_reg); | |
599 | ||
600 | tmp = RREG32(rec->mask_data_reg); | |
601 | tmp &= ~rec->mask_data_mask; | |
602 | WREG32(rec->mask_data_reg, tmp); | |
603 | tmp = RREG32(rec->mask_data_reg); | |
604 | ||
605 | /* clear pin values */ | |
606 | tmp = RREG32(rec->a_clk_reg); | |
607 | tmp &= ~rec->a_clk_mask; | |
608 | WREG32(rec->a_clk_reg, tmp); | |
609 | tmp = RREG32(rec->a_clk_reg); | |
610 | ||
611 | tmp = RREG32(rec->a_data_reg); | |
612 | tmp &= ~rec->a_data_mask; | |
613 | WREG32(rec->a_data_reg, tmp); | |
614 | tmp = RREG32(rec->a_data_reg); | |
615 | ||
616 | /* set the pins to input */ | |
617 | tmp = RREG32(rec->en_clk_reg); | |
618 | tmp &= ~rec->en_clk_mask; | |
619 | WREG32(rec->en_clk_reg, tmp); | |
620 | tmp = RREG32(rec->en_clk_reg); | |
621 | ||
622 | tmp = RREG32(rec->en_data_reg); | |
623 | tmp &= ~rec->en_data_mask; | |
624 | WREG32(rec->en_data_reg, tmp); | |
625 | tmp = RREG32(rec->en_data_reg); | |
626 | ||
627 | /* */ | |
628 | tmp = RREG32(RADEON_BIOS_6_SCRATCH); | |
629 | WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); | |
630 | saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); | |
631 | saved2 = RREG32(0x494); | |
632 | WREG32(0x494, saved2 | 0x1); | |
633 | ||
634 | WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); | |
635 | for (i = 0; i < 50; i++) { | |
636 | udelay(1); | |
637 | if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) | |
638 | break; | |
639 | } | |
640 | if (i == 50) { | |
641 | DRM_ERROR("failed to get i2c bus\n"); | |
642 | ret = -EBUSY; | |
643 | goto done; | |
644 | } | |
645 | ||
40bacf16 AD |
646 | reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; |
647 | switch (rec->mask_clk_reg) { | |
648 | case AVIVO_DC_GPIO_DDC1_MASK: | |
649 | reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); | |
650 | break; | |
651 | case AVIVO_DC_GPIO_DDC2_MASK: | |
652 | reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); | |
653 | break; | |
654 | case AVIVO_DC_GPIO_DDC3_MASK: | |
655 | reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); | |
656 | break; | |
657 | default: | |
658 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
659 | ret = -EINVAL; | |
660 | goto done; | |
661 | } | |
662 | ||
663 | /* check for bus probe */ | |
664 | p = &msgs[0]; | |
665 | if ((num == 1) && (p->len == 0)) { | |
666 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | | |
667 | AVIVO_DC_I2C_NACK | | |
668 | AVIVO_DC_I2C_HALT)); | |
669 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); | |
670 | udelay(1); | |
671 | WREG32(AVIVO_DC_I2C_RESET, 0); | |
672 | ||
673 | WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); | |
674 | WREG32(AVIVO_DC_I2C_DATA, 0); | |
675 | ||
676 | WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); | |
677 | WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | | |
678 | AVIVO_DC_I2C_DATA_COUNT(1) | | |
679 | (prescale << 16))); | |
680 | WREG32(AVIVO_DC_I2C_CONTROL1, reg); | |
681 | WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); | |
682 | for (j = 0; j < 200; j++) { | |
683 | udelay(50); | |
684 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
685 | if (tmp & AVIVO_DC_I2C_GO) | |
686 | continue; | |
687 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
688 | if (tmp & AVIVO_DC_I2C_DONE) | |
689 | break; | |
690 | else { | |
691 | DRM_DEBUG("i2c write error 0x%08x\n", tmp); | |
692 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); | |
693 | ret = -EIO; | |
694 | goto done; | |
695 | } | |
696 | } | |
697 | goto done; | |
698 | } | |
699 | ||
700 | for (i = 0; i < num; i++) { | |
701 | p = &msgs[i]; | |
702 | remaining = p->len; | |
703 | buffer_offset = 0; | |
704 | if (p->flags & I2C_M_RD) { | |
705 | while (remaining) { | |
706 | if (remaining > 15) | |
707 | current_count = 15; | |
708 | else | |
709 | current_count = remaining; | |
710 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | | |
711 | AVIVO_DC_I2C_NACK | | |
712 | AVIVO_DC_I2C_HALT)); | |
713 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); | |
714 | udelay(1); | |
715 | WREG32(AVIVO_DC_I2C_RESET, 0); | |
716 | ||
717 | WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); | |
718 | WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); | |
719 | WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | | |
720 | AVIVO_DC_I2C_DATA_COUNT(current_count) | | |
721 | (prescale << 16))); | |
722 | WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); | |
723 | WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); | |
724 | for (j = 0; j < 200; j++) { | |
725 | udelay(50); | |
726 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
727 | if (tmp & AVIVO_DC_I2C_GO) | |
728 | continue; | |
729 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
730 | if (tmp & AVIVO_DC_I2C_DONE) | |
731 | break; | |
732 | else { | |
733 | DRM_DEBUG("i2c read error 0x%08x\n", tmp); | |
734 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); | |
735 | ret = -EIO; | |
736 | goto done; | |
737 | } | |
738 | } | |
739 | for (j = 0; j < current_count; j++) | |
740 | p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; | |
741 | remaining -= current_count; | |
742 | buffer_offset += current_count; | |
743 | } | |
744 | } else { | |
745 | while (remaining) { | |
746 | if (remaining > 15) | |
747 | current_count = 15; | |
748 | else | |
749 | current_count = remaining; | |
750 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | | |
751 | AVIVO_DC_I2C_NACK | | |
752 | AVIVO_DC_I2C_HALT)); | |
753 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); | |
754 | udelay(1); | |
755 | WREG32(AVIVO_DC_I2C_RESET, 0); | |
756 | ||
757 | WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); | |
758 | for (j = 0; j < current_count; j++) | |
759 | WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); | |
760 | ||
761 | WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); | |
762 | WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | | |
763 | AVIVO_DC_I2C_DATA_COUNT(current_count) | | |
764 | (prescale << 16))); | |
765 | WREG32(AVIVO_DC_I2C_CONTROL1, reg); | |
766 | WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); | |
767 | for (j = 0; j < 200; j++) { | |
768 | udelay(50); | |
769 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
770 | if (tmp & AVIVO_DC_I2C_GO) | |
771 | continue; | |
772 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
773 | if (tmp & AVIVO_DC_I2C_DONE) | |
774 | break; | |
775 | else { | |
776 | DRM_DEBUG("i2c write error 0x%08x\n", tmp); | |
777 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); | |
778 | ret = -EIO; | |
779 | goto done; | |
780 | } | |
781 | } | |
782 | remaining -= current_count; | |
783 | buffer_offset += current_count; | |
784 | } | |
785 | } | |
786 | } | |
787 | ||
788 | done: | |
789 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | | |
790 | AVIVO_DC_I2C_NACK | | |
791 | AVIVO_DC_I2C_HALT)); | |
792 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); | |
793 | udelay(1); | |
794 | WREG32(AVIVO_DC_I2C_RESET, 0); | |
795 | ||
796 | WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); | |
797 | WREG32(AVIVO_DC_I2C_CONTROL1, saved1); | |
798 | WREG32(0x494, saved2); | |
799 | tmp = RREG32(RADEON_BIOS_6_SCRATCH); | |
800 | tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; | |
801 | WREG32(RADEON_BIOS_6_SCRATCH, tmp); | |
802 | ||
57fcab62 | 803 | mutex_unlock(&rdev->pm.mutex); |
40bacf16 AD |
804 | mutex_unlock(&rdev->dc_hw_i2c_mutex); |
805 | ||
806 | return ret; | |
807 | } | |
808 | ||
ac1aade6 | 809 | static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap, |
40bacf16 | 810 | struct i2c_msg *msgs, int num) |
40bacf16 AD |
811 | { |
812 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |
813 | struct radeon_device *rdev = i2c->dev->dev_private; | |
814 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
ac1aade6 | 815 | int ret = 0; |
40bacf16 AD |
816 | |
817 | switch (rdev->family) { | |
818 | case CHIP_R100: | |
819 | case CHIP_RV100: | |
820 | case CHIP_RS100: | |
821 | case CHIP_RV200: | |
822 | case CHIP_RS200: | |
823 | case CHIP_R200: | |
824 | case CHIP_RV250: | |
825 | case CHIP_RS300: | |
826 | case CHIP_RV280: | |
827 | case CHIP_R300: | |
828 | case CHIP_R350: | |
829 | case CHIP_RV350: | |
830 | case CHIP_RV380: | |
831 | case CHIP_R420: | |
832 | case CHIP_R423: | |
833 | case CHIP_RV410: | |
834 | case CHIP_RS400: | |
835 | case CHIP_RS480: | |
ac1aade6 | 836 | ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); |
40bacf16 AD |
837 | break; |
838 | case CHIP_RS600: | |
839 | case CHIP_RS690: | |
840 | case CHIP_RS740: | |
841 | /* XXX fill in hw i2c implementation */ | |
40bacf16 AD |
842 | break; |
843 | case CHIP_RV515: | |
844 | case CHIP_R520: | |
845 | case CHIP_RV530: | |
846 | case CHIP_RV560: | |
847 | case CHIP_RV570: | |
848 | case CHIP_R580: | |
ac1aade6 AD |
849 | if (rec->mm_i2c) |
850 | ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); | |
851 | else | |
852 | ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); | |
40bacf16 AD |
853 | break; |
854 | case CHIP_R600: | |
855 | case CHIP_RV610: | |
856 | case CHIP_RV630: | |
857 | case CHIP_RV670: | |
858 | /* XXX fill in hw i2c implementation */ | |
40bacf16 AD |
859 | break; |
860 | case CHIP_RV620: | |
861 | case CHIP_RV635: | |
862 | case CHIP_RS780: | |
863 | case CHIP_RS880: | |
864 | case CHIP_RV770: | |
865 | case CHIP_RV730: | |
866 | case CHIP_RV710: | |
867 | case CHIP_RV740: | |
868 | /* XXX fill in hw i2c implementation */ | |
40bacf16 | 869 | break; |
4c36b678 AD |
870 | case CHIP_CEDAR: |
871 | case CHIP_REDWOOD: | |
872 | case CHIP_JUNIPER: | |
873 | case CHIP_CYPRESS: | |
874 | case CHIP_HEMLOCK: | |
875 | /* XXX fill in hw i2c implementation */ | |
4c36b678 | 876 | break; |
40bacf16 AD |
877 | default: |
878 | DRM_ERROR("i2c: unhandled radeon chip\n"); | |
879 | ret = -EIO; | |
880 | break; | |
881 | } | |
882 | ||
883 | return ret; | |
884 | } | |
885 | ||
ac1aade6 | 886 | static u32 radeon_hw_i2c_func(struct i2c_adapter *adap) |
5a6f98f5 AD |
887 | { |
888 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
889 | } | |
890 | ||
891 | static const struct i2c_algorithm radeon_i2c_algo = { | |
ac1aade6 AD |
892 | .master_xfer = radeon_hw_i2c_xfer, |
893 | .functionality = radeon_hw_i2c_func, | |
5a6f98f5 AD |
894 | }; |
895 | ||
30388c6e AD |
896 | static const struct i2c_algorithm radeon_atom_i2c_algo = { |
897 | .master_xfer = radeon_atom_hw_i2c_xfer, | |
898 | .functionality = radeon_atom_hw_i2c_func, | |
899 | }; | |
900 | ||
771fe6b9 | 901 | struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
ab1e9ea0 AD |
902 | struct radeon_i2c_bus_rec *rec, |
903 | const char *name) | |
771fe6b9 | 904 | { |
ac1aade6 | 905 | struct radeon_device *rdev = dev->dev_private; |
771fe6b9 JG |
906 | struct radeon_i2c_chan *i2c; |
907 | int ret; | |
908 | ||
46783150 AD |
909 | /* don't add the mm_i2c bus unless hw_i2c is enabled */ |
910 | if (rec->mm_i2c && (radeon_hw_i2c == 0)) | |
911 | return NULL; | |
912 | ||
9a298b2a | 913 | i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); |
771fe6b9 JG |
914 | if (i2c == NULL) |
915 | return NULL; | |
916 | ||
40bacf16 | 917 | i2c->rec = *rec; |
5a6f98f5 | 918 | i2c->adapter.owner = THIS_MODULE; |
87d7a1f9 | 919 | i2c->adapter.class = I2C_CLASS_DDC; |
1ffd57c1 | 920 | i2c->adapter.dev.parent = &dev->pdev->dev; |
ac1aade6 | 921 | i2c->dev = dev; |
5a6f98f5 | 922 | i2c_set_adapdata(&i2c->adapter, i2c); |
e2b0a8e1 AD |
923 | if (rec->mm_i2c || |
924 | (rec->hw_capable && | |
925 | radeon_hw_i2c && | |
926 | ((rdev->family <= CHIP_RS480) || | |
927 | ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { | |
ac1aade6 | 928 | /* set the radeon hw i2c adapter */ |
164bcb94 AD |
929 | snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), |
930 | "Radeon i2c hw bus %s", name); | |
ac1aade6 AD |
931 | i2c->adapter.algo = &radeon_i2c_algo; |
932 | ret = i2c_add_adapter(&i2c->adapter); | |
933 | if (ret) { | |
934 | DRM_ERROR("Failed to register hw i2c %s\n", name); | |
935 | goto out_free; | |
936 | } | |
30388c6e AD |
937 | } else if (rec->hw_capable && |
938 | radeon_hw_i2c && | |
939 | ASIC_IS_DCE3(rdev)) { | |
940 | /* hw i2c using atom */ | |
941 | snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), | |
942 | "Radeon i2c hw bus %s", name); | |
943 | i2c->adapter.algo = &radeon_atom_i2c_algo; | |
944 | ret = i2c_add_adapter(&i2c->adapter); | |
945 | if (ret) { | |
946 | DRM_ERROR("Failed to register hw i2c %s\n", name); | |
947 | goto out_free; | |
948 | } | |
ac1aade6 AD |
949 | } else { |
950 | /* set the radeon bit adapter */ | |
164bcb94 AD |
951 | snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), |
952 | "Radeon i2c bit bus %s", name); | |
ac1aade6 AD |
953 | i2c->adapter.algo_data = &i2c->algo.bit; |
954 | i2c->algo.bit.pre_xfer = pre_xfer; | |
955 | i2c->algo.bit.post_xfer = post_xfer; | |
956 | i2c->algo.bit.setsda = set_data; | |
957 | i2c->algo.bit.setscl = set_clock; | |
958 | i2c->algo.bit.getsda = get_data; | |
959 | i2c->algo.bit.getscl = get_clock; | |
1849ecb2 | 960 | i2c->algo.bit.udelay = 10; |
90489557 | 961 | i2c->algo.bit.timeout = usecs_to_jiffies(2200); /* from VESA */ |
ac1aade6 AD |
962 | i2c->algo.bit.data = i2c; |
963 | ret = i2c_bit_add_bus(&i2c->adapter); | |
964 | if (ret) { | |
965 | DRM_ERROR("Failed to register bit i2c %s\n", name); | |
966 | goto out_free; | |
967 | } | |
771fe6b9 JG |
968 | } |
969 | ||
970 | return i2c; | |
971 | out_free: | |
9a298b2a | 972 | kfree(i2c); |
771fe6b9 JG |
973 | return NULL; |
974 | ||
975 | } | |
976 | ||
746c1aa4 | 977 | struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, |
6a93cb25 AD |
978 | struct radeon_i2c_bus_rec *rec, |
979 | const char *name) | |
746c1aa4 DA |
980 | { |
981 | struct radeon_i2c_chan *i2c; | |
982 | int ret; | |
983 | ||
984 | i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); | |
985 | if (i2c == NULL) | |
986 | return NULL; | |
987 | ||
6a93cb25 | 988 | i2c->rec = *rec; |
746c1aa4 | 989 | i2c->adapter.owner = THIS_MODULE; |
87d7a1f9 | 990 | i2c->adapter.class = I2C_CLASS_DDC; |
3f7e3632 | 991 | i2c->adapter.dev.parent = &dev->pdev->dev; |
746c1aa4 | 992 | i2c->dev = dev; |
164bcb94 AD |
993 | snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), |
994 | "Radeon aux bus %s", name); | |
746c1aa4 DA |
995 | i2c_set_adapdata(&i2c->adapter, i2c); |
996 | i2c->adapter.algo_data = &i2c->algo.dp; | |
997 | i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch; | |
998 | i2c->algo.dp.address = 0; | |
999 | ret = i2c_dp_aux_add_bus(&i2c->adapter); | |
1000 | if (ret) { | |
1001 | DRM_INFO("Failed to register i2c %s\n", name); | |
1002 | goto out_free; | |
1003 | } | |
1004 | ||
1005 | return i2c; | |
1006 | out_free: | |
1007 | kfree(i2c); | |
1008 | return NULL; | |
1009 | ||
1010 | } | |
1011 | ||
771fe6b9 | 1012 | void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) |
5a6f98f5 AD |
1013 | { |
1014 | if (!i2c) | |
1015 | return; | |
771fe6b9 | 1016 | i2c_del_adapter(&i2c->adapter); |
9a298b2a | 1017 | kfree(i2c); |
771fe6b9 JG |
1018 | } |
1019 | ||
f376b94f AD |
1020 | /* Add the default buses */ |
1021 | void radeon_i2c_init(struct radeon_device *rdev) | |
1022 | { | |
d1951782 AD |
1023 | if (radeon_hw_i2c) |
1024 | DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); | |
1025 | ||
f376b94f AD |
1026 | if (rdev->is_atom_bios) |
1027 | radeon_atombios_i2c_init(rdev); | |
1028 | else | |
1029 | radeon_combios_i2c_init(rdev); | |
1030 | } | |
1031 | ||
1032 | /* remove all the buses */ | |
1033 | void radeon_i2c_fini(struct radeon_device *rdev) | |
1034 | { | |
1035 | int i; | |
1036 | ||
1037 | for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { | |
1038 | if (rdev->i2c_bus[i]) { | |
1039 | radeon_i2c_destroy(rdev->i2c_bus[i]); | |
1040 | rdev->i2c_bus[i] = NULL; | |
1041 | } | |
1042 | } | |
1043 | } | |
1044 | ||
1045 | /* Add additional buses */ | |
1046 | void radeon_i2c_add(struct radeon_device *rdev, | |
1047 | struct radeon_i2c_bus_rec *rec, | |
1048 | const char *name) | |
1049 | { | |
1050 | struct drm_device *dev = rdev->ddev; | |
1051 | int i; | |
1052 | ||
1053 | for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { | |
1054 | if (!rdev->i2c_bus[i]) { | |
1055 | rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); | |
1056 | return; | |
1057 | } | |
1058 | } | |
1059 | } | |
1060 | ||
1061 | /* looks up bus based on id */ | |
1062 | struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, | |
1063 | struct radeon_i2c_bus_rec *i2c_bus) | |
1064 | { | |
1065 | int i; | |
1066 | ||
1067 | for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { | |
1068 | if (rdev->i2c_bus[i] && | |
1069 | (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { | |
1070 | return rdev->i2c_bus[i]; | |
1071 | } | |
1072 | } | |
1073 | return NULL; | |
1074 | } | |
1075 | ||
771fe6b9 JG |
1076 | struct drm_encoder *radeon_best_encoder(struct drm_connector *connector) |
1077 | { | |
1078 | return NULL; | |
1079 | } | |
fcec570b | 1080 | |
5a6f98f5 AD |
1081 | void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, |
1082 | u8 slave_addr, | |
1083 | u8 addr, | |
1084 | u8 *val) | |
fcec570b AD |
1085 | { |
1086 | u8 out_buf[2]; | |
1087 | u8 in_buf[2]; | |
1088 | struct i2c_msg msgs[] = { | |
1089 | { | |
1090 | .addr = slave_addr, | |
1091 | .flags = 0, | |
1092 | .len = 1, | |
1093 | .buf = out_buf, | |
1094 | }, | |
1095 | { | |
1096 | .addr = slave_addr, | |
1097 | .flags = I2C_M_RD, | |
1098 | .len = 1, | |
1099 | .buf = in_buf, | |
1100 | } | |
1101 | }; | |
1102 | ||
1103 | out_buf[0] = addr; | |
1104 | out_buf[1] = 0; | |
1105 | ||
1106 | if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { | |
1107 | *val = in_buf[0]; | |
1108 | DRM_DEBUG("val = 0x%02x\n", *val); | |
1109 | } else { | |
d4864d60 | 1110 | DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", |
fcec570b AD |
1111 | addr, *val); |
1112 | } | |
1113 | } | |
1114 | ||
5a6f98f5 AD |
1115 | void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, |
1116 | u8 slave_addr, | |
1117 | u8 addr, | |
1118 | u8 val) | |
fcec570b AD |
1119 | { |
1120 | uint8_t out_buf[2]; | |
1121 | struct i2c_msg msg = { | |
1122 | .addr = slave_addr, | |
1123 | .flags = 0, | |
1124 | .len = 2, | |
1125 | .buf = out_buf, | |
1126 | }; | |
1127 | ||
1128 | out_buf[0] = addr; | |
1129 | out_buf[1] = val; | |
1130 | ||
1131 | if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) | |
d4864d60 | 1132 | DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", |
fcec570b AD |
1133 | addr, val); |
1134 | } | |
1135 | ||
fb939dfc AD |
1136 | /* ddc router switching */ |
1137 | void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) | |
26b5bc98 AD |
1138 | { |
1139 | u8 val; | |
1140 | ||
fb939dfc | 1141 | if (!radeon_connector->router.ddc_valid) |
26b5bc98 AD |
1142 | return; |
1143 | ||
a70882aa AD |
1144 | if (!radeon_connector->router_bus) |
1145 | return; | |
1146 | ||
26b5bc98 AD |
1147 | radeon_i2c_get_byte(radeon_connector->router_bus, |
1148 | radeon_connector->router.i2c_addr, | |
1149 | 0x3, &val); | |
bdd91b2b | 1150 | val &= ~radeon_connector->router.ddc_mux_control_pin; |
26b5bc98 AD |
1151 | radeon_i2c_put_byte(radeon_connector->router_bus, |
1152 | radeon_connector->router.i2c_addr, | |
1153 | 0x3, val); | |
1154 | radeon_i2c_get_byte(radeon_connector->router_bus, | |
1155 | radeon_connector->router.i2c_addr, | |
1156 | 0x1, &val); | |
bdd91b2b | 1157 | val &= ~radeon_connector->router.ddc_mux_control_pin; |
fb939dfc AD |
1158 | val |= radeon_connector->router.ddc_mux_state; |
1159 | radeon_i2c_put_byte(radeon_connector->router_bus, | |
1160 | radeon_connector->router.i2c_addr, | |
1161 | 0x1, val); | |
1162 | } | |
1163 | ||
1164 | /* clock/data router switching */ | |
1165 | void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) | |
1166 | { | |
1167 | u8 val; | |
1168 | ||
1169 | if (!radeon_connector->router.cd_valid) | |
1170 | return; | |
1171 | ||
a70882aa AD |
1172 | if (!radeon_connector->router_bus) |
1173 | return; | |
1174 | ||
fb939dfc AD |
1175 | radeon_i2c_get_byte(radeon_connector->router_bus, |
1176 | radeon_connector->router.i2c_addr, | |
1177 | 0x3, &val); | |
bdd91b2b | 1178 | val &= ~radeon_connector->router.cd_mux_control_pin; |
fb939dfc AD |
1179 | radeon_i2c_put_byte(radeon_connector->router_bus, |
1180 | radeon_connector->router.i2c_addr, | |
1181 | 0x3, val); | |
1182 | radeon_i2c_get_byte(radeon_connector->router_bus, | |
1183 | radeon_connector->router.i2c_addr, | |
1184 | 0x1, &val); | |
bdd91b2b | 1185 | val &= ~radeon_connector->router.cd_mux_control_pin; |
fb939dfc | 1186 | val |= radeon_connector->router.cd_mux_state; |
26b5bc98 AD |
1187 | radeon_i2c_put_byte(radeon_connector->router_bus, |
1188 | radeon_connector->router.i2c_addr, | |
1189 | 0x1, val); | |
1190 | } | |
1191 |