Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include "drmP.h" | |
eb1f8e4f | 29 | #include "drm_crtc_helper.h" |
771fe6b9 JG |
30 | #include "radeon_drm.h" |
31 | #include "radeon_reg.h" | |
771fe6b9 JG |
32 | #include "radeon.h" |
33 | #include "atom.h" | |
34 | ||
771fe6b9 JG |
35 | irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS) |
36 | { | |
37 | struct drm_device *dev = (struct drm_device *) arg; | |
38 | struct radeon_device *rdev = dev->dev_private; | |
39 | ||
40 | return radeon_irq_process(rdev); | |
41 | } | |
42 | ||
d4877cf2 AD |
43 | /* |
44 | * Handle hotplug events outside the interrupt handler proper. | |
45 | */ | |
46 | static void radeon_hotplug_work_func(struct work_struct *work) | |
47 | { | |
48 | struct radeon_device *rdev = container_of(work, struct radeon_device, | |
49 | hotplug_work); | |
50 | struct drm_device *dev = rdev->ddev; | |
51 | struct drm_mode_config *mode_config = &dev->mode_config; | |
52 | struct drm_connector *connector; | |
53 | ||
54 | if (mode_config->num_connector) { | |
55 | list_for_each_entry(connector, &mode_config->connector_list, head) | |
56 | radeon_connector_hotplug(connector); | |
57 | } | |
58 | /* Just fire off a uevent and let userspace tell us what to do */ | |
eb1f8e4f | 59 | drm_helper_hpd_irq_event(dev); |
d4877cf2 AD |
60 | } |
61 | ||
771fe6b9 JG |
62 | void radeon_driver_irq_preinstall_kms(struct drm_device *dev) |
63 | { | |
64 | struct radeon_device *rdev = dev->dev_private; | |
65 | unsigned i; | |
66 | ||
d4877cf2 AD |
67 | INIT_WORK(&rdev->hotplug_work, radeon_hotplug_work_func); |
68 | ||
771fe6b9 JG |
69 | /* Disable *all* interrupts */ |
70 | rdev->irq.sw_int = false; | |
2031f77c | 71 | rdev->irq.gui_idle = false; |
9e7b414e | 72 | for (i = 0; i < rdev->num_crtc; i++) |
771fe6b9 | 73 | rdev->irq.crtc_vblank_int[i] = false; |
9e7b414e AD |
74 | for (i = 0; i < 6; i++) |
75 | rdev->irq.hpd[i] = false; | |
771fe6b9 JG |
76 | radeon_irq_set(rdev); |
77 | /* Clear bits */ | |
78 | radeon_irq_process(rdev); | |
79 | } | |
80 | ||
81 | int radeon_driver_irq_postinstall_kms(struct drm_device *dev) | |
82 | { | |
83 | struct radeon_device *rdev = dev->dev_private; | |
84 | ||
85 | dev->max_vblank_count = 0x001fffff; | |
86 | rdev->irq.sw_int = true; | |
87 | radeon_irq_set(rdev); | |
88 | return 0; | |
89 | } | |
90 | ||
91 | void radeon_driver_irq_uninstall_kms(struct drm_device *dev) | |
92 | { | |
93 | struct radeon_device *rdev = dev->dev_private; | |
94 | unsigned i; | |
95 | ||
96 | if (rdev == NULL) { | |
97 | return; | |
98 | } | |
99 | /* Disable *all* interrupts */ | |
100 | rdev->irq.sw_int = false; | |
2031f77c | 101 | rdev->irq.gui_idle = false; |
9e7b414e | 102 | for (i = 0; i < rdev->num_crtc; i++) |
771fe6b9 | 103 | rdev->irq.crtc_vblank_int[i] = false; |
9e7b414e | 104 | for (i = 0; i < 6; i++) |
003e69f9 | 105 | rdev->irq.hpd[i] = false; |
771fe6b9 JG |
106 | radeon_irq_set(rdev); |
107 | } | |
108 | ||
109 | int radeon_irq_kms_init(struct radeon_device *rdev) | |
110 | { | |
111 | int r = 0; | |
112 | ||
1614f8b1 | 113 | spin_lock_init(&rdev->irq.sw_lock); |
9e7b414e | 114 | r = drm_vblank_init(rdev->ddev, rdev->num_crtc); |
771fe6b9 JG |
115 | if (r) { |
116 | return r; | |
117 | } | |
3e5cb98d AD |
118 | /* enable msi */ |
119 | rdev->msi_enabled = 0; | |
c414a117 AD |
120 | /* MSIs don't seem to work reliably on all IGP |
121 | * chips. Disable MSI on them for now. | |
d8f60cfc AD |
122 | */ |
123 | if ((rdev->family >= CHIP_RV380) && | |
da7be684 AD |
124 | (!(rdev->flags & RADEON_IS_IGP)) && |
125 | (!(rdev->flags & RADEON_IS_AGP))) { | |
3e5cb98d | 126 | int ret = pci_enable_msi(rdev->pdev); |
d8f60cfc | 127 | if (!ret) { |
3e5cb98d | 128 | rdev->msi_enabled = 1; |
da7be684 | 129 | dev_info(rdev->dev, "radeon: using MSI.\n"); |
d8f60cfc | 130 | } |
3e5cb98d | 131 | } |
771fe6b9 | 132 | rdev->irq.installed = true; |
003e69f9 JG |
133 | r = drm_irq_install(rdev->ddev); |
134 | if (r) { | |
135 | rdev->irq.installed = false; | |
136 | return r; | |
137 | } | |
771fe6b9 JG |
138 | DRM_INFO("radeon: irq initialized.\n"); |
139 | return 0; | |
140 | } | |
141 | ||
142 | void radeon_irq_kms_fini(struct radeon_device *rdev) | |
143 | { | |
003e69f9 | 144 | drm_vblank_cleanup(rdev->ddev); |
771fe6b9 | 145 | if (rdev->irq.installed) { |
771fe6b9 | 146 | drm_irq_uninstall(rdev->ddev); |
003e69f9 | 147 | rdev->irq.installed = false; |
3e5cb98d AD |
148 | if (rdev->msi_enabled) |
149 | pci_disable_msi(rdev->pdev); | |
771fe6b9 JG |
150 | } |
151 | } | |
1614f8b1 DA |
152 | |
153 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev) | |
154 | { | |
155 | unsigned long irqflags; | |
156 | ||
157 | spin_lock_irqsave(&rdev->irq.sw_lock, irqflags); | |
158 | if (rdev->ddev->irq_enabled && (++rdev->irq.sw_refcount == 1)) { | |
159 | rdev->irq.sw_int = true; | |
160 | radeon_irq_set(rdev); | |
161 | } | |
162 | spin_unlock_irqrestore(&rdev->irq.sw_lock, irqflags); | |
163 | } | |
164 | ||
165 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev) | |
166 | { | |
167 | unsigned long irqflags; | |
168 | ||
169 | spin_lock_irqsave(&rdev->irq.sw_lock, irqflags); | |
170 | BUG_ON(rdev->ddev->irq_enabled && rdev->irq.sw_refcount <= 0); | |
171 | if (rdev->ddev->irq_enabled && (--rdev->irq.sw_refcount == 0)) { | |
172 | rdev->irq.sw_int = false; | |
173 | radeon_irq_set(rdev); | |
174 | } | |
175 | spin_unlock_irqrestore(&rdev->irq.sw_lock, irqflags); | |
176 | } | |
177 |