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drm/radeon/kms: enable underscan option for digital connectors
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_mode.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm_crtc.h>
34#include <drm_mode.h>
35#include <drm_edid.h>
746c1aa4 36#include <drm_dp_helper.h>
68adac5e 37#include <drm_fixed.h>
771fe6b9
JG		 38#include <linux/i2c.h>
39#include <linux/i2c-id.h>
40#include <linux/i2c-algo-bit.h>
c93bb85b 41
38651674 42struct radeon_bo;
c93bb85b 43struct radeon_device;
771fe6b9
JG		 44
45#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
46#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
47#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
48#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
49
771fe6b9
JG		 50enum radeon_rmx_type {
51 RMX_OFF,
52 RMX_FULL,
53 RMX_CENTER,
54 RMX_ASPECT
55};
56
57enum radeon_tv_std {
58 TV_STD_NTSC,
59 TV_STD_PAL,
60 TV_STD_PAL_M,
61 TV_STD_PAL_60,
62 TV_STD_NTSC_J,
63 TV_STD_SCART_PAL,
64 TV_STD_SECAM,
65 TV_STD_PAL_CN,
d79766fa 66 TV_STD_PAL_N,
771fe6b9
JG		 67};
68
5b1714d3
AD		 69enum radeon_underscan_type {
70 UNDERSCAN_OFF,
71 UNDERSCAN_ON,
72 UNDERSCAN_AUTO,
73};
74
8e36ed00
AD		 75enum radeon_hpd_id {
76 RADEON_HPD_1 = 0,
77 RADEON_HPD_2,
78 RADEON_HPD_3,
79 RADEON_HPD_4,
80 RADEON_HPD_5,
81 RADEON_HPD_6,
82 RADEON_HPD_NONE = 0xff,
83};
84
9b9fe724
AD		 85/* radeon gpio-based i2c
86 * 1. "mask" reg and bits
87 * grabs the gpio pins for software use
88 * 0=not held 1=held
89 * 2. "a" reg and bits
90 * output pin value
91 * 0=low 1=high
92 * 3. "en" reg and bits
93 * sets the pin direction
94 * 0=input 1=output
95 * 4. "y" reg and bits
96 * input pin value
97 * 0=low 1=high
98 */
771fe6b9
JG		 99struct radeon_i2c_bus_rec {
100 bool valid;
6a93cb25
AD		 101 /* id used by atom */
102 uint8_t i2c_id;
bcc1c2a1 103 /* id used by atom */
8e36ed00 104 enum radeon_hpd_id hpd;
6a93cb25
AD		 105 /* can be used with hw i2c engine */
106 bool hw_capable;
107 /* uses multi-media i2c engine */
108 bool mm_i2c;
109 /* regs and bits */
771fe6b9
JG		 110 uint32_t mask_clk_reg;
111 uint32_t mask_data_reg;
112 uint32_t a_clk_reg;
113 uint32_t a_data_reg;
9b9fe724
AD		 114 uint32_t en_clk_reg;
115 uint32_t en_data_reg;
116 uint32_t y_clk_reg;
117 uint32_t y_data_reg;
771fe6b9
JG		 118 uint32_t mask_clk_mask;
119 uint32_t mask_data_mask;
771fe6b9
JG		 120 uint32_t a_clk_mask;
121 uint32_t a_data_mask;
9b9fe724
AD		 122 uint32_t en_clk_mask;
123 uint32_t en_data_mask;
124 uint32_t y_clk_mask;
125 uint32_t y_data_mask;
771fe6b9
JG		 126};
127
128struct radeon_tmds_pll {
129 uint32_t freq;
130 uint32_t value;
131};
132
133#define RADEON_MAX_BIOS_CONNECTOR 16
134
7c27f87d 135/* pll flags */
771fe6b9
JG		 136#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
137#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
138#define RADEON_PLL_USE_REF_DIV (1 << 2)
139#define RADEON_PLL_LEGACY (1 << 3)
140#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
141#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
142#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
143#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
144#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
145#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
146#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
d0e275a9 147#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
fc10332b 148#define RADEON_PLL_USE_POST_DIV (1 << 12)
86cb2bbf 149#define RADEON_PLL_IS_LCD (1 << 13)
771fe6b9 150
7c27f87d
AD		 151/* pll algo */
152enum radeon_pll_algo {
153 PLL_ALGO_LEGACY,
383be5d1 154 PLL_ALGO_NEW
7c27f87d
AD		 155};
156
771fe6b9 157struct radeon_pll {
fc10332b
AD		 158 /* reference frequency */
159 uint32_t reference_freq;
160
161 /* fixed dividers */
162 uint32_t reference_div;
163 uint32_t post_div;
164
165 /* pll in/out limits */
771fe6b9
JG		 166 uint32_t pll_in_min;
167 uint32_t pll_in_max;
168 uint32_t pll_out_min;
169 uint32_t pll_out_max;
86cb2bbf
AD		 170 uint32_t lcd_pll_out_min;
171 uint32_t lcd_pll_out_max;
fc10332b 172 uint32_t best_vco;
771fe6b9 173
fc10332b 174 /* divider limits */
771fe6b9
JG		 175 uint32_t min_ref_div;
176 uint32_t max_ref_div;
177 uint32_t min_post_div;
178 uint32_t max_post_div;
179 uint32_t min_feedback_div;
180 uint32_t max_feedback_div;
181 uint32_t min_frac_feedback_div;
182 uint32_t max_frac_feedback_div;
fc10332b
AD		 183
184 /* flags for the current clock */
185 uint32_t flags;
186
187 /* pll id */
188 uint32_t id;
7c27f87d
AD		 189 /* pll algo */
190 enum radeon_pll_algo algo;
771fe6b9
JG		 191};
192
193struct radeon_i2c_chan {
771fe6b9 194 struct i2c_adapter adapter;
746c1aa4
DA		 195 struct drm_device *dev;
196 union {
ac1aade6 197 struct i2c_algo_bit_data bit;
746c1aa4 198 struct i2c_algo_dp_aux_data dp;
746c1aa4 199 } algo;
771fe6b9
JG		 200 struct radeon_i2c_bus_rec rec;
201};
202
203/* mostly for macs, but really any system without connector tables */
204enum radeon_connector_table {
205 CT_NONE,
206 CT_GENERIC,
207 CT_IBOOK,
208 CT_POWERBOOK_EXTERNAL,
209 CT_POWERBOOK_INTERNAL,
210 CT_POWERBOOK_VGA,
211 CT_MINI_EXTERNAL,
212 CT_MINI_INTERNAL,
213 CT_IMAC_G5_ISIGHT,
214 CT_EMAC,
76a7142a 215 CT_RN50_POWER,
771fe6b9
JG		 216};
217
fcec570b
AD		 218enum radeon_dvo_chip {
219 DVO_SIL164,
220 DVO_SIL1178,
221};
222
8be48d92 223struct radeon_fbdev;
38651674 224
771fe6b9
JG		 225struct radeon_mode_info {
226 struct atom_context *atom_context;
61c4b24b 227 struct card_info *atom_card_info;
771fe6b9
JG		 228 enum radeon_connector_table connector_table;
229 bool mode_config_initialized;
bcc1c2a1 230 struct radeon_crtc *crtcs[6];
445282db
DA		 231 /* DVI-I properties */
232 struct drm_property *coherent_mode_property;
233 /* DAC enable load detect */
234 struct drm_property *load_detect_property;
5b1714d3 235 /* TV standard */
445282db
DA		 236 struct drm_property *tv_std_property;
237 /* legacy TMDS PLL detect */
238 struct drm_property *tmds_pll_property;
5b1714d3
AD		 239 /* underscan */
240 struct drm_property *underscan_property;
3c537889
AD		 241 /* hardcoded DFP edid from BIOS */
242 struct edid *bios_hardcoded_edid;
38651674
DA		 243
244 /* pointer to fbdev info structure */
8be48d92 245 struct radeon_fbdev *rfbdev;
c93bb85b
JG		 246};
247
4ce001ab
DA		 248#define MAX_H_CODE_TIMING_LEN 32
249#define MAX_V_CODE_TIMING_LEN 32
250
251/* need to store these as reading
252 back code tables is excessive */
253struct radeon_tv_regs {
254 uint32_t tv_uv_adr;
255 uint32_t timing_cntl;
256 uint32_t hrestart;
257 uint32_t vrestart;
258 uint32_t frestart;
259 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
260 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
261};
262
771fe6b9
JG		 263struct radeon_crtc {
264 struct drm_crtc base;
265 int crtc_id;
266 u16 lut_r[256], lut_g[256], lut_b[256];
267 bool enabled;
268 bool can_tile;
269 uint32_t crtc_offset;
771fe6b9
JG		 270 struct drm_gem_object *cursor_bo;
271 uint64_t cursor_addr;
272 int cursor_width;
273 int cursor_height;
4162338a 274 uint32_t legacy_display_base_addr;
c836e862 275 uint32_t legacy_cursor_offset;
c93bb85b 276 enum radeon_rmx_type rmx_type;
5b1714d3
AD		 277 u8 h_border;
278 u8 v_border;
c93bb85b
JG		 279 fixed20_12 vsc;
280 fixed20_12 hsc;
de2103e4 281 struct drm_display_mode native_mode;
bcc1c2a1 282 int pll_id;
771fe6b9
JG		 283};
284
285struct radeon_encoder_primary_dac {
286 /* legacy primary dac */
287 uint32_t ps2_pdac_adj;
288};
289
290struct radeon_encoder_lvds {
291 /* legacy lvds */
292 uint16_t panel_vcc_delay;
293 uint8_t panel_pwr_delay;
294 uint8_t panel_digon_delay;
295 uint8_t panel_blon_delay;
296 uint16_t panel_ref_divider;
297 uint8_t panel_post_divider;
298 uint16_t panel_fb_divider;
299 bool use_bios_dividers;
300 uint32_t lvds_gen_cntl;
301 /* panel mode */
de2103e4 302 struct drm_display_mode native_mode;
771fe6b9
JG		 303};
304
305struct radeon_encoder_tv_dac {
306 /* legacy tv dac */
307 uint32_t ps2_tvdac_adj;
308 uint32_t ntsc_tvdac_adj;
309 uint32_t pal_tvdac_adj;
310
4ce001ab
DA		 311 int h_pos;
312 int v_pos;
313 int h_size;
314 int supported_tv_stds;
315 bool tv_on;
771fe6b9 316 enum radeon_tv_std tv_std;
4ce001ab 317 struct radeon_tv_regs tv;
771fe6b9
JG		 318};
319
320struct radeon_encoder_int_tmds {
321 /* legacy int tmds */
322 struct radeon_tmds_pll tmds_pll[4];
323};
324
fcec570b
AD		 325struct radeon_encoder_ext_tmds {
326 /* tmds over dvo */
327 struct radeon_i2c_chan *i2c_bus;
328 uint8_t slave_addr;
329 enum radeon_dvo_chip dvo_chip;
330};
331
ebbe1cb9
AD		 332/* spread spectrum */
333struct radeon_atom_ss {
334 uint16_t percentage;
335 uint8_t type;
336 uint8_t step;
337 uint8_t delay;
338 uint8_t range;
339 uint8_t refdiv;
340};
341
771fe6b9
JG		 342struct radeon_encoder_atom_dig {
343 /* atom dig */
344 bool coherent_mode;
f28cf339 345 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */
771fe6b9
JG		 346 /* atom lvds */
347 uint32_t lvds_misc;
348 uint16_t panel_pwr_delay;
7c27f87d 349 enum radeon_pll_algo pll_algo;
ebbe1cb9 350 struct radeon_atom_ss *ss;
771fe6b9 351 /* panel mode */
de2103e4 352 struct drm_display_mode native_mode;
771fe6b9
JG		 353};
354
4ce001ab
DA		 355struct radeon_encoder_atom_dac {
356 enum radeon_tv_std tv_std;
357};
358
771fe6b9
JG		 359struct radeon_encoder {
360 struct drm_encoder base;
361 uint32_t encoder_id;
362 uint32_t devices;
4ce001ab 363 uint32_t active_device;
771fe6b9
JG		 364 uint32_t flags;
365 uint32_t pixel_clock;
366 enum radeon_rmx_type rmx_type;
5b1714d3 367 enum radeon_underscan_type underscan_type;
de2103e4 368 struct drm_display_mode native_mode;
771fe6b9 369 void *enc_priv;
58bd0863 370 int audio_polling_active;
dafc3bd5 371 int hdmi_offset;
808032ee 372 int hdmi_config_offset;
dafc3bd5
CK		 373 int hdmi_audio_workaround;
374 int hdmi_buffer_status;
771fe6b9
JG		 375};
376
377struct radeon_connector_atom_dig {
378 uint32_t igp_lane_info;
379 bool linkb;
4143e919 380 /* displayport */
746c1aa4 381 struct radeon_i2c_chan *dp_i2c_bus;
1a66c95a 382 u8 dpcd[8];
4143e919 383 u8 dp_sink_type;
5801ead6
AD		 384 int dp_clock;
385 int dp_lane_count;
771fe6b9
JG		 386};
387
eed45b30
AD		 388struct radeon_gpio_rec {
389 bool valid;
390 u8 id;
391 u32 reg;
392 u32 mask;
393};
394
eed45b30
AD		 395struct radeon_hpd {
396 enum radeon_hpd_id hpd;
397 u8 plugged_state;
398 struct radeon_gpio_rec gpio;
399};
400
771fe6b9
JG		 401struct radeon_connector {
402 struct drm_connector base;
403 uint32_t connector_id;
404 uint32_t devices;
405 struct radeon_i2c_chan *ddc_bus;
5b1714d3 406 /* some systems have an hdmi and vga port with a shared ddc line */
0294cf4f 407 bool shared_ddc;
4ce001ab
DA		 408 bool use_digital;
409 /* we need to mind the EDID between detect
410 and get modes due to analog/digital/tvencoder */
411 struct edid *edid;
771fe6b9 412 void *con_priv;
445282db 413 bool dac_load_detect;
b75fad06 414 uint16_t connector_object_id;
eed45b30 415 struct radeon_hpd hpd;
771fe6b9
JG		 416};
417
418struct radeon_framebuffer {
419 struct drm_framebuffer base;
420 struct drm_gem_object *obj;
421};
422
d79766fa
AD		 423extern enum radeon_tv_std
424radeon_combios_get_tv_info(struct radeon_device *rdev);
425extern enum radeon_tv_std
426radeon_atombios_get_tv_info(struct radeon_device *rdev);
427
5b1714d3
AD		 428extern struct drm_connector *
429radeon_get_connector_for_encoder(struct drm_encoder *encoder);
430
d4877cf2
AD		 431extern void radeon_connector_hotplug(struct drm_connector *connector);
432extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
5801ead6
AD		 433extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
434 struct drm_display_mode *mode);
435extern void radeon_dp_set_link_config(struct drm_connector *connector,
436 struct drm_display_mode *mode);
437extern void dp_link_train(struct drm_encoder *encoder,
438 struct drm_connector *connector);
4143e919 439extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
9fa05c98 440extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
bcc1c2a1 441extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action);
5801ead6
AD		 442extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
443 int action, uint8_t lane_num,
444 uint8_t lane_set);
746c1aa4
DA		 445extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
446 uint8_t write_byte, uint8_t *read_byte);
447
448extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
6a93cb25
AD		 449 struct radeon_i2c_bus_rec *rec,
450 const char *name);
771fe6b9
JG		 451extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
452 struct radeon_i2c_bus_rec *rec,
453 const char *name);
454extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
5a6f98f5
AD		 455extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
456 u8 slave_addr,
457 u8 addr,
458 u8 *val);
459extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
460 u8 slave_addr,
461 u8 addr,
462 u8 val);
771fe6b9
JG		 463extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
464extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
465
466extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
467
468extern void radeon_compute_pll(struct radeon_pll *pll,
469 uint64_t freq,
470 uint32_t *dot_clock_p,
471 uint32_t *fb_div_p,
472 uint32_t *frac_fb_div_p,
473 uint32_t *ref_div_p,
fc10332b 474 uint32_t *post_div_p);
771fe6b9 475
1f3b6a45
DA		 476extern void radeon_setup_encoder_clones(struct drm_device *dev);
477
771fe6b9
JG		 478struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
479struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
480struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
481struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
482struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
483extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
32f48ffe 484extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
771fe6b9 485extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
4ce001ab 486extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
771fe6b9
JG		 487
488extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
489extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
490 struct drm_framebuffer *old_fb);
491extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
492 struct drm_display_mode *mode,
493 struct drm_display_mode *adjusted_mode,
494 int x, int y,
495 struct drm_framebuffer *old_fb);
496extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
497
498extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
499 struct drm_framebuffer *old_fb);
771fe6b9
JG		 500
501extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
502 struct drm_file *file_priv,
503 uint32_t handle,
504 uint32_t width,
505 uint32_t height);
506extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
507 int x, int y);
508
3c537889
AD		 509extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
510extern struct edid *
511radeon_combios_get_hardcoded_edid(struct radeon_device *rdev);
771fe6b9
JG		 512extern bool radeon_atom_get_clock_info(struct drm_device *dev);
513extern bool radeon_combios_get_clock_info(struct drm_device *dev);
514extern struct radeon_encoder_atom_dig *
515radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
fcec570b
AD		 516extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
517 struct radeon_encoder_int_tmds *tmds);
518extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
519 struct radeon_encoder_int_tmds *tmds);
520extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
521 struct radeon_encoder_int_tmds *tmds);
522extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
523 struct radeon_encoder_ext_tmds *tmds);
524extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
525 struct radeon_encoder_ext_tmds *tmds);
6fe7ac3f
AD		 526extern struct radeon_encoder_primary_dac *
527radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
528extern struct radeon_encoder_tv_dac *
529radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
771fe6b9
JG		 530extern struct radeon_encoder_lvds *
531radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
771fe6b9
JG		 532extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
533extern struct radeon_encoder_tv_dac *
534radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
535extern struct radeon_encoder_primary_dac *
536radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
fcec570b
AD		 537extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
538extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
771fe6b9
JG		 539extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
540extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
541extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
542extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
f657c2a7
YZ		 543extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
544extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
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JG		 545extern void
546radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
547extern void
548radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
549extern void
550radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
551extern void
552radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
553extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
554 u16 blue, int regno);
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DA		 555extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
556 u16 *blue, int regno);
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DA		 557void radeon_framebuffer_init(struct drm_device *dev,
558 struct radeon_framebuffer *rfb,
559 struct drm_mode_fb_cmd *mode_cmd,
560 struct drm_gem_object *obj);
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JG		 561
562int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
563bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
564bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
565void radeon_atombios_init_crtc(struct drm_device *dev,
566 struct radeon_crtc *radeon_crtc);
567void radeon_legacy_init_crtc(struct drm_device *dev,
568 struct radeon_crtc *radeon_crtc);
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JG		 569
570void radeon_get_clock_info(struct drm_device *dev);
571
572extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
573extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
574
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JG		 575void radeon_enc_destroy(struct drm_encoder *encoder);
576void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
577void radeon_combios_asic_init(struct drm_device *dev);
578extern int radeon_static_clocks_init(struct drm_device *dev);
c93bb85b
JG		 579bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
580 struct drm_display_mode *mode,
581 struct drm_display_mode *adjusted_mode);
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AD		 582void radeon_panel_mode_fixup(struct drm_encoder *encoder,
583 struct drm_display_mode *adjusted_mode);
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DA		 584void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
585
586/* legacy tv */
587void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
588 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
589 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
590void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
591 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
592 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
593void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
594 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
595 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
596void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
597 struct drm_display_mode *mode,
598 struct drm_display_mode *adjusted_mode);
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DA		 599
600/* fbdev layer */
601int radeon_fbdev_init(struct radeon_device *rdev);
602void radeon_fbdev_fini(struct radeon_device *rdev);
603void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
604int radeon_fbdev_total_size(struct radeon_device *rdev);
605bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
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DA		 606
607void radeon_fb_output_poll_changed(struct radeon_device *rdev);
771fe6b9 608#endif
Linux kernel - Deliverables
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