[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_mode.h

/*
 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
 *                VA Linux Systems Inc., Fremont, California.
 * Copyright 2008 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Original Authors:
 *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
 *
 * Kernel port Author: Dave Airlie
 */

#ifndef RADEON_MODE_H
#define RADEON_MODE_H

#include <drm_crtc.h>
#include <drm_mode.h>
#include <drm_edid.h>
#include <linux/i2c.h>
#include <linux/i2c-id.h>
#include <linux/i2c-algo-bit.h>
#include "radeon_fixed.h"

struct radeon_device;

#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)

enum radeon_connector_type {
	CONNECTOR_NONE,
	CONNECTOR_VGA,
	CONNECTOR_DVI_I,
	CONNECTOR_DVI_D,
	CONNECTOR_DVI_A,
	CONNECTOR_STV,
	CONNECTOR_CTV,
	CONNECTOR_LVDS,
	CONNECTOR_DIGITAL,
	CONNECTOR_SCART,
	CONNECTOR_HDMI_TYPE_A,
	CONNECTOR_HDMI_TYPE_B,
	CONNECTOR_0XC,
	CONNECTOR_0XD,
	CONNECTOR_DIN,
	CONNECTOR_DISPLAY_PORT,
	CONNECTOR_UNSUPPORTED
};

enum radeon_dvi_type {
	DVI_AUTO,
	DVI_DIGITAL,
	DVI_ANALOG
};

enum radeon_rmx_type {
	RMX_OFF,
	RMX_FULL,
	RMX_CENTER,
	RMX_ASPECT
};

enum radeon_tv_std {
	TV_STD_NTSC,
	TV_STD_PAL,
	TV_STD_PAL_M,
	TV_STD_PAL_60,
	TV_STD_NTSC_J,
	TV_STD_SCART_PAL,
	TV_STD_SECAM,
	TV_STD_PAL_CN,
};

struct radeon_i2c_bus_rec {
	bool valid;
	uint32_t mask_clk_reg;
	uint32_t mask_data_reg;
	uint32_t a_clk_reg;
	uint32_t a_data_reg;
	uint32_t put_clk_reg;
	uint32_t put_data_reg;
	uint32_t get_clk_reg;
	uint32_t get_data_reg;
	uint32_t mask_clk_mask;
	uint32_t mask_data_mask;
	uint32_t put_clk_mask;
	uint32_t put_data_mask;
	uint32_t get_clk_mask;
	uint32_t get_data_mask;
	uint32_t a_clk_mask;
	uint32_t a_data_mask;
};

struct radeon_tmds_pll {
    uint32_t freq;
    uint32_t value;
};

#define RADEON_MAX_BIOS_CONNECTOR 16

#define RADEON_PLL_USE_BIOS_DIVS        (1 << 0)
#define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
#define RADEON_PLL_USE_REF_DIV          (1 << 2)
#define RADEON_PLL_LEGACY               (1 << 3)
#define RADEON_PLL_PREFER_LOW_REF_DIV   (1 << 4)
#define RADEON_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
#define RADEON_PLL_PREFER_LOW_FB_DIV    (1 << 6)
#define RADEON_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
#define RADEON_PLL_PREFER_LOW_POST_DIV  (1 << 8)
#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
#define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)

struct radeon_pll {
	uint16_t reference_freq;
	uint16_t reference_div;
	uint32_t pll_in_min;
	uint32_t pll_in_max;
	uint32_t pll_out_min;
	uint32_t pll_out_max;
	uint16_t xclk;

	uint32_t min_ref_div;
	uint32_t max_ref_div;
	uint32_t min_post_div;
	uint32_t max_post_div;
	uint32_t min_feedback_div;
	uint32_t max_feedback_div;
	uint32_t min_frac_feedback_div;
	uint32_t max_frac_feedback_div;
	uint32_t best_vco;
};

struct radeon_i2c_chan {
	struct drm_device *dev;
	struct i2c_adapter adapter;
	struct i2c_algo_bit_data algo;
	struct radeon_i2c_bus_rec rec;
};

/* mostly for macs, but really any system without connector tables */
enum radeon_connector_table {
	CT_NONE,
	CT_GENERIC,
	CT_IBOOK,
	CT_POWERBOOK_EXTERNAL,
	CT_POWERBOOK_INTERNAL,
	CT_POWERBOOK_VGA,
	CT_MINI_EXTERNAL,
	CT_MINI_INTERNAL,
	CT_IMAC_G5_ISIGHT,
	CT_EMAC,
};

struct radeon_mode_info {
	struct atom_context *atom_context;
	struct card_info *atom_card_info;
	enum radeon_connector_table connector_table;
	bool mode_config_initialized;
	struct radeon_crtc *crtcs[2];
	/* DVI-I properties */
	struct drm_property *coherent_mode_property;
	/* DAC enable load detect */
	struct drm_property *load_detect_property;
	/* TV standard load detect */
	struct drm_property *tv_std_property;
	/* legacy TMDS PLL detect */
	struct drm_property *tmds_pll_property;

};

#define MAX_H_CODE_TIMING_LEN 32
#define MAX_V_CODE_TIMING_LEN 32

/* need to store these as reading
   back code tables is excessive */
struct radeon_tv_regs {
	uint32_t tv_uv_adr;
	uint32_t timing_cntl;
	uint32_t hrestart;
	uint32_t vrestart;
	uint32_t frestart;
	uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
	uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
};

struct radeon_crtc {
	struct drm_crtc base;
	int crtc_id;
	u16 lut_r[256], lut_g[256], lut_b[256];
	bool enabled;
	bool can_tile;
	uint32_t crtc_offset;
	struct drm_gem_object *cursor_bo;
	uint64_t cursor_addr;
	int cursor_width;
	int cursor_height;
	uint32_t legacy_display_base_addr;
	uint32_t legacy_cursor_offset;
	enum radeon_rmx_type rmx_type;
	fixed20_12 vsc;
	fixed20_12 hsc;
	struct drm_display_mode native_mode;
};

struct radeon_encoder_primary_dac {
	/* legacy primary dac */
	uint32_t ps2_pdac_adj;
};

struct radeon_encoder_lvds {
	/* legacy lvds */
	uint16_t panel_vcc_delay;
	uint8_t  panel_pwr_delay;
	uint8_t  panel_digon_delay;
	uint8_t  panel_blon_delay;
	uint16_t panel_ref_divider;
	uint8_t  panel_post_divider;
	uint16_t panel_fb_divider;
	bool     use_bios_dividers;
	uint32_t lvds_gen_cntl;
	/* panel mode */
	struct drm_display_mode native_mode;
};

struct radeon_encoder_tv_dac {
	/* legacy tv dac */
	uint32_t ps2_tvdac_adj;
	uint32_t ntsc_tvdac_adj;
	uint32_t pal_tvdac_adj;

	int               h_pos;
	int               v_pos;
	int               h_size;
	int               supported_tv_stds;
	bool              tv_on;
	enum radeon_tv_std tv_std;
	struct radeon_tv_regs tv;
};

struct radeon_encoder_int_tmds {
	/* legacy int tmds */
	struct radeon_tmds_pll tmds_pll[4];
};

/* spread spectrum */
struct radeon_atom_ss {
	uint16_t percentage;
	uint8_t type;
	uint8_t step;
	uint8_t delay;
	uint8_t range;
	uint8_t refdiv;
};

struct radeon_encoder_atom_dig {
	/* atom dig */
	bool coherent_mode;
	int dig_block;
	/* atom lvds */
	uint32_t lvds_misc;
	uint16_t panel_pwr_delay;
	struct radeon_atom_ss *ss;
	/* panel mode */
	struct drm_display_mode native_mode;
};

struct radeon_encoder_atom_dac {
	enum radeon_tv_std tv_std;
};

struct radeon_encoder {
	struct drm_encoder base;
	uint32_t encoder_id;
	uint32_t devices;
	uint32_t active_device;
	uint32_t flags;
	uint32_t pixel_clock;
	enum radeon_rmx_type rmx_type;
	struct drm_display_mode native_mode;
	void *enc_priv;
};

struct radeon_connector_atom_dig {
	uint32_t igp_lane_info;
	bool linkb;
};

struct radeon_connector {
	struct drm_connector base;
	uint32_t connector_id;
	uint32_t devices;
	struct radeon_i2c_chan *ddc_bus;
	/* some systems have a an hdmi and vga port with a shared ddc line */
	bool shared_ddc;
	bool use_digital;
	/* we need to mind the EDID between detect
	   and get modes due to analog/digital/tvencoder */
	struct edid *edid;
	void *con_priv;
	bool dac_load_detect;
};

struct radeon_framebuffer {
	struct drm_framebuffer base;
	struct drm_gem_object *obj;
};

extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
						 struct radeon_i2c_bus_rec *rec,
						 const char *name);
extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);

extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);

extern void radeon_compute_pll(struct radeon_pll *pll,
			       uint64_t freq,
			       uint32_t *dot_clock_p,
			       uint32_t *fb_div_p,
			       uint32_t *frac_fb_div_p,
			       uint32_t *ref_div_p,
			       uint32_t *post_div_p,
			       int flags);

struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);

extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
				   struct drm_framebuffer *old_fb);
extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
				   struct drm_display_mode *mode,
				   struct drm_display_mode *adjusted_mode,
				   int x, int y,
				   struct drm_framebuffer *old_fb);
extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);

extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
				 struct drm_framebuffer *old_fb);
extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc);

extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
				  struct drm_file *file_priv,
				  uint32_t handle,
				  uint32_t width,
				  uint32_t height);
extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
				   int x, int y);

extern bool radeon_atom_get_clock_info(struct drm_device *dev);
extern bool radeon_combios_get_clock_info(struct drm_device *dev);
extern struct radeon_encoder_atom_dig *
radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
				   struct radeon_encoder_int_tmds *tmds);
bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
					   struct radeon_encoder_int_tmds *tmds);
bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
					    struct radeon_encoder_int_tmds *tmds);
extern struct radeon_encoder_primary_dac *
radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
extern struct radeon_encoder_tv_dac *
radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
extern struct radeon_encoder_lvds *
radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
extern struct radeon_encoder_tv_dac *
radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
extern struct radeon_encoder_primary_dac *
radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
extern void
radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
extern void
radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
extern void
radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
extern void
radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
				     u16 blue, int regno);
extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
				     u16 *blue, int regno);
struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev,
						  struct drm_mode_fb_cmd *mode_cmd,
						  struct drm_gem_object *obj);

int radeonfb_probe(struct drm_device *dev);

int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
void radeon_atombios_init_crtc(struct drm_device *dev,
			       struct radeon_crtc *radeon_crtc);
void radeon_legacy_init_crtc(struct drm_device *dev,
			     struct radeon_crtc *radeon_crtc);
void radeon_i2c_do_lock(struct radeon_connector *radeon_connector, int lock_state);

void radeon_get_clock_info(struct drm_device *dev);

extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);

void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
			   struct drm_display_mode *mode,
			   struct drm_display_mode *adjusted_mode);
void radeon_enc_destroy(struct drm_encoder *encoder);
void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
void radeon_combios_asic_init(struct drm_device *dev);
extern int radeon_static_clocks_init(struct drm_device *dev);
bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
					struct drm_display_mode *mode,
					struct drm_display_mode *adjusted_mode);
void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);

/* legacy tv */
void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
				      uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
				      uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
				  uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
				  uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
				  uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
				  uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
			       struct drm_display_mode *mode,
			       struct drm_display_mode *adjusted_mode);
#endif
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
	3	* VA Linux Systems Inc., Fremont, California.
	4	* Copyright 2008 Red Hat Inc.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Original Authors:
	25	* Kevin E. Martin, Rickard E. Faith, Alan Hourihane
	26	*
	27	* Kernel port Author: Dave Airlie
	28	*/
	29
	30	#ifndef RADEON_MODE_H
	31	#define RADEON_MODE_H
	32
	33	#include <drm_crtc.h>
	34	#include <drm_mode.h>
	35	#include <drm_edid.h>
	36	#include <linux/i2c.h>
	37	#include <linux/i2c-id.h>
	38	#include <linux/i2c-algo-bit.h>
c93bb85b JG	39	#include "radeon_fixed.h"
	40
	41	struct radeon_device;
771fe6b9 JG	42
	43	#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
	44	#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
	45	#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
	46	#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
	47
	48	enum radeon_connector_type {
	49	CONNECTOR_NONE,
	50	CONNECTOR_VGA,
	51	CONNECTOR_DVI_I,
	52	CONNECTOR_DVI_D,
	53	CONNECTOR_DVI_A,
	54	CONNECTOR_STV,
	55	CONNECTOR_CTV,
	56	CONNECTOR_LVDS,
	57	CONNECTOR_DIGITAL,
	58	CONNECTOR_SCART,
	59	CONNECTOR_HDMI_TYPE_A,
	60	CONNECTOR_HDMI_TYPE_B,
	61	CONNECTOR_0XC,
	62	CONNECTOR_0XD,
	63	CONNECTOR_DIN,
	64	CONNECTOR_DISPLAY_PORT,
	65	CONNECTOR_UNSUPPORTED
	66	};
	67
	68	enum radeon_dvi_type {
	69	DVI_AUTO,
	70	DVI_DIGITAL,
	71	DVI_ANALOG
	72	};
	73
	74	enum radeon_rmx_type {
	75	RMX_OFF,
	76	RMX_FULL,
	77	RMX_CENTER,
	78	RMX_ASPECT
	79	};
	80
	81	enum radeon_tv_std {
	82	TV_STD_NTSC,
	83	TV_STD_PAL,
	84	TV_STD_PAL_M,
	85	TV_STD_PAL_60,
	86	TV_STD_NTSC_J,
	87	TV_STD_SCART_PAL,
	88	TV_STD_SECAM,
	89	TV_STD_PAL_CN,
	90	};
	91
	92	struct radeon_i2c_bus_rec {
	93	bool valid;
	94	uint32_t mask_clk_reg;
	95	uint32_t mask_data_reg;
	96	uint32_t a_clk_reg;
	97	uint32_t a_data_reg;
	98	uint32_t put_clk_reg;
	99	uint32_t put_data_reg;
	100	uint32_t get_clk_reg;
	101	uint32_t get_data_reg;
	102	uint32_t mask_clk_mask;
	103	uint32_t mask_data_mask;
	104	uint32_t put_clk_mask;
	105	uint32_t put_data_mask;
106	uint32_t get_clk_mask;
107	uint32_t get_data_mask;
108	uint32_t a_clk_mask;
109	uint32_t a_data_mask;
110	};
111
112	struct radeon_tmds_pll {
113	uint32_t freq;
114	uint32_t value;
115	};
116
117	#define RADEON_MAX_BIOS_CONNECTOR 16
118
119	#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
120	#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
121	#define RADEON_PLL_USE_REF_DIV (1 << 2)
122	#define RADEON_PLL_LEGACY (1 << 3)
123	#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
124	#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
125	#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
126	#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
127	#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
128	#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
129	#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
d0e275a9	130	#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
771fe6b9 JG	131
	132	struct radeon_pll {
	133	uint16_t reference_freq;
	134	uint16_t reference_div;
	135	uint32_t pll_in_min;
	136	uint32_t pll_in_max;
	137	uint32_t pll_out_min;
	138	uint32_t pll_out_max;
	139	uint16_t xclk;
	140
	141	uint32_t min_ref_div;
	142	uint32_t max_ref_div;
	143	uint32_t min_post_div;
	144	uint32_t max_post_div;
	145	uint32_t min_feedback_div;
	146	uint32_t max_feedback_div;
	147	uint32_t min_frac_feedback_div;
	148	uint32_t max_frac_feedback_div;
	149	uint32_t best_vco;
	150	};
	151
	152	struct radeon_i2c_chan {
	153	struct drm_device *dev;
	154	struct i2c_adapter adapter;
	155	struct i2c_algo_bit_data algo;
	156	struct radeon_i2c_bus_rec rec;
	157	};
	158
	159	/* mostly for macs, but really any system without connector tables */
	160	enum radeon_connector_table {
	161	CT_NONE,
	162	CT_GENERIC,
	163	CT_IBOOK,
	164	CT_POWERBOOK_EXTERNAL,
	165	CT_POWERBOOK_INTERNAL,
	166	CT_POWERBOOK_VGA,
	167	CT_MINI_EXTERNAL,
	168	CT_MINI_INTERNAL,
	169	CT_IMAC_G5_ISIGHT,
	170	CT_EMAC,
	171	};
	172
	173	struct radeon_mode_info {
	174	struct atom_context *atom_context;
61c4b24b	175	struct card_info *atom_card_info;
771fe6b9 JG	176	enum radeon_connector_table connector_table;
771fe6b9 JG	177	bool mode_config_initialized;
c93bb85b	178	struct radeon_crtc *crtcs[2];
445282db DA	179	/* DVI-I properties */
	180	struct drm_property *coherent_mode_property;
	181	/* DAC enable load detect */
	182	struct drm_property *load_detect_property;
	183	/* TV standard load detect */
	184	struct drm_property *tv_std_property;
	185	/* legacy TMDS PLL detect */
	186	struct drm_property *tmds_pll_property;
	187
c93bb85b JG	188	};
c93bb85b JG	189
4ce001ab DA	190	#define MAX_H_CODE_TIMING_LEN 32
	191	#define MAX_V_CODE_TIMING_LEN 32
	192
	193	/* need to store these as reading
	194	back code tables is excessive */
	195	struct radeon_tv_regs {
	196	uint32_t tv_uv_adr;
	197	uint32_t timing_cntl;
	198	uint32_t hrestart;
	199	uint32_t vrestart;
	200	uint32_t frestart;
	201	uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
	202	uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
	203	};
	204
771fe6b9 JG	205	struct radeon_crtc {
	206	struct drm_crtc base;
	207	int crtc_id;
	208	u16 lut_r[256], lut_g[256], lut_b[256];
	209	bool enabled;
	210	bool can_tile;
	211	uint32_t crtc_offset;
771fe6b9 JG	212	struct drm_gem_object *cursor_bo;
	213	uint64_t cursor_addr;
	214	int cursor_width;
	215	int cursor_height;
4162338a	216	uint32_t legacy_display_base_addr;
c836e862	217	uint32_t legacy_cursor_offset;
c93bb85b	218	enum radeon_rmx_type rmx_type;
c93bb85b JG	219	fixed20_12 vsc;
c93bb85b JG	220	fixed20_12 hsc;
de2103e4	221	struct drm_display_mode native_mode;
771fe6b9 JG	222	};
	223
	224	struct radeon_encoder_primary_dac {
	225	/* legacy primary dac */
	226	uint32_t ps2_pdac_adj;
	227	};
	228
	229	struct radeon_encoder_lvds {
	230	/* legacy lvds */
	231	uint16_t panel_vcc_delay;
	232	uint8_t panel_pwr_delay;
	233	uint8_t panel_digon_delay;
	234	uint8_t panel_blon_delay;
	235	uint16_t panel_ref_divider;
	236	uint8_t panel_post_divider;
	237	uint16_t panel_fb_divider;
	238	bool use_bios_dividers;
	239	uint32_t lvds_gen_cntl;
	240	/* panel mode */
de2103e4	241	struct drm_display_mode native_mode;
771fe6b9 JG	242	};
	243
	244	struct radeon_encoder_tv_dac {
	245	/* legacy tv dac */
	246	uint32_t ps2_tvdac_adj;
	247	uint32_t ntsc_tvdac_adj;
	248	uint32_t pal_tvdac_adj;
	249
4ce001ab DA	250	int h_pos;
	251	int v_pos;
	252	int h_size;
	253	int supported_tv_stds;
	254	bool tv_on;
771fe6b9	255	enum radeon_tv_std tv_std;
4ce001ab	256	struct radeon_tv_regs tv;
771fe6b9 JG	257	};
	258
	259	struct radeon_encoder_int_tmds {
	260	/* legacy int tmds */
	261	struct radeon_tmds_pll tmds_pll[4];
	262	};
	263
ebbe1cb9 AD	264	/* spread spectrum */
	265	struct radeon_atom_ss {
	266	uint16_t percentage;
	267	uint8_t type;
	268	uint8_t step;
	269	uint8_t delay;
	270	uint8_t range;
	271	uint8_t refdiv;
	272	};
	273
771fe6b9 JG	274	struct radeon_encoder_atom_dig {
	275	/* atom dig */
	276	bool coherent_mode;
	277	int dig_block;
	278	/* atom lvds */
	279	uint32_t lvds_misc;
	280	uint16_t panel_pwr_delay;
ebbe1cb9	281	struct radeon_atom_ss *ss;
771fe6b9	282	/* panel mode */
de2103e4	283	struct drm_display_mode native_mode;
771fe6b9 JG	284	};
771fe6b9 JG	285
4ce001ab DA	286	struct radeon_encoder_atom_dac {
	287	enum radeon_tv_std tv_std;
	288	};
	289
771fe6b9 JG	290	struct radeon_encoder {
	291	struct drm_encoder base;
	292	uint32_t encoder_id;
	293	uint32_t devices;
4ce001ab	294	uint32_t active_device;
771fe6b9 JG	295	uint32_t flags;
	296	uint32_t pixel_clock;
	297	enum radeon_rmx_type rmx_type;
de2103e4	298	struct drm_display_mode native_mode;
771fe6b9 JG	299	void *enc_priv;
	300	};
	301
	302	struct radeon_connector_atom_dig {
	303	uint32_t igp_lane_info;
	304	bool linkb;
	305	};
	306
	307	struct radeon_connector {
	308	struct drm_connector base;
	309	uint32_t connector_id;
	310	uint32_t devices;
	311	struct radeon_i2c_chan *ddc_bus;
0294cf4f AD	312	/* some systems have a an hdmi and vga port with a shared ddc line */
0294cf4f AD	313	bool shared_ddc;
4ce001ab DA	314	bool use_digital;
	315	/* we need to mind the EDID between detect
	316	and get modes due to analog/digital/tvencoder */
	317	struct edid *edid;
771fe6b9	318	void *con_priv;
445282db	319	bool dac_load_detect;
771fe6b9 JG	320	};
	321
	322	struct radeon_framebuffer {
	323	struct drm_framebuffer base;
	324	struct drm_gem_object *obj;
	325	};
	326
	327	extern struct radeon_i2c_chan radeon_i2c_create(struct drm_device dev,
	328	struct radeon_i2c_bus_rec *rec,
	329	const char *name);
	330	extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
	331	extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
	332	extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
	333
	334	extern struct drm_encoder radeon_best_encoder(struct drm_connector connector);
	335
	336	extern void radeon_compute_pll(struct radeon_pll *pll,
	337	uint64_t freq,
	338	uint32_t *dot_clock_p,
	339	uint32_t *fb_div_p,
	340	uint32_t *frac_fb_div_p,
	341	uint32_t *ref_div_p,
	342	uint32_t *post_div_p,
	343	int flags);
	344
	345	struct drm_encoder radeon_encoder_legacy_lvds_add(struct drm_device dev, int bios_index);
	346	struct drm_encoder radeon_encoder_legacy_primary_dac_add(struct drm_device dev, int bios_index, int with_tv);
	347	struct drm_encoder radeon_encoder_legacy_tv_dac_add(struct drm_device dev, int bios_index, int with_tv);
	348	struct drm_encoder radeon_encoder_legacy_tmds_int_add(struct drm_device dev, int bios_index);
	349	struct drm_encoder radeon_encoder_legacy_tmds_ext_add(struct drm_device dev, int bios_index);
	350	extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
	351	extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
4ce001ab	352	extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
771fe6b9 JG	353
	354	extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
	355	extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
	356	struct drm_framebuffer *old_fb);
	357	extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
	358	struct drm_display_mode *mode,
	359	struct drm_display_mode *adjusted_mode,
	360	int x, int y,
	361	struct drm_framebuffer *old_fb);
	362	extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
	363
	364	extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
	365	struct drm_framebuffer *old_fb);
	366	extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc);
	367
	368	extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
	369	struct drm_file *file_priv,
	370	uint32_t handle,
	371	uint32_t width,
	372	uint32_t height);
	373	extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
	374	int x, int y);
	375
	376	extern bool radeon_atom_get_clock_info(struct drm_device *dev);
	377	extern bool radeon_combios_get_clock_info(struct drm_device *dev);
	378	extern struct radeon_encoder_atom_dig *
	379	radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
445282db DA	380	bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
	381	struct radeon_encoder_int_tmds *tmds);
	382	bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
	383	struct radeon_encoder_int_tmds *tmds);
	384	bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
	385	struct radeon_encoder_int_tmds *tmds);
6fe7ac3f AD	386	extern struct radeon_encoder_primary_dac *
	387	radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
	388	extern struct radeon_encoder_tv_dac *
	389	radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
771fe6b9 JG	390	extern struct radeon_encoder_lvds *
771fe6b9 JG	391	radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
771fe6b9 JG	392	extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
	393	extern struct radeon_encoder_tv_dac *
	394	radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
	395	extern struct radeon_encoder_primary_dac *
	396	radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
	397	extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
	398	extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
	399	extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
	400	extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
f657c2a7 YZ	401	extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
f657c2a7 YZ	402	extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
771fe6b9 JG	403	extern void
	404	radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
	405	extern void
	406	radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
	407	extern void
	408	radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
	409	extern void
	410	radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
	411	extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
	412	u16 blue, int regno);
b8c00ac5 DA	413	extern void radeon_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
b8c00ac5 DA	414	u16 *blue, int regno);
771fe6b9 JG	415	struct drm_framebuffer radeon_framebuffer_create(struct drm_device dev,
	416	struct drm_mode_fb_cmd *mode_cmd,
	417	struct drm_gem_object *obj);
	418
	419	int radeonfb_probe(struct drm_device *dev);
	420
	421	int radeonfb_remove(struct drm_device dev, struct drm_framebuffer fb);
	422	bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
	423	bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
	424	void radeon_atombios_init_crtc(struct drm_device *dev,
	425	struct radeon_crtc *radeon_crtc);
	426	void radeon_legacy_init_crtc(struct drm_device *dev,
	427	struct radeon_crtc *radeon_crtc);
	428	void radeon_i2c_do_lock(struct radeon_connector *radeon_connector, int lock_state);
	429
	430	void radeon_get_clock_info(struct drm_device *dev);
	431
	432	extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
	433	extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
	434
	435	void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
	436	struct drm_display_mode *mode,
	437	struct drm_display_mode *adjusted_mode);
	438	void radeon_enc_destroy(struct drm_encoder *encoder);
	439	void radeon_copy_fb(struct drm_device dev, struct drm_gem_object dst_obj);
	440	void radeon_combios_asic_init(struct drm_device *dev);
	441	extern int radeon_static_clocks_init(struct drm_device *dev);
c93bb85b JG	442	bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
	443	struct drm_display_mode *mode,
	444	struct drm_display_mode *adjusted_mode);
4ce001ab DA	445	void atom_rv515_force_tv_scaler(struct radeon_device rdev, struct radeon_crtc radeon_crtc);
	446
	447	/* legacy tv */
	448	void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
	449	uint32_t h_total_disp, uint32_t h_sync_strt_wid,
	450	uint32_t v_total_disp, uint32_t v_sync_strt_wid);
	451	void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
	452	uint32_t htotal_cntl, uint32_t ppll_ref_div,
	453	uint32_t ppll_div_3, uint32_t pixclks_cntl);
	454	void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
	455	uint32_t htotal2_cntl, uint32_t p2pll_ref_div,
	456	uint32_t p2pll_div_0, uint32_t pixclks_cntl);
	457	void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
	458	struct drm_display_mode *mode,
	459	struct drm_display_mode *adjusted_mode);
771fe6b9	460	#endif