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771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
32 | #include <linux/list.h> | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
771fe6b9 | 34 | #include <drm/drmP.h> |
760285e7 | 35 | #include <drm/radeon_drm.h> |
771fe6b9 | 36 | #include "radeon.h" |
99ee7fac | 37 | #include "radeon_trace.h" |
771fe6b9 | 38 | |
771fe6b9 JG |
39 | |
40 | int radeon_ttm_init(struct radeon_device *rdev); | |
41 | void radeon_ttm_fini(struct radeon_device *rdev); | |
4c788679 | 42 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); |
771fe6b9 JG |
43 | |
44 | /* | |
45 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all | |
46 | * function are calling it. | |
47 | */ | |
48 | ||
67e8e3f9 MO |
49 | static void radeon_update_memory_usage(struct radeon_bo *bo, |
50 | unsigned mem_type, int sign) | |
51 | { | |
52 | struct radeon_device *rdev = bo->rdev; | |
53 | u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT; | |
54 | ||
55 | switch (mem_type) { | |
56 | case TTM_PL_TT: | |
57 | if (sign > 0) | |
58 | atomic64_add(size, &rdev->gtt_usage); | |
59 | else | |
60 | atomic64_sub(size, &rdev->gtt_usage); | |
61 | break; | |
62 | case TTM_PL_VRAM: | |
63 | if (sign > 0) | |
64 | atomic64_add(size, &rdev->vram_usage); | |
65 | else | |
66 | atomic64_sub(size, &rdev->vram_usage); | |
67 | break; | |
68 | } | |
69 | } | |
70 | ||
4c788679 | 71 | static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) |
771fe6b9 | 72 | { |
4c788679 | 73 | struct radeon_bo *bo; |
771fe6b9 | 74 | |
4c788679 | 75 | bo = container_of(tbo, struct radeon_bo, tbo); |
67e8e3f9 MO |
76 | |
77 | radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1); | |
78 | ||
4c788679 JG |
79 | mutex_lock(&bo->rdev->gem.mutex); |
80 | list_del_init(&bo->list); | |
81 | mutex_unlock(&bo->rdev->gem.mutex); | |
82 | radeon_bo_clear_surface_reg(bo); | |
c265f24d | 83 | WARN_ON(!list_empty(&bo->va)); |
441921d5 | 84 | drm_gem_object_release(&bo->gem_base); |
4c788679 | 85 | kfree(bo); |
771fe6b9 JG |
86 | } |
87 | ||
d03d8589 JG |
88 | bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) |
89 | { | |
90 | if (bo->destroy == &radeon_ttm_bo_destroy) | |
91 | return true; | |
92 | return false; | |
93 | } | |
94 | ||
312ea8da JG |
95 | void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) |
96 | { | |
deadcb36 | 97 | u32 c = 0, i; |
312ea8da | 98 | |
312ea8da | 99 | rbo->placement.placement = rbo->placements; |
20707874 | 100 | rbo->placement.busy_placement = rbo->placements; |
c9da4a4b MD |
101 | if (domain & RADEON_GEM_DOMAIN_VRAM) { |
102 | /* Try placing BOs which don't need CPU access outside of the | |
103 | * CPU accessible part of VRAM | |
104 | */ | |
105 | if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) && | |
106 | rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) { | |
107 | rbo->placements[c].fpfn = | |
108 | rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
109 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | | |
110 | TTM_PL_FLAG_UNCACHED | | |
111 | TTM_PL_FLAG_VRAM; | |
112 | } | |
113 | ||
114 | rbo->placements[c].fpfn = 0; | |
f1217ed0 CK |
115 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | |
116 | TTM_PL_FLAG_UNCACHED | | |
117 | TTM_PL_FLAG_VRAM; | |
c9da4a4b | 118 | } |
f1217ed0 | 119 | |
0d0b3e74 | 120 | if (domain & RADEON_GEM_DOMAIN_GTT) { |
02376d82 | 121 | if (rbo->flags & RADEON_GEM_GTT_UC) { |
c9da4a4b | 122 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
123 | rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | |
124 | TTM_PL_FLAG_TT; | |
125 | ||
02376d82 MD |
126 | } else if ((rbo->flags & RADEON_GEM_GTT_WC) || |
127 | (rbo->rdev->flags & RADEON_IS_AGP)) { | |
c9da4a4b | 128 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
129 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | |
130 | TTM_PL_FLAG_UNCACHED | | |
02376d82 | 131 | TTM_PL_FLAG_TT; |
0d0b3e74 | 132 | } else { |
c9da4a4b | 133 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
134 | rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | |
135 | TTM_PL_FLAG_TT; | |
0d0b3e74 JG |
136 | } |
137 | } | |
f1217ed0 | 138 | |
0d0b3e74 | 139 | if (domain & RADEON_GEM_DOMAIN_CPU) { |
02376d82 | 140 | if (rbo->flags & RADEON_GEM_GTT_UC) { |
c9da4a4b | 141 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
142 | rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | |
143 | TTM_PL_FLAG_SYSTEM; | |
144 | ||
02376d82 MD |
145 | } else if ((rbo->flags & RADEON_GEM_GTT_WC) || |
146 | rbo->rdev->flags & RADEON_IS_AGP) { | |
c9da4a4b | 147 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
148 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | |
149 | TTM_PL_FLAG_UNCACHED | | |
02376d82 | 150 | TTM_PL_FLAG_SYSTEM; |
0d0b3e74 | 151 | } else { |
c9da4a4b | 152 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
153 | rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | |
154 | TTM_PL_FLAG_SYSTEM; | |
0d0b3e74 JG |
155 | } |
156 | } | |
c9da4a4b MD |
157 | if (!c) { |
158 | rbo->placements[c].fpfn = 0; | |
f1217ed0 CK |
159 | rbo->placements[c++].flags = TTM_PL_MASK_CACHING | |
160 | TTM_PL_FLAG_SYSTEM; | |
c9da4a4b | 161 | } |
f1217ed0 | 162 | |
312ea8da JG |
163 | rbo->placement.num_placement = c; |
164 | rbo->placement.num_busy_placement = c; | |
deadcb36 | 165 | |
f1217ed0 | 166 | for (i = 0; i < c; ++i) { |
c8584039 | 167 | if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && |
c9da4a4b MD |
168 | (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && |
169 | !rbo->placements[i].fpfn) | |
c8584039 MD |
170 | rbo->placements[i].lpfn = |
171 | rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
172 | else | |
173 | rbo->placements[i].lpfn = 0; | |
f1217ed0 | 174 | } |
312ea8da JG |
175 | } |
176 | ||
441921d5 | 177 | int radeon_bo_create(struct radeon_device *rdev, |
831b6966 ML |
178 | unsigned long size, int byte_align, bool kernel, |
179 | u32 domain, u32 flags, struct sg_table *sg, | |
180 | struct reservation_object *resv, | |
181 | struct radeon_bo **bo_ptr) | |
771fe6b9 | 182 | { |
4c788679 | 183 | struct radeon_bo *bo; |
771fe6b9 | 184 | enum ttm_bo_type type; |
93225b0d | 185 | unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; |
57de4ba9 | 186 | size_t acc_size; |
771fe6b9 JG |
187 | int r; |
188 | ||
441921d5 DV |
189 | size = ALIGN(size, PAGE_SIZE); |
190 | ||
771fe6b9 JG |
191 | if (kernel) { |
192 | type = ttm_bo_type_kernel; | |
40f5cf99 AD |
193 | } else if (sg) { |
194 | type = ttm_bo_type_sg; | |
771fe6b9 JG |
195 | } else { |
196 | type = ttm_bo_type_device; | |
197 | } | |
4c788679 | 198 | *bo_ptr = NULL; |
2b66b50b | 199 | |
57de4ba9 JG |
200 | acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, |
201 | sizeof(struct radeon_bo)); | |
202 | ||
4c788679 JG |
203 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
204 | if (bo == NULL) | |
771fe6b9 | 205 | return -ENOMEM; |
441921d5 DV |
206 | r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); |
207 | if (unlikely(r)) { | |
208 | kfree(bo); | |
209 | return r; | |
210 | } | |
4c788679 | 211 | bo->rdev = rdev; |
4c788679 JG |
212 | bo->surface_reg = -1; |
213 | INIT_LIST_HEAD(&bo->list); | |
721604a1 | 214 | INIT_LIST_HEAD(&bo->va); |
bda72d58 MO |
215 | bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM | |
216 | RADEON_GEM_DOMAIN_GTT | | |
217 | RADEON_GEM_DOMAIN_CPU); | |
02376d82 MD |
218 | |
219 | bo->flags = flags; | |
220 | /* PCI GART is always snooped */ | |
221 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
222 | bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); | |
223 | ||
96ea47c0 MD |
224 | /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx |
225 | * See https://bugs.freedesktop.org/show_bug.cgi?id=91268 | |
226 | */ | |
227 | if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635) | |
228 | bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); | |
229 | ||
a08b588e MD |
230 | #ifdef CONFIG_X86_32 |
231 | /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit | |
232 | * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 | |
233 | */ | |
a28bbd58 | 234 | bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); |
a53fa438 MD |
235 | #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) |
236 | /* Don't try to enable write-combining when it can't work, or things | |
237 | * may be slow | |
238 | * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 | |
239 | */ | |
240 | ||
241 | #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ | |
242 | thanks to write-combining | |
243 | ||
93820498 MD |
244 | if (bo->flags & RADEON_GEM_GTT_WC) |
245 | DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " | |
246 | "better performance thanks to write-combining\n"); | |
a28bbd58 | 247 | bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); |
a08b588e MD |
248 | #endif |
249 | ||
1fb107fc | 250 | radeon_ttm_placement_from_domain(bo, domain); |
5cc6fbab | 251 | /* Kernel allocation are uninterruptible */ |
db7fce39 | 252 | down_read(&rdev->pm.mclk_lock); |
1fb107fc | 253 | r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, |
0b91c4a1 | 254 | &bo->placement, page_align, !kernel, NULL, |
831b6966 | 255 | acc_size, sg, resv, &radeon_ttm_bo_destroy); |
db7fce39 | 256 | up_read(&rdev->pm.mclk_lock); |
771fe6b9 | 257 | if (unlikely(r != 0)) { |
771fe6b9 JG |
258 | return r; |
259 | } | |
4c788679 | 260 | *bo_ptr = bo; |
441921d5 | 261 | |
99ee7fac | 262 | trace_radeon_bo_create(bo); |
441921d5 | 263 | |
771fe6b9 JG |
264 | return 0; |
265 | } | |
266 | ||
4c788679 | 267 | int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) |
771fe6b9 | 268 | { |
4c788679 | 269 | bool is_iomem; |
771fe6b9 JG |
270 | int r; |
271 | ||
4c788679 | 272 | if (bo->kptr) { |
771fe6b9 | 273 | if (ptr) { |
4c788679 | 274 | *ptr = bo->kptr; |
771fe6b9 | 275 | } |
771fe6b9 JG |
276 | return 0; |
277 | } | |
4c788679 | 278 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
771fe6b9 JG |
279 | if (r) { |
280 | return r; | |
281 | } | |
4c788679 | 282 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
771fe6b9 | 283 | if (ptr) { |
4c788679 | 284 | *ptr = bo->kptr; |
771fe6b9 | 285 | } |
4c788679 | 286 | radeon_bo_check_tiling(bo, 0, 0); |
771fe6b9 JG |
287 | return 0; |
288 | } | |
289 | ||
4c788679 | 290 | void radeon_bo_kunmap(struct radeon_bo *bo) |
771fe6b9 | 291 | { |
4c788679 | 292 | if (bo->kptr == NULL) |
771fe6b9 | 293 | return; |
4c788679 JG |
294 | bo->kptr = NULL; |
295 | radeon_bo_check_tiling(bo, 0, 0); | |
296 | ttm_bo_kunmap(&bo->kmap); | |
771fe6b9 JG |
297 | } |
298 | ||
512d8afc CK |
299 | struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo) |
300 | { | |
301 | if (bo == NULL) | |
302 | return NULL; | |
303 | ||
304 | ttm_bo_reference(&bo->tbo); | |
305 | return bo; | |
306 | } | |
307 | ||
4c788679 | 308 | void radeon_bo_unref(struct radeon_bo **bo) |
771fe6b9 | 309 | { |
4c788679 | 310 | struct ttm_buffer_object *tbo; |
f4b7fb94 | 311 | struct radeon_device *rdev; |
771fe6b9 | 312 | |
4c788679 | 313 | if ((*bo) == NULL) |
771fe6b9 | 314 | return; |
f4b7fb94 | 315 | rdev = (*bo)->rdev; |
4c788679 JG |
316 | tbo = &((*bo)->tbo); |
317 | ttm_bo_unref(&tbo); | |
318 | if (tbo == NULL) | |
319 | *bo = NULL; | |
771fe6b9 JG |
320 | } |
321 | ||
c4353016 MD |
322 | int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, |
323 | u64 *gpu_addr) | |
771fe6b9 | 324 | { |
312ea8da | 325 | int r, i; |
771fe6b9 | 326 | |
f72a113a CK |
327 | if (radeon_ttm_tt_has_userptr(bo->tbo.ttm)) |
328 | return -EPERM; | |
329 | ||
4c788679 JG |
330 | if (bo->pin_count) { |
331 | bo->pin_count++; | |
332 | if (gpu_addr) | |
333 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
d936622c MD |
334 | |
335 | if (max_offset != 0) { | |
336 | u64 domain_start; | |
337 | ||
338 | if (domain == RADEON_GEM_DOMAIN_VRAM) | |
339 | domain_start = bo->rdev->mc.vram_start; | |
340 | else | |
341 | domain_start = bo->rdev->mc.gtt_start; | |
e199fd42 MD |
342 | WARN_ON_ONCE(max_offset < |
343 | (radeon_bo_gpu_offset(bo) - domain_start)); | |
d936622c MD |
344 | } |
345 | ||
771fe6b9 JG |
346 | return 0; |
347 | } | |
312ea8da | 348 | radeon_ttm_placement_from_domain(bo, domain); |
f1217ed0 | 349 | for (i = 0; i < bo->placement.num_placement; i++) { |
3ca82da3 | 350 | /* force to pin into visible video ram */ |
b76ee67a | 351 | if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && |
f266f04d | 352 | !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) && |
b76ee67a MD |
353 | (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) |
354 | bo->placements[i].lpfn = | |
355 | bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
f1217ed0 | 356 | else |
b76ee67a | 357 | bo->placements[i].lpfn = max_offset >> PAGE_SHIFT; |
c4353016 | 358 | |
f1217ed0 | 359 | bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; |
c4353016 | 360 | } |
f1217ed0 | 361 | |
97a875cb | 362 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
4c788679 JG |
363 | if (likely(r == 0)) { |
364 | bo->pin_count = 1; | |
365 | if (gpu_addr != NULL) | |
366 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
71ecc97e AD |
367 | if (domain == RADEON_GEM_DOMAIN_VRAM) |
368 | bo->rdev->vram_pin_size += radeon_bo_size(bo); | |
369 | else | |
370 | bo->rdev->gart_pin_size += radeon_bo_size(bo); | |
371 | } else { | |
4c788679 | 372 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
71ecc97e | 373 | } |
771fe6b9 JG |
374 | return r; |
375 | } | |
c4353016 MD |
376 | |
377 | int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) | |
378 | { | |
379 | return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); | |
380 | } | |
771fe6b9 | 381 | |
4c788679 | 382 | int radeon_bo_unpin(struct radeon_bo *bo) |
771fe6b9 | 383 | { |
312ea8da | 384 | int r, i; |
771fe6b9 | 385 | |
4c788679 JG |
386 | if (!bo->pin_count) { |
387 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); | |
388 | return 0; | |
771fe6b9 | 389 | } |
4c788679 JG |
390 | bo->pin_count--; |
391 | if (bo->pin_count) | |
392 | return 0; | |
f1217ed0 CK |
393 | for (i = 0; i < bo->placement.num_placement; i++) { |
394 | bo->placements[i].lpfn = 0; | |
395 | bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; | |
396 | } | |
97a875cb | 397 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
71ecc97e AD |
398 | if (likely(r == 0)) { |
399 | if (bo->tbo.mem.mem_type == TTM_PL_VRAM) | |
400 | bo->rdev->vram_pin_size -= radeon_bo_size(bo); | |
401 | else | |
402 | bo->rdev->gart_pin_size -= radeon_bo_size(bo); | |
403 | } else { | |
4c788679 | 404 | dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); |
71ecc97e | 405 | } |
5cc6fbab | 406 | return r; |
cefb87ef DA |
407 | } |
408 | ||
4c788679 | 409 | int radeon_bo_evict_vram(struct radeon_device *rdev) |
771fe6b9 | 410 | { |
d796d844 DA |
411 | /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ |
412 | if (0 && (rdev->flags & RADEON_IS_IGP)) { | |
06b6476d AD |
413 | if (rdev->mc.igp_sideport_enabled == false) |
414 | /* Useless to evict on IGP chips */ | |
415 | return 0; | |
771fe6b9 JG |
416 | } |
417 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); | |
418 | } | |
419 | ||
4c788679 | 420 | void radeon_bo_force_delete(struct radeon_device *rdev) |
771fe6b9 | 421 | { |
4c788679 | 422 | struct radeon_bo *bo, *n; |
771fe6b9 JG |
423 | |
424 | if (list_empty(&rdev->gem.objects)) { | |
425 | return; | |
426 | } | |
4c788679 JG |
427 | dev_err(rdev->dev, "Userspace still has active objects !\n"); |
428 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { | |
4c788679 | 429 | dev_err(rdev->dev, "%p %p %lu %lu force free\n", |
31c3603d DV |
430 | &bo->gem_base, bo, (unsigned long)bo->gem_base.size, |
431 | *((unsigned long *)&bo->gem_base.refcount)); | |
4c788679 JG |
432 | mutex_lock(&bo->rdev->gem.mutex); |
433 | list_del_init(&bo->list); | |
434 | mutex_unlock(&bo->rdev->gem.mutex); | |
91132d6b | 435 | /* this should unref the ttm bo */ |
42192a94 | 436 | drm_gem_object_unreference_unlocked(&bo->gem_base); |
771fe6b9 JG |
437 | } |
438 | } | |
439 | ||
4c788679 | 440 | int radeon_bo_init(struct radeon_device *rdev) |
771fe6b9 | 441 | { |
a4d68279 | 442 | /* Add an MTRR for the VRAM */ |
a0a53aa8 | 443 | if (!rdev->fastfb_working) { |
07ebea25 AL |
444 | rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base, |
445 | rdev->mc.aper_size); | |
a0a53aa8 | 446 | } |
a4d68279 JG |
447 | DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", |
448 | rdev->mc.mc_vram_size >> 20, | |
449 | (unsigned long long)rdev->mc.aper_size >> 20); | |
450 | DRM_INFO("RAM width %dbits %cDR\n", | |
451 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); | |
771fe6b9 JG |
452 | return radeon_ttm_init(rdev); |
453 | } | |
454 | ||
4c788679 | 455 | void radeon_bo_fini(struct radeon_device *rdev) |
771fe6b9 JG |
456 | { |
457 | radeon_ttm_fini(rdev); | |
07ebea25 | 458 | arch_phys_wc_del(rdev->mc.vram_mtrr); |
771fe6b9 JG |
459 | } |
460 | ||
19dff56a MO |
461 | /* Returns how many bytes TTM can move per IB. |
462 | */ | |
463 | static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev) | |
464 | { | |
465 | u64 real_vram_size = rdev->mc.real_vram_size; | |
466 | u64 vram_usage = atomic64_read(&rdev->vram_usage); | |
467 | ||
468 | /* This function is based on the current VRAM usage. | |
469 | * | |
470 | * - If all of VRAM is free, allow relocating the number of bytes that | |
471 | * is equal to 1/4 of the size of VRAM for this IB. | |
472 | ||
473 | * - If more than one half of VRAM is occupied, only allow relocating | |
474 | * 1 MB of data for this IB. | |
475 | * | |
476 | * - From 0 to one half of used VRAM, the threshold decreases | |
477 | * linearly. | |
478 | * __________________ | |
479 | * 1/4 of -|\ | | |
480 | * VRAM | \ | | |
481 | * | \ | | |
482 | * | \ | | |
483 | * | \ | | |
484 | * | \ | | |
485 | * | \ | | |
486 | * | \________|1 MB | |
487 | * |----------------| | |
488 | * VRAM 0 % 100 % | |
489 | * used used | |
490 | * | |
491 | * Note: It's a threshold, not a limit. The threshold must be crossed | |
492 | * for buffer relocations to stop, so any buffer of an arbitrary size | |
493 | * can be moved as long as the threshold isn't crossed before | |
494 | * the relocation takes place. We don't want to disable buffer | |
495 | * relocations completely. | |
496 | * | |
497 | * The idea is that buffers should be placed in VRAM at creation time | |
498 | * and TTM should only do a minimum number of relocations during | |
499 | * command submission. In practice, you need to submit at least | |
500 | * a dozen IBs to move all buffers to VRAM if they are in GTT. | |
501 | * | |
502 | * Also, things can get pretty crazy under memory pressure and actual | |
503 | * VRAM usage can change a lot, so playing safe even at 50% does | |
504 | * consistently increase performance. | |
505 | */ | |
506 | ||
507 | u64 half_vram = real_vram_size >> 1; | |
508 | u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; | |
509 | u64 bytes_moved_threshold = half_free_vram >> 1; | |
510 | return max(bytes_moved_threshold, 1024*1024ull); | |
511 | } | |
512 | ||
513 | int radeon_bo_list_validate(struct radeon_device *rdev, | |
514 | struct ww_acquire_ctx *ticket, | |
ecff665f | 515 | struct list_head *head, int ring) |
771fe6b9 | 516 | { |
1d0c0942 | 517 | struct radeon_bo_list *lobj; |
466be338 | 518 | struct list_head duplicates; |
771fe6b9 | 519 | int r; |
19dff56a MO |
520 | u64 bytes_moved = 0, initial_bytes_moved; |
521 | u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev); | |
771fe6b9 | 522 | |
466be338 CK |
523 | INIT_LIST_HEAD(&duplicates); |
524 | r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates); | |
771fe6b9 | 525 | if (unlikely(r != 0)) { |
771fe6b9 JG |
526 | return r; |
527 | } | |
19dff56a | 528 | |
147666fb | 529 | list_for_each_entry(lobj, head, tv.head) { |
466be338 | 530 | struct radeon_bo *bo = lobj->robj; |
4c788679 | 531 | if (!bo->pin_count) { |
ce6758c8 | 532 | u32 domain = lobj->prefered_domains; |
3852752c | 533 | u32 allowed = lobj->allowed_domains; |
19dff56a MO |
534 | u32 current_domain = |
535 | radeon_mem_type_to_domain(bo->tbo.mem.mem_type); | |
536 | ||
537 | /* Check if this buffer will be moved and don't move it | |
538 | * if we have moved too many buffers for this IB already. | |
539 | * | |
540 | * Note that this allows moving at least one buffer of | |
541 | * any size, because it doesn't take the current "bo" | |
542 | * into account. We don't want to disallow buffer moves | |
543 | * completely. | |
544 | */ | |
3852752c | 545 | if ((allowed & current_domain) != 0 && |
19dff56a MO |
546 | (domain & current_domain) == 0 && /* will be moved */ |
547 | bytes_moved > bytes_moved_threshold) { | |
548 | /* don't move it */ | |
549 | domain = current_domain; | |
550 | } | |
551 | ||
20707874 AD |
552 | retry: |
553 | radeon_ttm_placement_from_domain(bo, domain); | |
f2ba57b5 | 554 | if (ring == R600_RING_TYPE_UVD_INDEX) |
3852752c | 555 | radeon_uvd_force_into_uvd_segment(bo, allowed); |
19dff56a MO |
556 | |
557 | initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved); | |
558 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
559 | bytes_moved += atomic64_read(&rdev->num_bytes_moved) - | |
560 | initial_bytes_moved; | |
561 | ||
e376573f | 562 | if (unlikely(r)) { |
ce6758c8 CK |
563 | if (r != -ERESTARTSYS && |
564 | domain != lobj->allowed_domains) { | |
565 | domain = lobj->allowed_domains; | |
20707874 AD |
566 | goto retry; |
567 | } | |
1b6e5fd5 | 568 | ttm_eu_backoff_reservation(ticket, head); |
771fe6b9 | 569 | return r; |
e376573f | 570 | } |
771fe6b9 | 571 | } |
4c788679 JG |
572 | lobj->gpu_offset = radeon_bo_gpu_offset(bo); |
573 | lobj->tiling_flags = bo->tiling_flags; | |
771fe6b9 | 574 | } |
466be338 CK |
575 | |
576 | list_for_each_entry(lobj, &duplicates, tv.head) { | |
577 | lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj); | |
578 | lobj->tiling_flags = lobj->robj->tiling_flags; | |
579 | } | |
580 | ||
771fe6b9 JG |
581 | return 0; |
582 | } | |
583 | ||
550e2d92 | 584 | int radeon_bo_get_surface_reg(struct radeon_bo *bo) |
771fe6b9 | 585 | { |
4c788679 | 586 | struct radeon_device *rdev = bo->rdev; |
e024e110 | 587 | struct radeon_surface_reg *reg; |
4c788679 | 588 | struct radeon_bo *old_object; |
e024e110 DA |
589 | int steal; |
590 | int i; | |
591 | ||
977c38d5 | 592 | lockdep_assert_held(&bo->tbo.resv->lock.base); |
4c788679 JG |
593 | |
594 | if (!bo->tiling_flags) | |
e024e110 DA |
595 | return 0; |
596 | ||
4c788679 JG |
597 | if (bo->surface_reg >= 0) { |
598 | reg = &rdev->surface_regs[bo->surface_reg]; | |
599 | i = bo->surface_reg; | |
e024e110 DA |
600 | goto out; |
601 | } | |
602 | ||
603 | steal = -1; | |
604 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { | |
605 | ||
606 | reg = &rdev->surface_regs[i]; | |
4c788679 | 607 | if (!reg->bo) |
e024e110 DA |
608 | break; |
609 | ||
4c788679 | 610 | old_object = reg->bo; |
e024e110 DA |
611 | if (old_object->pin_count == 0) |
612 | steal = i; | |
613 | } | |
614 | ||
615 | /* if we are all out */ | |
616 | if (i == RADEON_GEM_MAX_SURFACES) { | |
617 | if (steal == -1) | |
618 | return -ENOMEM; | |
619 | /* find someone with a surface reg and nuke their BO */ | |
620 | reg = &rdev->surface_regs[steal]; | |
4c788679 | 621 | old_object = reg->bo; |
e024e110 DA |
622 | /* blow away the mapping */ |
623 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); | |
4c788679 | 624 | ttm_bo_unmap_virtual(&old_object->tbo); |
e024e110 DA |
625 | old_object->surface_reg = -1; |
626 | i = steal; | |
627 | } | |
628 | ||
4c788679 JG |
629 | bo->surface_reg = i; |
630 | reg->bo = bo; | |
e024e110 DA |
631 | |
632 | out: | |
4c788679 | 633 | radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, |
d961db75 | 634 | bo->tbo.mem.start << PAGE_SHIFT, |
4c788679 | 635 | bo->tbo.num_pages << PAGE_SHIFT); |
e024e110 DA |
636 | return 0; |
637 | } | |
638 | ||
4c788679 | 639 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) |
e024e110 | 640 | { |
4c788679 | 641 | struct radeon_device *rdev = bo->rdev; |
e024e110 DA |
642 | struct radeon_surface_reg *reg; |
643 | ||
4c788679 | 644 | if (bo->surface_reg == -1) |
e024e110 DA |
645 | return; |
646 | ||
4c788679 JG |
647 | reg = &rdev->surface_regs[bo->surface_reg]; |
648 | radeon_clear_surface_reg(rdev, bo->surface_reg); | |
e024e110 | 649 | |
4c788679 JG |
650 | reg->bo = NULL; |
651 | bo->surface_reg = -1; | |
e024e110 DA |
652 | } |
653 | ||
4c788679 JG |
654 | int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
655 | uint32_t tiling_flags, uint32_t pitch) | |
e024e110 | 656 | { |
285484e2 | 657 | struct radeon_device *rdev = bo->rdev; |
4c788679 JG |
658 | int r; |
659 | ||
285484e2 JG |
660 | if (rdev->family >= CHIP_CEDAR) { |
661 | unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; | |
662 | ||
663 | bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; | |
664 | bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; | |
665 | mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; | |
666 | tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; | |
667 | stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; | |
668 | switch (bankw) { | |
669 | case 0: | |
670 | case 1: | |
671 | case 2: | |
672 | case 4: | |
673 | case 8: | |
674 | break; | |
675 | default: | |
676 | return -EINVAL; | |
677 | } | |
678 | switch (bankh) { | |
679 | case 0: | |
680 | case 1: | |
681 | case 2: | |
682 | case 4: | |
683 | case 8: | |
684 | break; | |
685 | default: | |
686 | return -EINVAL; | |
687 | } | |
688 | switch (mtaspect) { | |
689 | case 0: | |
690 | case 1: | |
691 | case 2: | |
692 | case 4: | |
693 | case 8: | |
694 | break; | |
695 | default: | |
696 | return -EINVAL; | |
697 | } | |
698 | if (tilesplit > 6) { | |
699 | return -EINVAL; | |
700 | } | |
701 | if (stilesplit > 6) { | |
702 | return -EINVAL; | |
703 | } | |
704 | } | |
4c788679 JG |
705 | r = radeon_bo_reserve(bo, false); |
706 | if (unlikely(r != 0)) | |
707 | return r; | |
708 | bo->tiling_flags = tiling_flags; | |
709 | bo->pitch = pitch; | |
710 | radeon_bo_unreserve(bo); | |
711 | return 0; | |
e024e110 DA |
712 | } |
713 | ||
4c788679 JG |
714 | void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
715 | uint32_t *tiling_flags, | |
716 | uint32_t *pitch) | |
e024e110 | 717 | { |
977c38d5 ML |
718 | lockdep_assert_held(&bo->tbo.resv->lock.base); |
719 | ||
e024e110 | 720 | if (tiling_flags) |
4c788679 | 721 | *tiling_flags = bo->tiling_flags; |
e024e110 | 722 | if (pitch) |
4c788679 | 723 | *pitch = bo->pitch; |
e024e110 DA |
724 | } |
725 | ||
4c788679 JG |
726 | int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
727 | bool force_drop) | |
e024e110 | 728 | { |
977c38d5 ML |
729 | if (!force_drop) |
730 | lockdep_assert_held(&bo->tbo.resv->lock.base); | |
4c788679 JG |
731 | |
732 | if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) | |
e024e110 DA |
733 | return 0; |
734 | ||
735 | if (force_drop) { | |
4c788679 | 736 | radeon_bo_clear_surface_reg(bo); |
e024e110 DA |
737 | return 0; |
738 | } | |
739 | ||
4c788679 | 740 | if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { |
e024e110 DA |
741 | if (!has_moved) |
742 | return 0; | |
743 | ||
4c788679 JG |
744 | if (bo->surface_reg >= 0) |
745 | radeon_bo_clear_surface_reg(bo); | |
e024e110 DA |
746 | return 0; |
747 | } | |
748 | ||
4c788679 | 749 | if ((bo->surface_reg >= 0) && !has_moved) |
e024e110 DA |
750 | return 0; |
751 | ||
4c788679 | 752 | return radeon_bo_get_surface_reg(bo); |
e024e110 DA |
753 | } |
754 | ||
755 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, | |
67e8e3f9 | 756 | struct ttm_mem_reg *new_mem) |
e024e110 | 757 | { |
d03d8589 | 758 | struct radeon_bo *rbo; |
67e8e3f9 | 759 | |
d03d8589 JG |
760 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
761 | return; | |
67e8e3f9 | 762 | |
d03d8589 | 763 | rbo = container_of(bo, struct radeon_bo, tbo); |
4c788679 | 764 | radeon_bo_check_tiling(rbo, 0, 1); |
721604a1 | 765 | radeon_vm_bo_invalidate(rbo->rdev, rbo); |
67e8e3f9 MO |
766 | |
767 | /* update statistics */ | |
768 | if (!new_mem) | |
769 | return; | |
770 | ||
771 | radeon_update_memory_usage(rbo, bo->mem.mem_type, -1); | |
772 | radeon_update_memory_usage(rbo, new_mem->mem_type, 1); | |
e024e110 DA |
773 | } |
774 | ||
0a2d50e3 | 775 | int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) |
e024e110 | 776 | { |
0a2d50e3 | 777 | struct radeon_device *rdev; |
d03d8589 | 778 | struct radeon_bo *rbo; |
c9da4a4b MD |
779 | unsigned long offset, size, lpfn; |
780 | int i, r; | |
0a2d50e3 | 781 | |
d03d8589 | 782 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
0a2d50e3 | 783 | return 0; |
d03d8589 | 784 | rbo = container_of(bo, struct radeon_bo, tbo); |
4c788679 | 785 | radeon_bo_check_tiling(rbo, 0, 0); |
0a2d50e3 | 786 | rdev = rbo->rdev; |
54409259 CK |
787 | if (bo->mem.mem_type != TTM_PL_VRAM) |
788 | return 0; | |
789 | ||
790 | size = bo->mem.num_pages << PAGE_SHIFT; | |
791 | offset = bo->mem.start << PAGE_SHIFT; | |
792 | if ((offset + size) <= rdev->mc.visible_vram_size) | |
793 | return 0; | |
794 | ||
795 | /* hurrah the memory is not visible ! */ | |
796 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); | |
c9da4a4b MD |
797 | lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; |
798 | for (i = 0; i < rbo->placement.num_placement; i++) { | |
799 | /* Force into visible VRAM */ | |
800 | if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && | |
801 | (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn)) | |
802 | rbo->placements[i].lpfn = lpfn; | |
803 | } | |
54409259 CK |
804 | r = ttm_bo_validate(bo, &rbo->placement, false, false); |
805 | if (unlikely(r == -ENOMEM)) { | |
806 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); | |
807 | return ttm_bo_validate(bo, &rbo->placement, false, false); | |
808 | } else if (unlikely(r != 0)) { | |
809 | return r; | |
0a2d50e3 | 810 | } |
54409259 CK |
811 | |
812 | offset = bo->mem.start << PAGE_SHIFT; | |
813 | /* this should never happen */ | |
814 | if ((offset + size) > rdev->mc.visible_vram_size) | |
815 | return -EINVAL; | |
816 | ||
0a2d50e3 | 817 | return 0; |
e024e110 | 818 | } |
ce580fab | 819 | |
83f30d0e | 820 | int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) |
ce580fab AK |
821 | { |
822 | int r; | |
823 | ||
12432354 | 824 | r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL); |
ce580fab AK |
825 | if (unlikely(r != 0)) |
826 | return r; | |
ce580fab AK |
827 | if (mem_type) |
828 | *mem_type = bo->tbo.mem.mem_type; | |
f2c24b83 ML |
829 | |
830 | r = ttm_bo_wait(&bo->tbo, true, true, no_wait); | |
ce580fab AK |
831 | ttm_bo_unreserve(&bo->tbo); |
832 | return r; | |
833 | } | |
587cdda8 CK |
834 | |
835 | /** | |
836 | * radeon_bo_fence - add fence to buffer object | |
837 | * | |
838 | * @bo: buffer object in question | |
839 | * @fence: fence to add | |
840 | * @shared: true if fence should be added shared | |
841 | * | |
842 | */ | |
843 | void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence, | |
844 | bool shared) | |
845 | { | |
846 | struct reservation_object *resv = bo->tbo.resv; | |
847 | ||
848 | if (shared) | |
849 | reservation_object_add_shared_fence(resv, &fence->base); | |
850 | else | |
851 | reservation_object_add_excl_fence(resv, &fence->base); | |
852 | } |