drm/radeon: separate UVD code v3
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_ucode.h
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1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __RADEON_UCODE_H__
24#define __RADEON_UCODE_H__
25
26/* CP */
27#define R600_PFP_UCODE_SIZE 576
28#define R600_PM4_UCODE_SIZE 1792
29#define R700_PFP_UCODE_SIZE 848
30#define R700_PM4_UCODE_SIZE 1360
31#define EVERGREEN_PFP_UCODE_SIZE 1120
32#define EVERGREEN_PM4_UCODE_SIZE 1376
33#define CAYMAN_PFP_UCODE_SIZE 2176
34#define CAYMAN_PM4_UCODE_SIZE 2176
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35#define SI_PFP_UCODE_SIZE 2144
36#define SI_PM4_UCODE_SIZE 2144
37#define SI_CE_UCODE_SIZE 2144
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38#define CIK_PFP_UCODE_SIZE 2144
39#define CIK_ME_UCODE_SIZE 2144
40#define CIK_CE_UCODE_SIZE 2144
41
42/* MEC */
43#define CIK_MEC_UCODE_SIZE 4192
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44
45/* RLC */
46#define R600_RLC_UCODE_SIZE 768
47#define R700_RLC_UCODE_SIZE 1024
48#define EVERGREEN_RLC_UCODE_SIZE 768
49#define CAYMAN_RLC_UCODE_SIZE 1024
50#define ARUBA_RLC_UCODE_SIZE 1536
a0ceada6 51#define SI_RLC_UCODE_SIZE 2048
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52#define BONAIRE_RLC_UCODE_SIZE 2048
53#define KB_RLC_UCODE_SIZE 2560
54#define KV_RLC_UCODE_SIZE 2560
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55
56/* MC */
57#define BTC_MC_UCODE_SIZE 6024
58#define CAYMAN_MC_UCODE_SIZE 6037
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59#define SI_MC_UCODE_SIZE 7769
60#define OLAND_MC_UCODE_SIZE 7863
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61#define CIK_MC_UCODE_SIZE 7866
62
63/* SDMA */
64#define CIK_SDMA_UCODE_SIZE 1050
65#define CIK_SDMA_UCODE_VERSION 64
138e4e16 66
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67/* SMC */
68#define RV770_SMC_UCODE_START 0x0100
69#define RV770_SMC_UCODE_SIZE 0x410d
70#define RV770_SMC_INT_VECTOR_START 0xffc0
71#define RV770_SMC_INT_VECTOR_SIZE 0x0040
72
73#define RV730_SMC_UCODE_START 0x0100
74#define RV730_SMC_UCODE_SIZE 0x412c
75#define RV730_SMC_INT_VECTOR_START 0xffc0
76#define RV730_SMC_INT_VECTOR_SIZE 0x0040
77
78#define RV710_SMC_UCODE_START 0x0100
79#define RV710_SMC_UCODE_SIZE 0x3f1f
80#define RV710_SMC_INT_VECTOR_START 0xffc0
81#define RV710_SMC_INT_VECTOR_SIZE 0x0040
82
83#define RV740_SMC_UCODE_START 0x0100
84#define RV740_SMC_UCODE_SIZE 0x41c5
85#define RV740_SMC_INT_VECTOR_START 0xffc0
86#define RV740_SMC_INT_VECTOR_SIZE 0x0040
87
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88#define CEDAR_SMC_UCODE_START 0x0100
89#define CEDAR_SMC_UCODE_SIZE 0x5d50
90#define CEDAR_SMC_INT_VECTOR_START 0xffc0
91#define CEDAR_SMC_INT_VECTOR_SIZE 0x0040
92
93#define REDWOOD_SMC_UCODE_START 0x0100
94#define REDWOOD_SMC_UCODE_SIZE 0x5f0a
95#define REDWOOD_SMC_INT_VECTOR_START 0xffc0
96#define REDWOOD_SMC_INT_VECTOR_SIZE 0x0040
97
98#define JUNIPER_SMC_UCODE_START 0x0100
99#define JUNIPER_SMC_UCODE_SIZE 0x5f1f
100#define JUNIPER_SMC_INT_VECTOR_START 0xffc0
101#define JUNIPER_SMC_INT_VECTOR_SIZE 0x0040
102
103#define CYPRESS_SMC_UCODE_START 0x0100
104#define CYPRESS_SMC_UCODE_SIZE 0x61f7
105#define CYPRESS_SMC_INT_VECTOR_START 0xffc0
106#define CYPRESS_SMC_INT_VECTOR_SIZE 0x0040
107
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108#define BARTS_SMC_UCODE_START 0x0100
109#define BARTS_SMC_UCODE_SIZE 0x6107
110#define BARTS_SMC_INT_VECTOR_START 0xffc0
111#define BARTS_SMC_INT_VECTOR_SIZE 0x0040
112
113#define TURKS_SMC_UCODE_START 0x0100
114#define TURKS_SMC_UCODE_SIZE 0x605b
115#define TURKS_SMC_INT_VECTOR_START 0xffc0
116#define TURKS_SMC_INT_VECTOR_SIZE 0x0040
117
118#define CAICOS_SMC_UCODE_START 0x0100
119#define CAICOS_SMC_UCODE_SIZE 0x5fbd
120#define CAICOS_SMC_INT_VECTOR_START 0xffc0
121#define CAICOS_SMC_INT_VECTOR_SIZE 0x0040
122
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123#define CAYMAN_SMC_UCODE_START 0x0100
124#define CAYMAN_SMC_UCODE_SIZE 0x79ec
125#define CAYMAN_SMC_INT_VECTOR_START 0xffc0
126#define CAYMAN_SMC_INT_VECTOR_SIZE 0x0040
127
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128#define TAHITI_SMC_UCODE_START 0x10000
129#define TAHITI_SMC_UCODE_SIZE 0xf458
130
131#define PITCAIRN_SMC_UCODE_START 0x10000
132#define PITCAIRN_SMC_UCODE_SIZE 0xe9f4
133
134#define VERDE_SMC_UCODE_START 0x10000
135#define VERDE_SMC_UCODE_SIZE 0xebe4
136
137#define OLAND_SMC_UCODE_START 0x10000
138#define OLAND_SMC_UCODE_SIZE 0xe7b4
139
140#define HAINAN_SMC_UCODE_START 0x10000
141#define HAINAN_SMC_UCODE_SIZE 0xe67C
142
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143#define BONAIRE_SMC_UCODE_START 0x20000
144#define BONAIRE_SMC_UCODE_SIZE 0x1FDEC
145
138e4e16 146#endif
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