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1 | /* |
2 | * Copyright 2011 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #ifndef __RS780D_H__ | |
24 | #define __RS780D_H__ | |
25 | ||
26 | #define CG_SPLL_FUNC_CNTL 0x600 | |
27 | # define SPLL_RESET (1 << 0) | |
28 | # define SPLL_SLEEP (1 << 1) | |
29 | # define SPLL_REF_DIV(x) ((x) << 2) | |
30 | # define SPLL_REF_DIV_MASK (7 << 2) | |
444bddc4 | 31 | # define SPLL_REF_DIV_SHIFT 2 |
9d67006e AD |
32 | # define SPLL_FB_DIV(x) ((x) << 5) |
33 | # define SPLL_FB_DIV_MASK (0xff << 2) | |
34 | # define SPLL_FB_DIV_SHIFT 2 | |
35 | # define SPLL_PULSEEN (1 << 13) | |
36 | # define SPLL_PULSENUM(x) ((x) << 14) | |
37 | # define SPLL_PULSENUM_MASK (3 << 14) | |
38 | # define SPLL_SW_HILEN(x) ((x) << 16) | |
39 | # define SPLL_SW_HILEN_MASK (0xf << 16) | |
444bddc4 | 40 | # define SPLL_SW_HILEN_SHIFT 16 |
9d67006e AD |
41 | # define SPLL_SW_LOLEN(x) ((x) << 20) |
42 | # define SPLL_SW_LOLEN_MASK (0xf << 20) | |
444bddc4 | 43 | # define SPLL_SW_LOLEN_SHIFT 20 |
9d67006e AD |
44 | # define SPLL_DIVEN (1 << 24) |
45 | # define SPLL_BYPASS_EN (1 << 25) | |
46 | # define SPLL_CHG_STATUS (1 << 29) | |
47 | # define SPLL_CTLREQ (1 << 30) | |
48 | # define SPLL_CTLACK (1 << 31) | |
49 | ||
50 | /* RS780/RS880 PM */ | |
51 | #define FVTHROT_CNTRL_REG 0x3000 | |
52 | #define DONT_WAIT_FOR_FBDIV_WRAP (1 << 0) | |
53 | #define MINIMUM_CIP(x) ((x) << 1) | |
54 | #define MINIMUM_CIP_SHIFT 1 | |
55 | #define MINIMUM_CIP_MASK 0x1fffffe | |
56 | #define REFRESH_RATE_DIVISOR(x) ((x) << 25) | |
57 | #define REFRESH_RATE_DIVISOR_SHIFT 25 | |
58 | #define REFRESH_RATE_DIVISOR_MASK (0x3 << 25) | |
59 | #define ENABLE_FV_THROT (1 << 27) | |
60 | #define ENABLE_FV_UPDATE (1 << 28) | |
61 | #define TREND_SEL_MODE (1 << 29) | |
62 | #define FORCE_TREND_SEL (1 << 30) | |
63 | #define ENABLE_FV_THROT_IO (1 << 31) | |
64 | #define FVTHROT_TARGET_REG 0x3004 | |
65 | #define TARGET_IDLE_COUNT(x) ((x) << 0) | |
66 | #define TARGET_IDLE_COUNT_MASK 0xffffff | |
67 | #define TARGET_IDLE_COUNT_SHIFT 0 | |
68 | #define FVTHROT_CB1 0x3008 | |
69 | #define FVTHROT_CB2 0x300c | |
70 | #define FVTHROT_CB3 0x3010 | |
71 | #define FVTHROT_CB4 0x3014 | |
72 | #define FVTHROT_UTC0 0x3018 | |
73 | #define FVTHROT_UTC1 0x301c | |
74 | #define FVTHROT_UTC2 0x3020 | |
75 | #define FVTHROT_UTC3 0x3024 | |
76 | #define FVTHROT_UTC4 0x3028 | |
77 | #define FVTHROT_DTC0 0x302c | |
78 | #define FVTHROT_DTC1 0x3030 | |
79 | #define FVTHROT_DTC2 0x3034 | |
80 | #define FVTHROT_DTC3 0x3038 | |
81 | #define FVTHROT_DTC4 0x303c | |
82 | #define FVTHROT_FBDIV_REG0 0x3040 | |
83 | #define MIN_FEEDBACK_DIV(x) ((x) << 0) | |
84 | #define MIN_FEEDBACK_DIV_MASK 0xfff | |
85 | #define MIN_FEEDBACK_DIV_SHIFT 0 | |
86 | #define MAX_FEEDBACK_DIV(x) ((x) << 12) | |
87 | #define MAX_FEEDBACK_DIV_MASK (0xfff << 12) | |
88 | #define MAX_FEEDBACK_DIV_SHIFT 12 | |
89 | #define FVTHROT_FBDIV_REG1 0x3044 | |
90 | #define MAX_FEEDBACK_STEP(x) ((x) << 0) | |
91 | #define MAX_FEEDBACK_STEP_MASK 0xfff | |
92 | #define MAX_FEEDBACK_STEP_SHIFT 0 | |
93 | #define STARTING_FEEDBACK_DIV(x) ((x) << 12) | |
94 | #define STARTING_FEEDBACK_DIV_MASK (0xfff << 12) | |
95 | #define STARTING_FEEDBACK_DIV_SHIFT 12 | |
96 | #define FORCE_FEEDBACK_DIV (1 << 24) | |
97 | #define FVTHROT_FBDIV_REG2 0x3048 | |
98 | #define FORCED_FEEDBACK_DIV(x) ((x) << 0) | |
99 | #define FORCED_FEEDBACK_DIV_MASK 0xfff | |
100 | #define FORCED_FEEDBACK_DIV_SHIFT 0 | |
101 | #define FB_DIV_TIMER_VAL(x) ((x) << 12) | |
102 | #define FB_DIV_TIMER_VAL_MASK (0xffff << 12) | |
103 | #define FB_DIV_TIMER_VAL_SHIFT 12 | |
104 | #define FVTHROT_FB_US_REG0 0x304c | |
105 | #define FVTHROT_FB_US_REG1 0x3050 | |
106 | #define FVTHROT_FB_DS_REG0 0x3054 | |
107 | #define FVTHROT_FB_DS_REG1 0x3058 | |
108 | #define FVTHROT_PWM_CTRL_REG0 0x305c | |
109 | #define STARTING_PWM_HIGHTIME(x) ((x) << 0) | |
110 | #define STARTING_PWM_HIGHTIME_MASK 0xfff | |
111 | #define STARTING_PWM_HIGHTIME_SHIFT 0 | |
112 | #define NUMBER_OF_CYCLES_IN_PERIOD(x) ((x) << 12) | |
113 | #define NUMBER_OF_CYCLES_IN_PERIOD_MASK (0xfff << 12) | |
114 | #define NUMBER_OF_CYCLES_IN_PERIOD_SHIFT 12 | |
115 | #define FORCE_STARTING_PWM_HIGHTIME (1 << 24) | |
116 | #define INVERT_PWM_WAVEFORM (1 << 25) | |
117 | #define FVTHROT_PWM_CTRL_REG1 0x3060 | |
118 | #define MIN_PWM_HIGHTIME(x) ((x) << 0) | |
119 | #define MIN_PWM_HIGHTIME_MASK 0xfff | |
120 | #define MIN_PWM_HIGHTIME_SHIFT 0 | |
121 | #define MAX_PWM_HIGHTIME(x) ((x) << 12) | |
122 | #define MAX_PWM_HIGHTIME_MASK (0xfff << 12) | |
123 | #define MAX_PWM_HIGHTIME_SHIFT 12 | |
124 | #define FVTHROT_PWM_US_REG0 0x3064 | |
125 | #define FVTHROT_PWM_US_REG1 0x3068 | |
126 | #define FVTHROT_PWM_DS_REG0 0x306c | |
127 | #define FVTHROT_PWM_DS_REG1 0x3070 | |
128 | #define FVTHROT_STATUS_REG0 0x3074 | |
129 | #define CURRENT_FEEDBACK_DIV_MASK 0xfff | |
130 | #define CURRENT_FEEDBACK_DIV_SHIFT 0 | |
131 | #define FVTHROT_STATUS_REG1 0x3078 | |
132 | #define FVTHROT_STATUS_REG2 0x307c | |
133 | #define CG_INTGFX_MISC 0x3080 | |
134 | #define FVTHROT_VBLANK_SEL (1 << 9) | |
135 | #define FVTHROT_PWM_FEEDBACK_DIV_REG1 0x308c | |
136 | #define RANGE0_PWM_FEEDBACK_DIV(x) ((x) << 0) | |
137 | #define RANGE0_PWM_FEEDBACK_DIV_MASK 0xfff | |
138 | #define RANGE0_PWM_FEEDBACK_DIV_SHIFT 0 | |
139 | #define RANGE_PWM_FEEDBACK_DIV_EN (1 << 12) | |
140 | #define FVTHROT_PWM_FEEDBACK_DIV_REG2 0x3090 | |
141 | #define RANGE1_PWM_FEEDBACK_DIV(x) ((x) << 0) | |
142 | #define RANGE1_PWM_FEEDBACK_DIV_MASK 0xfff | |
143 | #define RANGE1_PWM_FEEDBACK_DIV_SHIFT 0 | |
144 | #define RANGE2_PWM_FEEDBACK_DIV(x) ((x) << 12) | |
145 | #define RANGE2_PWM_FEEDBACK_DIV_MASK (0xfff << 12) | |
146 | #define RANGE2_PWM_FEEDBACK_DIV_SHIFT 12 | |
147 | #define FVTHROT_PWM_FEEDBACK_DIV_REG3 0x3094 | |
148 | #define RANGE0_PWM(x) ((x) << 0) | |
149 | #define RANGE0_PWM_MASK 0xfff | |
150 | #define RANGE0_PWM_SHIFT 0 | |
151 | #define RANGE1_PWM(x) ((x) << 12) | |
152 | #define RANGE1_PWM_MASK (0xfff << 12) | |
153 | #define RANGE1_PWM_SHIFT 12 | |
154 | #define FVTHROT_PWM_FEEDBACK_DIV_REG4 0x3098 | |
155 | #define RANGE2_PWM(x) ((x) << 0) | |
156 | #define RANGE2_PWM_MASK 0xfff | |
157 | #define RANGE2_PWM_SHIFT 0 | |
158 | #define RANGE3_PWM(x) ((x) << 12) | |
159 | #define RANGE3_PWM_MASK (0xfff << 12) | |
160 | #define RANGE3_PWM_SHIFT 12 | |
161 | #define FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1 0x30ac | |
162 | #define RANGE0_SLOW_CLK_FEEDBACK_DIV(x) ((x) << 0) | |
163 | #define RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK 0xfff | |
164 | #define RANGE0_SLOW_CLK_FEEDBACK_DIV_SHIFT 0 | |
165 | #define RANGE_SLOW_CLK_FEEDBACK_DIV_EN (1 << 12) | |
166 | ||
167 | #define GFX_MACRO_BYPASS_CNTL 0x30c0 | |
168 | #define SPLL_BYPASS_CNTL (1 << 0) | |
169 | #define UPLL_BYPASS_CNTL (1 << 1) | |
170 | ||
171 | #endif |