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1 | /* |
2 | * Copyright 2011 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #ifndef RV730_H | |
24 | #define RV730_H | |
25 | ||
26 | #define CG_SPLL_FUNC_CNTL 0x600 | |
27 | #define SPLL_RESET (1 << 0) | |
28 | #define SPLL_SLEEP (1 << 1) | |
29 | #define SPLL_DIVEN (1 << 2) | |
30 | #define SPLL_BYPASS_EN (1 << 3) | |
31 | #define SPLL_REF_DIV(x) ((x) << 4) | |
32 | #define SPLL_REF_DIV_MASK (0x3f << 4) | |
33 | #define SPLL_HILEN(x) ((x) << 12) | |
34 | #define SPLL_HILEN_MASK (0xf << 12) | |
35 | #define SPLL_LOLEN(x) ((x) << 16) | |
36 | #define SPLL_LOLEN_MASK (0xf << 16) | |
37 | #define CG_SPLL_FUNC_CNTL_2 0x604 | |
38 | #define SCLK_MUX_SEL(x) ((x) << 0) | |
39 | #define SCLK_MUX_SEL_MASK (0x1ff << 0) | |
40 | #define CG_SPLL_FUNC_CNTL_3 0x608 | |
41 | #define SPLL_FB_DIV(x) ((x) << 0) | |
42 | #define SPLL_FB_DIV_MASK (0x3ffffff << 0) | |
43 | #define SPLL_DITHEN (1 << 28) | |
44 | ||
45 | #define CG_MPLL_FUNC_CNTL 0x624 | |
46 | #define MPLL_RESET (1 << 0) | |
47 | #define MPLL_SLEEP (1 << 1) | |
48 | #define MPLL_DIVEN (1 << 2) | |
49 | #define MPLL_BYPASS_EN (1 << 3) | |
50 | #define MPLL_REF_DIV(x) ((x) << 4) | |
51 | #define MPLL_REF_DIV_MASK (0x3f << 4) | |
52 | #define MPLL_HILEN(x) ((x) << 12) | |
53 | #define MPLL_HILEN_MASK (0xf << 12) | |
54 | #define MPLL_LOLEN(x) ((x) << 16) | |
55 | #define MPLL_LOLEN_MASK (0xf << 16) | |
56 | #define CG_MPLL_FUNC_CNTL_2 0x628 | |
57 | #define MCLK_MUX_SEL(x) ((x) << 0) | |
58 | #define MCLK_MUX_SEL_MASK (0x1ff << 0) | |
59 | #define CG_MPLL_FUNC_CNTL_3 0x62c | |
60 | #define MPLL_FB_DIV(x) ((x) << 0) | |
61 | #define MPLL_FB_DIV_MASK (0x3ffffff << 0) | |
62 | #define MPLL_DITHEN (1 << 28) | |
63 | ||
64 | #define CG_TCI_MPLL_SPREAD_SPECTRUM 0x634 | |
65 | #define CG_TCI_MPLL_SPREAD_SPECTRUM_2 0x638 | |
66 | #define GENERAL_PWRMGT 0x63c | |
67 | # define GLOBAL_PWRMGT_EN (1 << 0) | |
68 | # define STATIC_PM_EN (1 << 1) | |
69 | # define THERMAL_PROTECTION_DIS (1 << 2) | |
70 | # define THERMAL_PROTECTION_TYPE (1 << 3) | |
71 | # define ENABLE_GEN2PCIE (1 << 4) | |
72 | # define ENABLE_GEN2XSP (1 << 5) | |
73 | # define SW_SMIO_INDEX(x) ((x) << 6) | |
74 | # define SW_SMIO_INDEX_MASK (3 << 6) | |
75 | # define LOW_VOLT_D2_ACPI (1 << 8) | |
76 | # define LOW_VOLT_D3_ACPI (1 << 9) | |
77 | # define VOLT_PWRMGT_EN (1 << 10) | |
78 | # define BACKBIAS_PAD_EN (1 << 18) | |
79 | # define BACKBIAS_VALUE (1 << 19) | |
80 | # define DYN_SPREAD_SPECTRUM_EN (1 << 23) | |
81 | # define AC_DC_SW (1 << 24) | |
82 | ||
83 | #define SCLK_PWRMGT_CNTL 0x644 | |
84 | # define SCLK_PWRMGT_OFF (1 << 0) | |
85 | # define SCLK_LOW_D1 (1 << 1) | |
86 | # define FIR_RESET (1 << 4) | |
87 | # define FIR_FORCE_TREND_SEL (1 << 5) | |
88 | # define FIR_TREND_MODE (1 << 6) | |
89 | # define DYN_GFX_CLK_OFF_EN (1 << 7) | |
90 | # define GFX_CLK_FORCE_ON (1 << 8) | |
91 | # define GFX_CLK_REQUEST_OFF (1 << 9) | |
92 | # define GFX_CLK_FORCE_OFF (1 << 10) | |
93 | # define GFX_CLK_OFF_ACPI_D1 (1 << 11) | |
94 | # define GFX_CLK_OFF_ACPI_D2 (1 << 12) | |
95 | # define GFX_CLK_OFF_ACPI_D3 (1 << 13) | |
96 | ||
97 | #define TCI_MCLK_PWRMGT_CNTL 0x648 | |
98 | # define MPLL_PWRMGT_OFF (1 << 5) | |
99 | # define DLL_READY (1 << 6) | |
100 | # define MC_INT_CNTL (1 << 7) | |
101 | # define MRDCKA_SLEEP (1 << 8) | |
102 | # define MRDCKB_SLEEP (1 << 9) | |
103 | # define MRDCKC_SLEEP (1 << 10) | |
104 | # define MRDCKD_SLEEP (1 << 11) | |
105 | # define MRDCKE_SLEEP (1 << 12) | |
106 | # define MRDCKF_SLEEP (1 << 13) | |
107 | # define MRDCKG_SLEEP (1 << 14) | |
108 | # define MRDCKH_SLEEP (1 << 15) | |
109 | # define MRDCKA_RESET (1 << 16) | |
110 | # define MRDCKB_RESET (1 << 17) | |
111 | # define MRDCKC_RESET (1 << 18) | |
112 | # define MRDCKD_RESET (1 << 19) | |
113 | # define MRDCKE_RESET (1 << 20) | |
114 | # define MRDCKF_RESET (1 << 21) | |
115 | # define MRDCKG_RESET (1 << 22) | |
116 | # define MRDCKH_RESET (1 << 23) | |
117 | # define DLL_READY_READ (1 << 24) | |
118 | # define USE_DISPLAY_GAP (1 << 25) | |
119 | # define USE_DISPLAY_URGENT_NORMAL (1 << 26) | |
120 | # define MPLL_TURNOFF_D2 (1 << 28) | |
121 | #define TCI_DLL_CNTL 0x64c | |
122 | ||
123 | #define CG_PG_CNTL 0x858 | |
124 | # define PWRGATE_ENABLE (1 << 0) | |
125 | ||
126 | #define CG_AT 0x6d4 | |
127 | #define CG_R(x) ((x) << 0) | |
128 | #define CG_R_MASK (0xffff << 0) | |
129 | #define CG_L(x) ((x) << 16) | |
130 | #define CG_L_MASK (0xffff << 16) | |
131 | ||
132 | #define CG_SPLL_SPREAD_SPECTRUM 0x790 | |
133 | #define SSEN (1 << 0) | |
134 | #define CLK_S(x) ((x) << 4) | |
135 | #define CLK_S_MASK (0xfff << 4) | |
136 | #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 | |
137 | #define CLK_V(x) ((x) << 0) | |
138 | #define CLK_V_MASK (0x3ffffff << 0) | |
139 | ||
140 | #define MC_ARB_DRAM_TIMING 0x2774 | |
141 | #define MC_ARB_DRAM_TIMING2 0x2778 | |
142 | ||
143 | #define MC_ARB_RFSH_RATE 0x27b0 | |
144 | #define POWERMODE0(x) ((x) << 0) | |
145 | #define POWERMODE0_MASK (0xff << 0) | |
146 | #define POWERMODE1(x) ((x) << 8) | |
147 | #define POWERMODE1_MASK (0xff << 8) | |
148 | #define POWERMODE2(x) ((x) << 16) | |
149 | #define POWERMODE2_MASK (0xff << 16) | |
150 | #define POWERMODE3(x) ((x) << 24) | |
151 | #define POWERMODE3_MASK (0xff << 24) | |
152 | ||
153 | #define MC_ARB_DRAM_TIMING_1 0x27f0 | |
154 | #define MC_ARB_DRAM_TIMING_2 0x27f4 | |
155 | #define MC_ARB_DRAM_TIMING_3 0x27f8 | |
156 | #define MC_ARB_DRAM_TIMING2_1 0x27fc | |
157 | #define MC_ARB_DRAM_TIMING2_2 0x2800 | |
158 | #define MC_ARB_DRAM_TIMING2_3 0x2804 | |
159 | ||
160 | #define MC4_IO_DQ_PAD_CNTL_D0_I0 0x2978 | |
161 | #define MC4_IO_DQ_PAD_CNTL_D0_I1 0x297c | |
162 | #define MC4_IO_QS_PAD_CNTL_D0_I0 0x2980 | |
163 | #define MC4_IO_QS_PAD_CNTL_D0_I1 0x2984 | |
164 | ||
165 | #endif |