Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
3ce0a23d JG |
28 | #include <linux/firmware.h> |
29 | #include <linux/platform_device.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
760285e7 | 31 | #include <drm/drmP.h> |
771fe6b9 | 32 | #include "radeon.h" |
e6990375 | 33 | #include "radeon_asic.h" |
760285e7 | 34 | #include <drm/radeon_drm.h> |
3ce0a23d | 35 | #include "rv770d.h" |
3ce0a23d | 36 | #include "atom.h" |
d39c3b89 | 37 | #include "avivod.h" |
771fe6b9 | 38 | |
3ce0a23d JG |
39 | #define R700_PFP_UCODE_SIZE 848 |
40 | #define R700_PM4_UCODE_SIZE 1360 | |
771fe6b9 | 41 | |
3ce0a23d JG |
42 | static void rv770_gpu_init(struct radeon_device *rdev); |
43 | void rv770_fini(struct radeon_device *rdev); | |
9e46a48d | 44 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev); |
771fe6b9 | 45 | |
6f34be50 AD |
46 | u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
47 | { | |
48 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; | |
49 | u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); | |
f6496479 | 50 | int i; |
6f34be50 AD |
51 | |
52 | /* Lock the graphics update lock */ | |
53 | tmp |= AVIVO_D1GRPH_UPDATE_LOCK; | |
54 | WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); | |
55 | ||
56 | /* update the scanout addresses */ | |
57 | if (radeon_crtc->crtc_id) { | |
58 | WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); | |
59 | WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); | |
60 | } else { | |
61 | WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); | |
62 | WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); | |
63 | } | |
64 | WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | |
65 | (u32)crtc_base); | |
66 | WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | |
67 | (u32)crtc_base); | |
68 | ||
69 | /* Wait for update_pending to go high. */ | |
f6496479 AD |
70 | for (i = 0; i < rdev->usec_timeout; i++) { |
71 | if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) | |
72 | break; | |
73 | udelay(1); | |
74 | } | |
6f34be50 AD |
75 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
76 | ||
77 | /* Unlock the lock, so double-buffering can take place inside vblank */ | |
78 | tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; | |
79 | WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); | |
80 | ||
81 | /* Return current update_pending status: */ | |
82 | return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING; | |
83 | } | |
84 | ||
21a8122a | 85 | /* get temperature in millidegrees */ |
20d391d7 | 86 | int rv770_get_temp(struct radeon_device *rdev) |
21a8122a AD |
87 | { |
88 | u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> | |
89 | ASIC_T_SHIFT; | |
20d391d7 | 90 | int actual_temp; |
21a8122a | 91 | |
20d391d7 AD |
92 | if (temp & 0x400) |
93 | actual_temp = -256; | |
94 | else if (temp & 0x200) | |
95 | actual_temp = 255; | |
96 | else if (temp & 0x100) { | |
97 | actual_temp = temp & 0x1ff; | |
98 | actual_temp |= ~0x1ff; | |
99 | } else | |
100 | actual_temp = temp & 0xff; | |
21a8122a | 101 | |
20d391d7 | 102 | return (actual_temp * 1000) / 2; |
21a8122a AD |
103 | } |
104 | ||
49e02b73 AD |
105 | void rv770_pm_misc(struct radeon_device *rdev) |
106 | { | |
a081a9d6 RM |
107 | int req_ps_idx = rdev->pm.requested_power_state_index; |
108 | int req_cm_idx = rdev->pm.requested_clock_mode_index; | |
109 | struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; | |
110 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; | |
4d60173f AD |
111 | |
112 | if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { | |
a377e187 AD |
113 | /* 0xff01 is a flag rather then an actual voltage */ |
114 | if (voltage->voltage == 0xff01) | |
115 | return; | |
4d60173f | 116 | if (voltage->voltage != rdev->pm.current_vddc) { |
8a83ec5e | 117 | radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); |
4d60173f | 118 | rdev->pm.current_vddc = voltage->voltage; |
0fcbe947 | 119 | DRM_DEBUG("Setting: v: %d\n", voltage->voltage); |
4d60173f AD |
120 | } |
121 | } | |
49e02b73 | 122 | } |
771fe6b9 JG |
123 | |
124 | /* | |
3ce0a23d | 125 | * GART |
771fe6b9 | 126 | */ |
1109ca09 | 127 | static int rv770_pcie_gart_enable(struct radeon_device *rdev) |
771fe6b9 | 128 | { |
3ce0a23d JG |
129 | u32 tmp; |
130 | int r, i; | |
771fe6b9 | 131 | |
c9a1be96 | 132 | if (rdev->gart.robj == NULL) { |
4aac0473 JG |
133 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
134 | return -EINVAL; | |
3ce0a23d | 135 | } |
4aac0473 JG |
136 | r = radeon_gart_table_vram_pin(rdev); |
137 | if (r) | |
3ce0a23d | 138 | return r; |
82568565 | 139 | radeon_gart_restore(rdev); |
3ce0a23d JG |
140 | /* Setup L2 cache */ |
141 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
142 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
143 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
144 | WREG32(VM_L2_CNTL2, 0); | |
145 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); | |
146 | /* Setup TLB control */ | |
147 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
148 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
149 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | | |
150 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); | |
151 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); | |
152 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); | |
153 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); | |
0b8c30bc AD |
154 | if (rdev->family == CHIP_RV740) |
155 | WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); | |
3ce0a23d JG |
156 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
157 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); | |
158 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); | |
159 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); | |
160 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); | |
1a029b76 | 161 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
3ce0a23d JG |
162 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
163 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | | |
164 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); | |
165 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, | |
166 | (u32)(rdev->dummy_page.addr >> 12)); | |
167 | for (i = 1; i < 7; i++) | |
168 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
771fe6b9 | 169 | |
3ce0a23d | 170 | r600_pcie_gart_tlb_flush(rdev); |
fcf4de5a TV |
171 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
172 | (unsigned)(rdev->mc.gtt_size >> 20), | |
173 | (unsigned long long)rdev->gart.table_addr); | |
3ce0a23d | 174 | rdev->gart.ready = true; |
771fe6b9 JG |
175 | return 0; |
176 | } | |
177 | ||
1109ca09 | 178 | static void rv770_pcie_gart_disable(struct radeon_device *rdev) |
771fe6b9 | 179 | { |
3ce0a23d | 180 | u32 tmp; |
c9a1be96 | 181 | int i; |
3ce0a23d | 182 | |
3ce0a23d JG |
183 | /* Disable all tables */ |
184 | for (i = 0; i < 7; i++) | |
185 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
186 | ||
187 | /* Setup L2 cache */ | |
188 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | | |
189 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
190 | WREG32(VM_L2_CNTL2, 0); | |
191 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); | |
192 | /* Setup TLB control */ | |
193 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); | |
194 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); | |
195 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); | |
196 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); | |
197 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); | |
198 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); | |
199 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); | |
200 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); | |
c9a1be96 | 201 | radeon_gart_table_vram_unpin(rdev); |
4aac0473 JG |
202 | } |
203 | ||
1109ca09 | 204 | static void rv770_pcie_gart_fini(struct radeon_device *rdev) |
4aac0473 | 205 | { |
f9274562 | 206 | radeon_gart_fini(rdev); |
4aac0473 JG |
207 | rv770_pcie_gart_disable(rdev); |
208 | radeon_gart_table_vram_free(rdev); | |
771fe6b9 JG |
209 | } |
210 | ||
211 | ||
1109ca09 | 212 | static void rv770_agp_enable(struct radeon_device *rdev) |
1a029b76 JG |
213 | { |
214 | u32 tmp; | |
215 | int i; | |
216 | ||
217 | /* Setup L2 cache */ | |
218 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
219 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
220 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
221 | WREG32(VM_L2_CNTL2, 0); | |
222 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); | |
223 | /* Setup TLB control */ | |
224 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
225 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
226 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | | |
227 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); | |
228 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); | |
229 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); | |
230 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); | |
231 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); | |
232 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); | |
233 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); | |
234 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); | |
235 | for (i = 0; i < 7; i++) | |
236 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
237 | } | |
238 | ||
a3c1945a | 239 | static void rv770_mc_program(struct radeon_device *rdev) |
771fe6b9 | 240 | { |
a3c1945a | 241 | struct rv515_mc_save save; |
3ce0a23d JG |
242 | u32 tmp; |
243 | int i, j; | |
244 | ||
245 | /* Initialize HDP */ | |
246 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
247 | WREG32((0x2c14 + j), 0x00000000); | |
248 | WREG32((0x2c18 + j), 0x00000000); | |
249 | WREG32((0x2c1c + j), 0x00000000); | |
250 | WREG32((0x2c20 + j), 0x00000000); | |
251 | WREG32((0x2c24 + j), 0x00000000); | |
252 | } | |
812d0469 AD |
253 | /* r7xx hw bug. Read from HDP_DEBUG1 rather |
254 | * than writing to HDP_REG_COHERENCY_FLUSH_CNTL | |
255 | */ | |
256 | tmp = RREG32(HDP_DEBUG1); | |
3ce0a23d | 257 | |
a3c1945a | 258 | rv515_mc_stop(rdev, &save); |
3ce0a23d | 259 | if (r600_mc_wait_for_idle(rdev)) { |
a3c1945a | 260 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3ce0a23d | 261 | } |
3ce0a23d JG |
262 | /* Lockout access through VGA aperture*/ |
263 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); | |
3ce0a23d | 264 | /* Update configuration */ |
1a029b76 JG |
265 | if (rdev->flags & RADEON_IS_AGP) { |
266 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { | |
267 | /* VRAM before AGP */ | |
268 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
269 | rdev->mc.vram_start >> 12); | |
270 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
271 | rdev->mc.gtt_end >> 12); | |
272 | } else { | |
273 | /* VRAM after AGP */ | |
274 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
275 | rdev->mc.gtt_start >> 12); | |
276 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
277 | rdev->mc.vram_end >> 12); | |
278 | } | |
279 | } else { | |
280 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
281 | rdev->mc.vram_start >> 12); | |
282 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
283 | rdev->mc.vram_end >> 12); | |
284 | } | |
16cdf04d | 285 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); |
1a029b76 | 286 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
3ce0a23d JG |
287 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
288 | WREG32(MC_VM_FB_LOCATION, tmp); | |
289 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); | |
290 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); | |
46fcd2b3 | 291 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
3ce0a23d | 292 | if (rdev->flags & RADEON_IS_AGP) { |
1a029b76 | 293 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); |
3ce0a23d JG |
294 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); |
295 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); | |
296 | } else { | |
297 | WREG32(MC_VM_AGP_BASE, 0); | |
298 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); | |
299 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); | |
300 | } | |
3ce0a23d | 301 | if (r600_mc_wait_for_idle(rdev)) { |
a3c1945a | 302 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3ce0a23d | 303 | } |
a3c1945a | 304 | rv515_mc_resume(rdev, &save); |
698443d9 DA |
305 | /* we need to own VRAM, so turn off the VGA renderer here |
306 | * to stop it overwriting our objects */ | |
d39c3b89 | 307 | rv515_vga_render_disable(rdev); |
771fe6b9 JG |
308 | } |
309 | ||
3ce0a23d JG |
310 | |
311 | /* | |
312 | * CP. | |
313 | */ | |
314 | void r700_cp_stop(struct radeon_device *rdev) | |
771fe6b9 | 315 | { |
53595338 | 316 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
3ce0a23d | 317 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
724c80e1 | 318 | WREG32(SCRATCH_UMSK, 0); |
4d75658b | 319 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
771fe6b9 JG |
320 | } |
321 | ||
3ce0a23d | 322 | static int rv770_cp_load_microcode(struct radeon_device *rdev) |
771fe6b9 | 323 | { |
3ce0a23d JG |
324 | const __be32 *fw_data; |
325 | int i; | |
326 | ||
327 | if (!rdev->me_fw || !rdev->pfp_fw) | |
328 | return -EINVAL; | |
329 | ||
330 | r700_cp_stop(rdev); | |
4eace7fd CC |
331 | WREG32(CP_RB_CNTL, |
332 | #ifdef __BIG_ENDIAN | |
333 | BUF_SWAP_32BIT | | |
334 | #endif | |
335 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); | |
3ce0a23d JG |
336 | |
337 | /* Reset cp */ | |
338 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | |
339 | RREG32(GRBM_SOFT_RESET); | |
340 | mdelay(15); | |
341 | WREG32(GRBM_SOFT_RESET, 0); | |
342 | ||
343 | fw_data = (const __be32 *)rdev->pfp_fw->data; | |
344 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
345 | for (i = 0; i < R700_PFP_UCODE_SIZE; i++) | |
346 | WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); | |
347 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
348 | ||
349 | fw_data = (const __be32 *)rdev->me_fw->data; | |
350 | WREG32(CP_ME_RAM_WADDR, 0); | |
351 | for (i = 0; i < R700_PM4_UCODE_SIZE; i++) | |
352 | WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); | |
353 | ||
354 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
355 | WREG32(CP_ME_RAM_WADDR, 0); | |
356 | WREG32(CP_ME_RAM_RADDR, 0); | |
357 | return 0; | |
771fe6b9 JG |
358 | } |
359 | ||
fe251e2f AD |
360 | void r700_cp_fini(struct radeon_device *rdev) |
361 | { | |
45df6803 | 362 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
fe251e2f | 363 | r700_cp_stop(rdev); |
45df6803 CK |
364 | radeon_ring_fini(rdev, ring); |
365 | radeon_scratch_free(rdev, ring->rptr_save_reg); | |
fe251e2f | 366 | } |
771fe6b9 JG |
367 | |
368 | /* | |
3ce0a23d | 369 | * Core functions |
771fe6b9 | 370 | */ |
3ce0a23d | 371 | static void rv770_gpu_init(struct radeon_device *rdev) |
771fe6b9 | 372 | { |
3ce0a23d | 373 | int i, j, num_qd_pipes; |
d03f5d59 | 374 | u32 ta_aux_cntl; |
3ce0a23d JG |
375 | u32 sx_debug_1; |
376 | u32 smx_dc_ctl0; | |
d03f5d59 | 377 | u32 db_debug3; |
3ce0a23d JG |
378 | u32 num_gs_verts_per_thread; |
379 | u32 vgt_gs_per_es; | |
380 | u32 gs_prim_buffer_depth = 0; | |
381 | u32 sq_ms_fifo_sizes; | |
382 | u32 sq_config; | |
383 | u32 sq_thread_resource_mgmt; | |
384 | u32 hdp_host_path_cntl; | |
385 | u32 sq_dyn_gpr_size_simd_ab_0; | |
3ce0a23d JG |
386 | u32 gb_tiling_config = 0; |
387 | u32 cc_rb_backend_disable = 0; | |
388 | u32 cc_gc_shader_pipe_config = 0; | |
389 | u32 mc_arb_ramcfg; | |
416a2bd2 AD |
390 | u32 db_debug4, tmp; |
391 | u32 inactive_pipes, shader_pipe_config; | |
392 | u32 disabled_rb_mask; | |
393 | unsigned active_number; | |
771fe6b9 | 394 | |
3ce0a23d | 395 | /* setup chip specs */ |
416a2bd2 | 396 | rdev->config.rv770.tiling_group_size = 256; |
3ce0a23d JG |
397 | switch (rdev->family) { |
398 | case CHIP_RV770: | |
399 | rdev->config.rv770.max_pipes = 4; | |
400 | rdev->config.rv770.max_tile_pipes = 8; | |
401 | rdev->config.rv770.max_simds = 10; | |
402 | rdev->config.rv770.max_backends = 4; | |
403 | rdev->config.rv770.max_gprs = 256; | |
404 | rdev->config.rv770.max_threads = 248; | |
405 | rdev->config.rv770.max_stack_entries = 512; | |
406 | rdev->config.rv770.max_hw_contexts = 8; | |
407 | rdev->config.rv770.max_gs_threads = 16 * 2; | |
408 | rdev->config.rv770.sx_max_export_size = 128; | |
409 | rdev->config.rv770.sx_max_export_pos_size = 16; | |
410 | rdev->config.rv770.sx_max_export_smx_size = 112; | |
411 | rdev->config.rv770.sq_num_cf_insts = 2; | |
412 | ||
413 | rdev->config.rv770.sx_num_of_sets = 7; | |
414 | rdev->config.rv770.sc_prim_fifo_size = 0xF9; | |
415 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; | |
416 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; | |
417 | break; | |
418 | case CHIP_RV730: | |
419 | rdev->config.rv770.max_pipes = 2; | |
420 | rdev->config.rv770.max_tile_pipes = 4; | |
421 | rdev->config.rv770.max_simds = 8; | |
422 | rdev->config.rv770.max_backends = 2; | |
423 | rdev->config.rv770.max_gprs = 128; | |
424 | rdev->config.rv770.max_threads = 248; | |
425 | rdev->config.rv770.max_stack_entries = 256; | |
426 | rdev->config.rv770.max_hw_contexts = 8; | |
427 | rdev->config.rv770.max_gs_threads = 16 * 2; | |
428 | rdev->config.rv770.sx_max_export_size = 256; | |
429 | rdev->config.rv770.sx_max_export_pos_size = 32; | |
430 | rdev->config.rv770.sx_max_export_smx_size = 224; | |
431 | rdev->config.rv770.sq_num_cf_insts = 2; | |
432 | ||
433 | rdev->config.rv770.sx_num_of_sets = 7; | |
434 | rdev->config.rv770.sc_prim_fifo_size = 0xf9; | |
435 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; | |
436 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; | |
437 | if (rdev->config.rv770.sx_max_export_pos_size > 16) { | |
438 | rdev->config.rv770.sx_max_export_pos_size -= 16; | |
439 | rdev->config.rv770.sx_max_export_smx_size += 16; | |
440 | } | |
441 | break; | |
442 | case CHIP_RV710: | |
443 | rdev->config.rv770.max_pipes = 2; | |
444 | rdev->config.rv770.max_tile_pipes = 2; | |
445 | rdev->config.rv770.max_simds = 2; | |
446 | rdev->config.rv770.max_backends = 1; | |
447 | rdev->config.rv770.max_gprs = 256; | |
448 | rdev->config.rv770.max_threads = 192; | |
449 | rdev->config.rv770.max_stack_entries = 256; | |
450 | rdev->config.rv770.max_hw_contexts = 4; | |
451 | rdev->config.rv770.max_gs_threads = 8 * 2; | |
452 | rdev->config.rv770.sx_max_export_size = 128; | |
453 | rdev->config.rv770.sx_max_export_pos_size = 16; | |
454 | rdev->config.rv770.sx_max_export_smx_size = 112; | |
455 | rdev->config.rv770.sq_num_cf_insts = 1; | |
456 | ||
457 | rdev->config.rv770.sx_num_of_sets = 7; | |
458 | rdev->config.rv770.sc_prim_fifo_size = 0x40; | |
459 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; | |
460 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; | |
461 | break; | |
462 | case CHIP_RV740: | |
463 | rdev->config.rv770.max_pipes = 4; | |
464 | rdev->config.rv770.max_tile_pipes = 4; | |
465 | rdev->config.rv770.max_simds = 8; | |
466 | rdev->config.rv770.max_backends = 4; | |
467 | rdev->config.rv770.max_gprs = 256; | |
468 | rdev->config.rv770.max_threads = 248; | |
469 | rdev->config.rv770.max_stack_entries = 512; | |
470 | rdev->config.rv770.max_hw_contexts = 8; | |
471 | rdev->config.rv770.max_gs_threads = 16 * 2; | |
472 | rdev->config.rv770.sx_max_export_size = 256; | |
473 | rdev->config.rv770.sx_max_export_pos_size = 32; | |
474 | rdev->config.rv770.sx_max_export_smx_size = 224; | |
475 | rdev->config.rv770.sq_num_cf_insts = 2; | |
476 | ||
477 | rdev->config.rv770.sx_num_of_sets = 7; | |
478 | rdev->config.rv770.sc_prim_fifo_size = 0x100; | |
479 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; | |
480 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; | |
481 | ||
482 | if (rdev->config.rv770.sx_max_export_pos_size > 16) { | |
483 | rdev->config.rv770.sx_max_export_pos_size -= 16; | |
484 | rdev->config.rv770.sx_max_export_smx_size += 16; | |
485 | } | |
486 | break; | |
487 | default: | |
488 | break; | |
489 | } | |
490 | ||
491 | /* Initialize HDP */ | |
492 | j = 0; | |
493 | for (i = 0; i < 32; i++) { | |
494 | WREG32((0x2c14 + j), 0x00000000); | |
495 | WREG32((0x2c18 + j), 0x00000000); | |
496 | WREG32((0x2c1c + j), 0x00000000); | |
497 | WREG32((0x2c20 + j), 0x00000000); | |
498 | WREG32((0x2c24 + j), 0x00000000); | |
499 | j += 0x18; | |
500 | } | |
501 | ||
502 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); | |
503 | ||
504 | /* setup tiling, simd, pipe config */ | |
505 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); | |
506 | ||
416a2bd2 AD |
507 | shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); |
508 | inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT; | |
509 | for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) { | |
510 | if (!(inactive_pipes & tmp)) { | |
511 | active_number++; | |
512 | } | |
513 | tmp <<= 1; | |
514 | } | |
515 | if (active_number == 1) { | |
516 | WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1); | |
517 | } else { | |
518 | WREG32(SPI_CONFIG_CNTL, 0); | |
519 | } | |
520 | ||
521 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; | |
522 | tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16); | |
523 | if (tmp < rdev->config.rv770.max_backends) { | |
524 | rdev->config.rv770.max_backends = tmp; | |
525 | } | |
526 | ||
527 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; | |
528 | tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK); | |
529 | if (tmp < rdev->config.rv770.max_pipes) { | |
530 | rdev->config.rv770.max_pipes = tmp; | |
531 | } | |
532 | tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK); | |
533 | if (tmp < rdev->config.rv770.max_simds) { | |
534 | rdev->config.rv770.max_simds = tmp; | |
535 | } | |
536 | ||
3ce0a23d JG |
537 | switch (rdev->config.rv770.max_tile_pipes) { |
538 | case 1: | |
d03f5d59 | 539 | default: |
416a2bd2 | 540 | gb_tiling_config = PIPE_TILING(0); |
3ce0a23d JG |
541 | break; |
542 | case 2: | |
416a2bd2 | 543 | gb_tiling_config = PIPE_TILING(1); |
3ce0a23d JG |
544 | break; |
545 | case 4: | |
416a2bd2 | 546 | gb_tiling_config = PIPE_TILING(2); |
3ce0a23d JG |
547 | break; |
548 | case 8: | |
416a2bd2 | 549 | gb_tiling_config = PIPE_TILING(3); |
3ce0a23d JG |
550 | break; |
551 | } | |
d03f5d59 | 552 | rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; |
3ce0a23d | 553 | |
416a2bd2 AD |
554 | disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK; |
555 | tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; | |
556 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends, | |
557 | R7XX_MAX_BACKENDS, disabled_rb_mask); | |
558 | gb_tiling_config |= tmp << 16; | |
559 | rdev->config.rv770.backend_map = tmp; | |
560 | ||
3ce0a23d JG |
561 | if (rdev->family == CHIP_RV770) |
562 | gb_tiling_config |= BANK_TILING(1); | |
29d65406 AD |
563 | else { |
564 | if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) | |
565 | gb_tiling_config |= BANK_TILING(1); | |
566 | else | |
567 | gb_tiling_config |= BANK_TILING(0); | |
568 | } | |
961fb597 | 569 | rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); |
881fe6c1 | 570 | gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); |
e29649db | 571 | if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { |
3ce0a23d JG |
572 | gb_tiling_config |= ROW_TILING(3); |
573 | gb_tiling_config |= SAMPLE_SPLIT(3); | |
574 | } else { | |
575 | gb_tiling_config |= | |
576 | ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); | |
577 | gb_tiling_config |= | |
578 | SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); | |
579 | } | |
580 | ||
581 | gb_tiling_config |= BANK_SWAPS(1); | |
e7aeeba6 | 582 | rdev->config.rv770.tile_config = gb_tiling_config; |
3ce0a23d JG |
583 | |
584 | WREG32(GB_TILING_CONFIG, gb_tiling_config); | |
585 | WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); | |
586 | WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); | |
4d75658b AD |
587 | WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
588 | WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff)); | |
3ce0a23d | 589 | |
3ce0a23d JG |
590 | WREG32(CGTS_SYS_TCC_DISABLE, 0); |
591 | WREG32(CGTS_TCC_DISABLE, 0); | |
f867c60d AD |
592 | WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); |
593 | WREG32(CGTS_USER_TCC_DISABLE, 0); | |
3ce0a23d | 594 | |
416a2bd2 AD |
595 | |
596 | num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); | |
3ce0a23d JG |
597 | WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); |
598 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); | |
599 | ||
600 | /* set HW defaults for 3D engine */ | |
601 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | | |
e29649db | 602 | ROQ_IB2_START(0x2b))); |
3ce0a23d JG |
603 | |
604 | WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); | |
605 | ||
d03f5d59 AD |
606 | ta_aux_cntl = RREG32(TA_CNTL_AUX); |
607 | WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); | |
3ce0a23d JG |
608 | |
609 | sx_debug_1 = RREG32(SX_DEBUG_1); | |
610 | sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; | |
611 | WREG32(SX_DEBUG_1, sx_debug_1); | |
612 | ||
613 | smx_dc_ctl0 = RREG32(SMX_DC_CTL0); | |
614 | smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); | |
615 | smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); | |
616 | WREG32(SMX_DC_CTL0, smx_dc_ctl0); | |
617 | ||
d03f5d59 AD |
618 | if (rdev->family != CHIP_RV740) |
619 | WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | | |
620 | GS_FLUSH_CTL(4) | | |
621 | ACK_FLUSH_CTL(3) | | |
622 | SYNC_FLUSH_CTL)); | |
3ce0a23d | 623 | |
b866d133 AD |
624 | if (rdev->family != CHIP_RV770) |
625 | WREG32(SMX_SAR_CTL0, 0x00003f3f); | |
626 | ||
d03f5d59 AD |
627 | db_debug3 = RREG32(DB_DEBUG3); |
628 | db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); | |
629 | switch (rdev->family) { | |
630 | case CHIP_RV770: | |
631 | case CHIP_RV740: | |
632 | db_debug3 |= DB_CLK_OFF_DELAY(0x1f); | |
633 | break; | |
634 | case CHIP_RV710: | |
635 | case CHIP_RV730: | |
636 | default: | |
637 | db_debug3 |= DB_CLK_OFF_DELAY(2); | |
638 | break; | |
639 | } | |
640 | WREG32(DB_DEBUG3, db_debug3); | |
641 | ||
642 | if (rdev->family != CHIP_RV770) { | |
3ce0a23d JG |
643 | db_debug4 = RREG32(DB_DEBUG4); |
644 | db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; | |
645 | WREG32(DB_DEBUG4, db_debug4); | |
646 | } | |
647 | ||
648 | WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | | |
e29649db AD |
649 | POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | |
650 | SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); | |
3ce0a23d JG |
651 | |
652 | WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | | |
e29649db AD |
653 | SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | |
654 | SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); | |
3ce0a23d JG |
655 | |
656 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); | |
657 | ||
658 | WREG32(VGT_NUM_INSTANCES, 1); | |
659 | ||
3ce0a23d JG |
660 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); |
661 | ||
662 | WREG32(CP_PERFMON_CNTL, 0); | |
663 | ||
664 | sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | | |
665 | DONE_FIFO_HIWATER(0xe0) | | |
666 | ALU_UPDATE_FIFO_HIWATER(0x8)); | |
667 | switch (rdev->family) { | |
668 | case CHIP_RV770: | |
3ce0a23d JG |
669 | case CHIP_RV730: |
670 | case CHIP_RV710: | |
d03f5d59 AD |
671 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); |
672 | break; | |
3ce0a23d JG |
673 | case CHIP_RV740: |
674 | default: | |
675 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); | |
676 | break; | |
677 | } | |
678 | WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); | |
679 | ||
680 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT | |
681 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values | |
682 | */ | |
683 | sq_config = RREG32(SQ_CONFIG); | |
684 | sq_config &= ~(PS_PRIO(3) | | |
685 | VS_PRIO(3) | | |
686 | GS_PRIO(3) | | |
687 | ES_PRIO(3)); | |
688 | sq_config |= (DX9_CONSTS | | |
689 | VC_ENABLE | | |
690 | EXPORT_SRC_C | | |
691 | PS_PRIO(0) | | |
692 | VS_PRIO(1) | | |
693 | GS_PRIO(2) | | |
694 | ES_PRIO(3)); | |
695 | if (rdev->family == CHIP_RV710) | |
696 | /* no vertex cache */ | |
697 | sq_config &= ~VC_ENABLE; | |
698 | ||
699 | WREG32(SQ_CONFIG, sq_config); | |
700 | ||
701 | WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | | |
fe62e1a4 DA |
702 | NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | |
703 | NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); | |
3ce0a23d JG |
704 | |
705 | WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | | |
fe62e1a4 | 706 | NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); |
3ce0a23d JG |
707 | |
708 | sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | | |
709 | NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | | |
710 | NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); | |
711 | if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) | |
712 | sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); | |
713 | else | |
714 | sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); | |
715 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); | |
716 | ||
717 | WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | | |
718 | NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); | |
719 | ||
720 | WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | | |
721 | NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); | |
722 | ||
723 | sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | | |
724 | SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | | |
725 | SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | | |
726 | SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); | |
727 | ||
728 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); | |
729 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); | |
730 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); | |
731 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); | |
732 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); | |
733 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); | |
734 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); | |
735 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); | |
736 | ||
737 | WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | | |
fe62e1a4 | 738 | FORCE_EOV_MAX_REZ_CNT(255))); |
3ce0a23d JG |
739 | |
740 | if (rdev->family == CHIP_RV710) | |
741 | WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | | |
fe62e1a4 | 742 | AUTO_INVLD_EN(ES_AND_GS_AUTO))); |
3ce0a23d JG |
743 | else |
744 | WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | | |
fe62e1a4 | 745 | AUTO_INVLD_EN(ES_AND_GS_AUTO))); |
3ce0a23d JG |
746 | |
747 | switch (rdev->family) { | |
748 | case CHIP_RV770: | |
749 | case CHIP_RV730: | |
750 | case CHIP_RV740: | |
751 | gs_prim_buffer_depth = 384; | |
752 | break; | |
753 | case CHIP_RV710: | |
754 | gs_prim_buffer_depth = 128; | |
755 | break; | |
756 | default: | |
757 | break; | |
758 | } | |
759 | ||
760 | num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; | |
761 | vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; | |
762 | /* Max value for this is 256 */ | |
763 | if (vgt_gs_per_es > 256) | |
764 | vgt_gs_per_es = 256; | |
765 | ||
766 | WREG32(VGT_ES_PER_GS, 128); | |
767 | WREG32(VGT_GS_PER_ES, vgt_gs_per_es); | |
768 | WREG32(VGT_GS_PER_VS, 2); | |
769 | ||
770 | /* more default values. 2D/3D driver should adjust as needed */ | |
771 | WREG32(VGT_GS_VERTEX_REUSE, 16); | |
772 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); | |
773 | WREG32(VGT_STRMOUT_EN, 0); | |
774 | WREG32(SX_MISC, 0); | |
775 | WREG32(PA_SC_MODE_CNTL, 0); | |
776 | WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); | |
777 | WREG32(PA_SC_AA_CONFIG, 0); | |
778 | WREG32(PA_SC_CLIPRECT_RULE, 0xffff); | |
779 | WREG32(PA_SC_LINE_STIPPLE, 0); | |
780 | WREG32(SPI_INPUT_Z, 0); | |
781 | WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); | |
782 | WREG32(CB_COLOR7_FRAG, 0); | |
783 | ||
784 | /* clear render buffer base addresses */ | |
785 | WREG32(CB_COLOR0_BASE, 0); | |
786 | WREG32(CB_COLOR1_BASE, 0); | |
787 | WREG32(CB_COLOR2_BASE, 0); | |
788 | WREG32(CB_COLOR3_BASE, 0); | |
789 | WREG32(CB_COLOR4_BASE, 0); | |
790 | WREG32(CB_COLOR5_BASE, 0); | |
791 | WREG32(CB_COLOR6_BASE, 0); | |
792 | WREG32(CB_COLOR7_BASE, 0); | |
793 | ||
794 | WREG32(TCP_CNTL, 0); | |
795 | ||
796 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); | |
797 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); | |
798 | ||
799 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); | |
800 | ||
801 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | | |
802 | NUM_CLIP_SEQ(3))); | |
b866d133 | 803 | WREG32(VC_ENHANCE, 0); |
3ce0a23d JG |
804 | } |
805 | ||
0ef0c1f7 AD |
806 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
807 | { | |
808 | u64 size_bf, size_af; | |
809 | ||
810 | if (mc->mc_vram_size > 0xE0000000) { | |
811 | /* leave room for at least 512M GTT */ | |
812 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
813 | mc->real_vram_size = 0xE0000000; | |
814 | mc->mc_vram_size = 0xE0000000; | |
815 | } | |
816 | if (rdev->flags & RADEON_IS_AGP) { | |
817 | size_bf = mc->gtt_start; | |
dfc6ae5b | 818 | size_af = 0xFFFFFFFF - mc->gtt_end; |
0ef0c1f7 AD |
819 | if (size_bf > size_af) { |
820 | if (mc->mc_vram_size > size_bf) { | |
821 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
822 | mc->real_vram_size = size_bf; | |
823 | mc->mc_vram_size = size_bf; | |
824 | } | |
825 | mc->vram_start = mc->gtt_start - mc->mc_vram_size; | |
826 | } else { | |
827 | if (mc->mc_vram_size > size_af) { | |
828 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
829 | mc->real_vram_size = size_af; | |
830 | mc->mc_vram_size = size_af; | |
831 | } | |
dfc6ae5b | 832 | mc->vram_start = mc->gtt_end + 1; |
0ef0c1f7 AD |
833 | } |
834 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
835 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", | |
836 | mc->mc_vram_size >> 20, mc->vram_start, | |
837 | mc->vram_end, mc->real_vram_size >> 20); | |
838 | } else { | |
b4183e30 | 839 | radeon_vram_location(rdev, &rdev->mc, 0); |
0ef0c1f7 AD |
840 | rdev->mc.gtt_base_align = 0; |
841 | radeon_gtt_location(rdev, mc); | |
842 | } | |
843 | } | |
844 | ||
1109ca09 | 845 | static int rv770_mc_init(struct radeon_device *rdev) |
3ce0a23d | 846 | { |
3ce0a23d | 847 | u32 tmp; |
5885b7a9 | 848 | int chansize, numchan; |
3ce0a23d JG |
849 | |
850 | /* Get VRAM informations */ | |
3ce0a23d | 851 | rdev->mc.vram_is_ddr = true; |
5885b7a9 AD |
852 | tmp = RREG32(MC_ARB_RAMCFG); |
853 | if (tmp & CHANSIZE_OVERRIDE) { | |
854 | chansize = 16; | |
855 | } else if (tmp & CHANSIZE_MASK) { | |
856 | chansize = 64; | |
857 | } else { | |
858 | chansize = 32; | |
859 | } | |
860 | tmp = RREG32(MC_SHARED_CHMAP); | |
861 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { | |
862 | case 0: | |
863 | default: | |
864 | numchan = 1; | |
865 | break; | |
866 | case 1: | |
867 | numchan = 2; | |
868 | break; | |
869 | case 2: | |
870 | numchan = 4; | |
871 | break; | |
872 | case 3: | |
873 | numchan = 8; | |
874 | break; | |
875 | } | |
876 | rdev->mc.vram_width = numchan * chansize; | |
771fe6b9 | 877 | /* Could aper size report 0 ? */ |
01d73a69 JC |
878 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
879 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); | |
3ce0a23d JG |
880 | /* Setup GPU memory space */ |
881 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); | |
882 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); | |
51e5fcd3 | 883 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
0ef0c1f7 | 884 | r700_vram_gtt_location(rdev, &rdev->mc); |
f47299c5 AD |
885 | radeon_update_bandwidth_info(rdev); |
886 | ||
3ce0a23d JG |
887 | return 0; |
888 | } | |
d594e46a | 889 | |
fc30b8ef | 890 | static int rv770_startup(struct radeon_device *rdev) |
3ce0a23d | 891 | { |
4d75658b | 892 | struct radeon_ring *ring; |
3ce0a23d JG |
893 | int r; |
894 | ||
9e46a48d AD |
895 | /* enable pcie gen2 link */ |
896 | rv770_pcie_gen2_enable(rdev); | |
897 | ||
779720a3 AD |
898 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
899 | r = r600_init_microcode(rdev); | |
900 | if (r) { | |
901 | DRM_ERROR("Failed to load firmware!\n"); | |
902 | return r; | |
903 | } | |
904 | } | |
905 | ||
16cdf04d AD |
906 | r = r600_vram_scratch_init(rdev); |
907 | if (r) | |
908 | return r; | |
909 | ||
a3c1945a | 910 | rv770_mc_program(rdev); |
1a029b76 JG |
911 | if (rdev->flags & RADEON_IS_AGP) { |
912 | rv770_agp_enable(rdev); | |
913 | } else { | |
914 | r = rv770_pcie_gart_enable(rdev); | |
915 | if (r) | |
916 | return r; | |
917 | } | |
16cdf04d | 918 | |
3ce0a23d | 919 | rv770_gpu_init(rdev); |
c38c7b64 JG |
920 | r = r600_blit_init(rdev); |
921 | if (r) { | |
922 | r600_blit_fini(rdev); | |
27cd7769 | 923 | rdev->asic->copy.copy = NULL; |
c38c7b64 JG |
924 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
925 | } | |
b70d6bb3 | 926 | |
724c80e1 AD |
927 | /* allocate wb buffer */ |
928 | r = radeon_wb_init(rdev); | |
929 | if (r) | |
930 | return r; | |
931 | ||
30eb77f4 JG |
932 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
933 | if (r) { | |
934 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); | |
935 | return r; | |
936 | } | |
937 | ||
4d75658b AD |
938 | r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); |
939 | if (r) { | |
940 | dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); | |
941 | return r; | |
942 | } | |
943 | ||
d8f60cfc | 944 | /* Enable IRQ */ |
d8f60cfc AD |
945 | r = r600_irq_init(rdev); |
946 | if (r) { | |
947 | DRM_ERROR("radeon: IH init failed (%d).\n", r); | |
948 | radeon_irq_kms_fini(rdev); | |
949 | return r; | |
950 | } | |
951 | r600_irq_set(rdev); | |
952 | ||
4d75658b | 953 | ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
e32eb50d | 954 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
78c5560a AD |
955 | R600_CP_RB_RPTR, R600_CP_RB_WPTR, |
956 | 0, 0xfffff, RADEON_CP_PACKET2); | |
3ce0a23d JG |
957 | if (r) |
958 | return r; | |
4d75658b AD |
959 | |
960 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; | |
961 | r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, | |
962 | DMA_RB_RPTR, DMA_RB_WPTR, | |
963 | 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); | |
964 | if (r) | |
965 | return r; | |
966 | ||
3ce0a23d JG |
967 | r = rv770_cp_load_microcode(rdev); |
968 | if (r) | |
969 | return r; | |
970 | r = r600_cp_resume(rdev); | |
971 | if (r) | |
972 | return r; | |
724c80e1 | 973 | |
4d75658b AD |
974 | r = r600_dma_resume(rdev); |
975 | if (r) | |
976 | return r; | |
977 | ||
2898c348 CK |
978 | r = radeon_ib_pool_init(rdev); |
979 | if (r) { | |
980 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); | |
b15ba512 | 981 | return r; |
2898c348 | 982 | } |
b15ba512 | 983 | |
d4e30ef0 AD |
984 | r = r600_audio_init(rdev); |
985 | if (r) { | |
986 | DRM_ERROR("radeon: audio init failed\n"); | |
987 | return r; | |
988 | } | |
989 | ||
3ce0a23d JG |
990 | return 0; |
991 | } | |
992 | ||
fc30b8ef DA |
993 | int rv770_resume(struct radeon_device *rdev) |
994 | { | |
995 | int r; | |
996 | ||
1a029b76 JG |
997 | /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, |
998 | * posting will perform necessary task to bring back GPU into good | |
999 | * shape. | |
1000 | */ | |
fc30b8ef | 1001 | /* post card */ |
e7d40b9a | 1002 | atom_asic_init(rdev->mode_info.atom_context); |
fc30b8ef | 1003 | |
b15ba512 | 1004 | rdev->accel_working = true; |
fc30b8ef DA |
1005 | r = rv770_startup(rdev); |
1006 | if (r) { | |
1007 | DRM_ERROR("r600 startup failed on resume\n"); | |
6b7746e8 | 1008 | rdev->accel_working = false; |
fc30b8ef DA |
1009 | return r; |
1010 | } | |
1011 | ||
fc30b8ef DA |
1012 | return r; |
1013 | ||
1014 | } | |
1015 | ||
3ce0a23d JG |
1016 | int rv770_suspend(struct radeon_device *rdev) |
1017 | { | |
8a8c6e7c | 1018 | r600_audio_fini(rdev); |
3ce0a23d | 1019 | r700_cp_stop(rdev); |
4d75658b | 1020 | r600_dma_stop(rdev); |
0c45249f | 1021 | r600_irq_suspend(rdev); |
724c80e1 | 1022 | radeon_wb_disable(rdev); |
4aac0473 | 1023 | rv770_pcie_gart_disable(rdev); |
6ddddfe7 | 1024 | |
3ce0a23d JG |
1025 | return 0; |
1026 | } | |
1027 | ||
1028 | /* Plan is to move initialization in that function and use | |
1029 | * helper function so that radeon_device_init pretty much | |
1030 | * do nothing more than calling asic specific function. This | |
1031 | * should also allow to remove a bunch of callback function | |
1032 | * like vram_info. | |
1033 | */ | |
1034 | int rv770_init(struct radeon_device *rdev) | |
1035 | { | |
1036 | int r; | |
1037 | ||
3ce0a23d JG |
1038 | /* Read BIOS */ |
1039 | if (!radeon_get_bios(rdev)) { | |
1040 | if (ASIC_IS_AVIVO(rdev)) | |
1041 | return -EINVAL; | |
1042 | } | |
1043 | /* Must be an ATOMBIOS */ | |
e7d40b9a JG |
1044 | if (!rdev->is_atom_bios) { |
1045 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); | |
3ce0a23d | 1046 | return -EINVAL; |
e7d40b9a | 1047 | } |
3ce0a23d JG |
1048 | r = radeon_atombios_init(rdev); |
1049 | if (r) | |
1050 | return r; | |
1051 | /* Post card if necessary */ | |
fd909c37 | 1052 | if (!radeon_card_posted(rdev)) { |
72542d77 DA |
1053 | if (!rdev->bios) { |
1054 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); | |
1055 | return -EINVAL; | |
1056 | } | |
3ce0a23d JG |
1057 | DRM_INFO("GPU not posted. posting now...\n"); |
1058 | atom_asic_init(rdev->mode_info.atom_context); | |
1059 | } | |
1060 | /* Initialize scratch registers */ | |
1061 | r600_scratch_init(rdev); | |
1062 | /* Initialize surface registers */ | |
1063 | radeon_surface_init(rdev); | |
7433874e | 1064 | /* Initialize clocks */ |
5e6dde7e | 1065 | radeon_get_clock_info(rdev->ddev); |
3ce0a23d | 1066 | /* Fence driver */ |
30eb77f4 | 1067 | r = radeon_fence_driver_init(rdev); |
3ce0a23d JG |
1068 | if (r) |
1069 | return r; | |
d594e46a | 1070 | /* initialize AGP */ |
700a0cc0 JG |
1071 | if (rdev->flags & RADEON_IS_AGP) { |
1072 | r = radeon_agp_init(rdev); | |
1073 | if (r) | |
1074 | radeon_agp_disable(rdev); | |
1075 | } | |
3ce0a23d | 1076 | r = rv770_mc_init(rdev); |
b574f251 | 1077 | if (r) |
3ce0a23d | 1078 | return r; |
3ce0a23d | 1079 | /* Memory manager */ |
4c788679 | 1080 | r = radeon_bo_init(rdev); |
3ce0a23d JG |
1081 | if (r) |
1082 | return r; | |
d8f60cfc AD |
1083 | |
1084 | r = radeon_irq_kms_init(rdev); | |
1085 | if (r) | |
1086 | return r; | |
1087 | ||
e32eb50d CK |
1088 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
1089 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); | |
3ce0a23d | 1090 | |
4d75658b AD |
1091 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; |
1092 | r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); | |
1093 | ||
d8f60cfc AD |
1094 | rdev->ih.ring_obj = NULL; |
1095 | r600_ih_ring_init(rdev, 64 * 1024); | |
1096 | ||
4aac0473 JG |
1097 | r = r600_pcie_gart_init(rdev); |
1098 | if (r) | |
1099 | return r; | |
1100 | ||
779720a3 | 1101 | rdev->accel_working = true; |
fc30b8ef | 1102 | r = rv770_startup(rdev); |
3ce0a23d | 1103 | if (r) { |
655efd3d | 1104 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
fe251e2f | 1105 | r700_cp_fini(rdev); |
4d75658b | 1106 | r600_dma_fini(rdev); |
655efd3d | 1107 | r600_irq_fini(rdev); |
724c80e1 | 1108 | radeon_wb_fini(rdev); |
2898c348 | 1109 | radeon_ib_pool_fini(rdev); |
655efd3d | 1110 | radeon_irq_kms_fini(rdev); |
75c81298 | 1111 | rv770_pcie_gart_fini(rdev); |
733289c2 | 1112 | rdev->accel_working = false; |
3ce0a23d | 1113 | } |
8a8c6e7c | 1114 | |
3ce0a23d JG |
1115 | return 0; |
1116 | } | |
1117 | ||
1118 | void rv770_fini(struct radeon_device *rdev) | |
1119 | { | |
1120 | r600_blit_fini(rdev); | |
fe251e2f | 1121 | r700_cp_fini(rdev); |
4d75658b | 1122 | r600_dma_fini(rdev); |
d8f60cfc | 1123 | r600_irq_fini(rdev); |
724c80e1 | 1124 | radeon_wb_fini(rdev); |
2898c348 | 1125 | radeon_ib_pool_fini(rdev); |
d8f60cfc | 1126 | radeon_irq_kms_fini(rdev); |
4aac0473 | 1127 | rv770_pcie_gart_fini(rdev); |
16cdf04d | 1128 | r600_vram_scratch_fini(rdev); |
3ce0a23d JG |
1129 | radeon_gem_fini(rdev); |
1130 | radeon_fence_driver_fini(rdev); | |
d0269ed8 | 1131 | radeon_agp_fini(rdev); |
4c788679 | 1132 | radeon_bo_fini(rdev); |
e7d40b9a | 1133 | radeon_atombios_fini(rdev); |
3ce0a23d JG |
1134 | kfree(rdev->bios); |
1135 | rdev->bios = NULL; | |
771fe6b9 | 1136 | } |
9e46a48d AD |
1137 | |
1138 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev) | |
1139 | { | |
1140 | u32 link_width_cntl, lanes, speed_cntl, tmp; | |
1141 | u16 link_cntl2; | |
197bbb3d DA |
1142 | u32 mask; |
1143 | int ret; | |
9e46a48d | 1144 | |
d42dd579 AD |
1145 | if (radeon_pcie_gen2 == 0) |
1146 | return; | |
1147 | ||
9e46a48d AD |
1148 | if (rdev->flags & RADEON_IS_IGP) |
1149 | return; | |
1150 | ||
1151 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
1152 | return; | |
1153 | ||
1154 | /* x2 cards have a special sequence */ | |
1155 | if (ASIC_IS_X2(rdev)) | |
1156 | return; | |
1157 | ||
197bbb3d DA |
1158 | ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); |
1159 | if (ret != 0) | |
1160 | return; | |
1161 | ||
1162 | if (!(mask & DRM_PCIE_SPEED_50)) | |
1163 | return; | |
1164 | ||
1165 | DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); | |
1166 | ||
9e46a48d AD |
1167 | /* advertise upconfig capability */ |
1168 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); | |
1169 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; | |
1170 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); | |
1171 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); | |
1172 | if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { | |
1173 | lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; | |
1174 | link_width_cntl &= ~(LC_LINK_WIDTH_MASK | | |
1175 | LC_RECONFIG_ARC_MISSING_ESCAPE); | |
1176 | link_width_cntl |= lanes | LC_RECONFIG_NOW | | |
1177 | LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT; | |
1178 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); | |
1179 | } else { | |
1180 | link_width_cntl |= LC_UPCONFIGURE_DIS; | |
1181 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); | |
1182 | } | |
1183 | ||
1184 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | |
1185 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && | |
1186 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { | |
1187 | ||
1188 | tmp = RREG32(0x541c); | |
1189 | WREG32(0x541c, tmp | 0x8); | |
1190 | WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); | |
1191 | link_cntl2 = RREG16(0x4088); | |
1192 | link_cntl2 &= ~TARGET_LINK_SPEED_MASK; | |
1193 | link_cntl2 |= 0x2; | |
1194 | WREG16(0x4088, link_cntl2); | |
1195 | WREG32(MM_CFGREGS_CNTL, 0); | |
1196 | ||
1197 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | |
1198 | speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; | |
1199 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); | |
1200 | ||
1201 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | |
1202 | speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; | |
1203 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); | |
1204 | ||
1205 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | |
1206 | speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; | |
1207 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); | |
1208 | ||
1209 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | |
1210 | speed_cntl |= LC_GEN2_EN_STRAP; | |
1211 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); | |
1212 | ||
1213 | } else { | |
1214 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); | |
1215 | /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ | |
1216 | if (1) | |
1217 | link_width_cntl |= LC_UPCONFIGURE_DIS; | |
1218 | else | |
1219 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; | |
1220 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); | |
1221 | } | |
1222 | } |