Commit | Line | Data |
---|---|---|
2048e328 MY |
1 | /* |
2 | * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd | |
3 | * Author:Mark Yao <mark.yao@rock-chips.com> | |
4 | * | |
5 | * This software is licensed under the terms of the GNU General Public | |
6 | * License version 2, as published by the Free Software Foundation, and | |
7 | * may be copied, distributed, and modified under those terms. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <drm/drm.h> | |
16 | #include <drm/drmP.h> | |
63ebb9fa | 17 | #include <drm/drm_atomic.h> |
2048e328 MY |
18 | #include <drm/drm_crtc.h> |
19 | #include <drm/drm_crtc_helper.h> | |
20 | #include <drm/drm_plane_helper.h> | |
21 | ||
22 | #include <linux/kernel.h> | |
00fe6148 | 23 | #include <linux/module.h> |
2048e328 MY |
24 | #include <linux/platform_device.h> |
25 | #include <linux/clk.h> | |
26 | #include <linux/of.h> | |
27 | #include <linux/of_device.h> | |
28 | #include <linux/pm_runtime.h> | |
29 | #include <linux/component.h> | |
30 | ||
31 | #include <linux/reset.h> | |
32 | #include <linux/delay.h> | |
33 | ||
34 | #include "rockchip_drm_drv.h" | |
35 | #include "rockchip_drm_gem.h" | |
36 | #include "rockchip_drm_fb.h" | |
37 | #include "rockchip_drm_vop.h" | |
38 | ||
d49463ec MY |
39 | #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \ |
40 | vop_mask_write(x, off, mask, shift, v, write_mask, true) | |
41 | ||
42 | #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \ | |
43 | vop_mask_write(x, off, mask, shift, v, write_mask, false) | |
2048e328 MY |
44 | |
45 | #define REG_SET(x, base, reg, v, mode) \ | |
d49463ec MY |
46 | __REG_SET_##mode(x, base + reg.offset, \ |
47 | reg.mask, reg.shift, v, reg.write_mask) | |
c7647f86 | 48 | #define REG_SET_MASK(x, base, reg, mask, v, mode) \ |
d49463ec MY |
49 | __REG_SET_##mode(x, base + reg.offset, \ |
50 | mask, reg.shift, v, reg.write_mask) | |
2048e328 MY |
51 | |
52 | #define VOP_WIN_SET(x, win, name, v) \ | |
53 | REG_SET(x, win->base, win->phy->name, v, RELAXED) | |
4c156c21 MY |
54 | #define VOP_SCL_SET(x, win, name, v) \ |
55 | REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) | |
1194fffb MY |
56 | #define VOP_SCL_SET_EXT(x, win, name, v) \ |
57 | REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED) | |
2048e328 MY |
58 | #define VOP_CTRL_SET(x, name, v) \ |
59 | REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) | |
60 | ||
dbb3d944 MY |
61 | #define VOP_INTR_GET(vop, name) \ |
62 | vop_read_reg(vop, 0, &vop->data->ctrl->name) | |
63 | ||
c7647f86 JK |
64 | #define VOP_INTR_SET(vop, name, mask, v) \ |
65 | REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL) | |
dbb3d944 MY |
66 | #define VOP_INTR_SET_TYPE(vop, name, type, v) \ |
67 | do { \ | |
c7647f86 | 68 | int i, reg = 0, mask = 0; \ |
dbb3d944 | 69 | for (i = 0; i < vop->data->intr->nintrs; i++) { \ |
c7647f86 | 70 | if (vop->data->intr->intrs[i] & type) { \ |
dbb3d944 | 71 | reg |= (v) << i; \ |
c7647f86 JK |
72 | mask |= 1 << i; \ |
73 | } \ | |
dbb3d944 | 74 | } \ |
c7647f86 | 75 | VOP_INTR_SET(vop, name, mask, reg); \ |
dbb3d944 MY |
76 | } while (0) |
77 | #define VOP_INTR_GET_TYPE(vop, name, type) \ | |
78 | vop_get_intr_type(vop, &vop->data->intr->name, type) | |
79 | ||
2048e328 MY |
80 | #define VOP_WIN_GET(x, win, name) \ |
81 | vop_read_reg(x, win->base, &win->phy->name) | |
82 | ||
83 | #define VOP_WIN_GET_YRGBADDR(vop, win) \ | |
84 | vop_readl(vop, win->base + win->phy->yrgb_mst.offset) | |
85 | ||
86 | #define to_vop(x) container_of(x, struct vop, crtc) | |
87 | #define to_vop_win(x) container_of(x, struct vop_win, base) | |
63ebb9fa | 88 | #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base) |
2048e328 | 89 | |
63ebb9fa MY |
90 | struct vop_plane_state { |
91 | struct drm_plane_state base; | |
92 | int format; | |
2048e328 | 93 | dma_addr_t yrgb_mst; |
63ebb9fa | 94 | bool enable; |
2048e328 MY |
95 | }; |
96 | ||
97 | struct vop_win { | |
98 | struct drm_plane base; | |
99 | const struct vop_win_data *data; | |
100 | struct vop *vop; | |
101 | ||
4f9d39a7 DV |
102 | /* protected by dev->event_lock */ |
103 | bool enable; | |
104 | dma_addr_t yrgb_mst; | |
2048e328 MY |
105 | }; |
106 | ||
107 | struct vop { | |
108 | struct drm_crtc crtc; | |
109 | struct device *dev; | |
110 | struct drm_device *drm_dev; | |
31e980c5 | 111 | bool is_enabled; |
2048e328 | 112 | |
2048e328 MY |
113 | /* mutex vsync_ work */ |
114 | struct mutex vsync_mutex; | |
115 | bool vsync_work_pending; | |
1067219b | 116 | struct completion dsp_hold_completion; |
63ebb9fa | 117 | struct completion wait_update_complete; |
4f9d39a7 DV |
118 | |
119 | /* protected by dev->event_lock */ | |
63ebb9fa | 120 | struct drm_pending_vblank_event *event; |
2048e328 MY |
121 | |
122 | const struct vop_data *data; | |
123 | ||
124 | uint32_t *regsbak; | |
125 | void __iomem *regs; | |
126 | ||
127 | /* physical map length of vop register */ | |
128 | uint32_t len; | |
129 | ||
130 | /* one time only one process allowed to config the register */ | |
131 | spinlock_t reg_lock; | |
132 | /* lock vop irq reg */ | |
133 | spinlock_t irq_lock; | |
134 | ||
135 | unsigned int irq; | |
136 | ||
137 | /* vop AHP clk */ | |
138 | struct clk *hclk; | |
139 | /* vop dclk */ | |
140 | struct clk *dclk; | |
141 | /* vop share memory frequency */ | |
142 | struct clk *aclk; | |
143 | ||
144 | /* vop dclk reset */ | |
145 | struct reset_control *dclk_rst; | |
146 | ||
2048e328 MY |
147 | struct vop_win win[]; |
148 | }; | |
149 | ||
2048e328 MY |
150 | static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) |
151 | { | |
152 | writel(v, vop->regs + offset); | |
153 | vop->regsbak[offset >> 2] = v; | |
154 | } | |
155 | ||
156 | static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) | |
157 | { | |
158 | return readl(vop->regs + offset); | |
159 | } | |
160 | ||
161 | static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, | |
162 | const struct vop_reg *reg) | |
163 | { | |
164 | return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; | |
165 | } | |
166 | ||
2048e328 | 167 | static inline void vop_mask_write(struct vop *vop, uint32_t offset, |
d49463ec MY |
168 | uint32_t mask, uint32_t shift, uint32_t v, |
169 | bool write_mask, bool relaxed) | |
2048e328 | 170 | { |
d49463ec MY |
171 | if (!mask) |
172 | return; | |
2048e328 | 173 | |
d49463ec MY |
174 | if (write_mask) { |
175 | v = ((v << shift) & 0xffff) | (mask << (shift + 16)); | |
176 | } else { | |
2048e328 MY |
177 | uint32_t cached_val = vop->regsbak[offset >> 2]; |
178 | ||
d49463ec MY |
179 | v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); |
180 | vop->regsbak[offset >> 2] = v; | |
2048e328 | 181 | } |
d49463ec MY |
182 | |
183 | if (relaxed) | |
184 | writel_relaxed(v, vop->regs + offset); | |
185 | else | |
186 | writel(v, vop->regs + offset); | |
2048e328 MY |
187 | } |
188 | ||
dbb3d944 MY |
189 | static inline uint32_t vop_get_intr_type(struct vop *vop, |
190 | const struct vop_reg *reg, int type) | |
191 | { | |
192 | uint32_t i, ret = 0; | |
193 | uint32_t regs = vop_read_reg(vop, 0, reg); | |
194 | ||
195 | for (i = 0; i < vop->data->intr->nintrs; i++) { | |
196 | if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) | |
197 | ret |= vop->data->intr->intrs[i]; | |
198 | } | |
199 | ||
200 | return ret; | |
201 | } | |
202 | ||
0cf33fe3 MY |
203 | static inline void vop_cfg_done(struct vop *vop) |
204 | { | |
205 | VOP_CTRL_SET(vop, cfg_done, 1); | |
206 | } | |
207 | ||
85a359f2 TF |
208 | static bool has_rb_swapped(uint32_t format) |
209 | { | |
210 | switch (format) { | |
211 | case DRM_FORMAT_XBGR8888: | |
212 | case DRM_FORMAT_ABGR8888: | |
213 | case DRM_FORMAT_BGR888: | |
214 | case DRM_FORMAT_BGR565: | |
215 | return true; | |
216 | default: | |
217 | return false; | |
218 | } | |
219 | } | |
220 | ||
2048e328 MY |
221 | static enum vop_data_format vop_convert_format(uint32_t format) |
222 | { | |
223 | switch (format) { | |
224 | case DRM_FORMAT_XRGB8888: | |
225 | case DRM_FORMAT_ARGB8888: | |
85a359f2 TF |
226 | case DRM_FORMAT_XBGR8888: |
227 | case DRM_FORMAT_ABGR8888: | |
2048e328 MY |
228 | return VOP_FMT_ARGB8888; |
229 | case DRM_FORMAT_RGB888: | |
85a359f2 | 230 | case DRM_FORMAT_BGR888: |
2048e328 MY |
231 | return VOP_FMT_RGB888; |
232 | case DRM_FORMAT_RGB565: | |
85a359f2 | 233 | case DRM_FORMAT_BGR565: |
2048e328 MY |
234 | return VOP_FMT_RGB565; |
235 | case DRM_FORMAT_NV12: | |
236 | return VOP_FMT_YUV420SP; | |
237 | case DRM_FORMAT_NV16: | |
238 | return VOP_FMT_YUV422SP; | |
239 | case DRM_FORMAT_NV24: | |
240 | return VOP_FMT_YUV444SP; | |
241 | default: | |
242 | DRM_ERROR("unsupport format[%08x]\n", format); | |
243 | return -EINVAL; | |
244 | } | |
245 | } | |
246 | ||
84c7f8ca MY |
247 | static bool is_yuv_support(uint32_t format) |
248 | { | |
249 | switch (format) { | |
250 | case DRM_FORMAT_NV12: | |
251 | case DRM_FORMAT_NV16: | |
252 | case DRM_FORMAT_NV24: | |
253 | return true; | |
254 | default: | |
255 | return false; | |
256 | } | |
257 | } | |
258 | ||
2048e328 MY |
259 | static bool is_alpha_support(uint32_t format) |
260 | { | |
261 | switch (format) { | |
262 | case DRM_FORMAT_ARGB8888: | |
85a359f2 | 263 | case DRM_FORMAT_ABGR8888: |
2048e328 MY |
264 | return true; |
265 | default: | |
266 | return false; | |
267 | } | |
268 | } | |
269 | ||
4c156c21 MY |
270 | static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, |
271 | uint32_t dst, bool is_horizontal, | |
272 | int vsu_mode, int *vskiplines) | |
273 | { | |
274 | uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; | |
275 | ||
276 | if (is_horizontal) { | |
277 | if (mode == SCALE_UP) | |
278 | val = GET_SCL_FT_BIC(src, dst); | |
279 | else if (mode == SCALE_DOWN) | |
280 | val = GET_SCL_FT_BILI_DN(src, dst); | |
281 | } else { | |
282 | if (mode == SCALE_UP) { | |
283 | if (vsu_mode == SCALE_UP_BIL) | |
284 | val = GET_SCL_FT_BILI_UP(src, dst); | |
285 | else | |
286 | val = GET_SCL_FT_BIC(src, dst); | |
287 | } else if (mode == SCALE_DOWN) { | |
288 | if (vskiplines) { | |
289 | *vskiplines = scl_get_vskiplines(src, dst); | |
290 | val = scl_get_bili_dn_vskip(src, dst, | |
291 | *vskiplines); | |
292 | } else { | |
293 | val = GET_SCL_FT_BILI_DN(src, dst); | |
294 | } | |
295 | } | |
296 | } | |
297 | ||
298 | return val; | |
299 | } | |
300 | ||
301 | static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, | |
302 | uint32_t src_w, uint32_t src_h, uint32_t dst_w, | |
303 | uint32_t dst_h, uint32_t pixel_format) | |
304 | { | |
305 | uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; | |
306 | uint16_t cbcr_hor_scl_mode = SCALE_NONE; | |
307 | uint16_t cbcr_ver_scl_mode = SCALE_NONE; | |
308 | int hsub = drm_format_horz_chroma_subsampling(pixel_format); | |
309 | int vsub = drm_format_vert_chroma_subsampling(pixel_format); | |
310 | bool is_yuv = is_yuv_support(pixel_format); | |
311 | uint16_t cbcr_src_w = src_w / hsub; | |
312 | uint16_t cbcr_src_h = src_h / vsub; | |
313 | uint16_t vsu_mode; | |
314 | uint16_t lb_mode; | |
315 | uint32_t val; | |
2db00cf5 | 316 | int vskiplines = 0; |
4c156c21 MY |
317 | |
318 | if (dst_w > 3840) { | |
319 | DRM_ERROR("Maximum destination width (3840) exceeded\n"); | |
320 | return; | |
321 | } | |
322 | ||
1194fffb MY |
323 | if (!win->phy->scl->ext) { |
324 | VOP_SCL_SET(vop, win, scale_yrgb_x, | |
325 | scl_cal_scale2(src_w, dst_w)); | |
326 | VOP_SCL_SET(vop, win, scale_yrgb_y, | |
327 | scl_cal_scale2(src_h, dst_h)); | |
328 | if (is_yuv) { | |
329 | VOP_SCL_SET(vop, win, scale_cbcr_x, | |
ee8662fc | 330 | scl_cal_scale2(cbcr_src_w, dst_w)); |
1194fffb | 331 | VOP_SCL_SET(vop, win, scale_cbcr_y, |
ee8662fc | 332 | scl_cal_scale2(cbcr_src_h, dst_h)); |
1194fffb MY |
333 | } |
334 | return; | |
335 | } | |
336 | ||
4c156c21 MY |
337 | yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); |
338 | yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); | |
339 | ||
340 | if (is_yuv) { | |
341 | cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); | |
342 | cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); | |
343 | if (cbcr_hor_scl_mode == SCALE_DOWN) | |
344 | lb_mode = scl_vop_cal_lb_mode(dst_w, true); | |
345 | else | |
346 | lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); | |
347 | } else { | |
348 | if (yrgb_hor_scl_mode == SCALE_DOWN) | |
349 | lb_mode = scl_vop_cal_lb_mode(dst_w, false); | |
350 | else | |
351 | lb_mode = scl_vop_cal_lb_mode(src_w, false); | |
352 | } | |
353 | ||
1194fffb | 354 | VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); |
4c156c21 MY |
355 | if (lb_mode == LB_RGB_3840X2) { |
356 | if (yrgb_ver_scl_mode != SCALE_NONE) { | |
357 | DRM_ERROR("ERROR : not allow yrgb ver scale\n"); | |
358 | return; | |
359 | } | |
360 | if (cbcr_ver_scl_mode != SCALE_NONE) { | |
361 | DRM_ERROR("ERROR : not allow cbcr ver scale\n"); | |
362 | return; | |
363 | } | |
364 | vsu_mode = SCALE_UP_BIL; | |
365 | } else if (lb_mode == LB_RGB_2560X4) { | |
366 | vsu_mode = SCALE_UP_BIL; | |
367 | } else { | |
368 | vsu_mode = SCALE_UP_BIC; | |
369 | } | |
370 | ||
371 | val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, | |
372 | true, 0, NULL); | |
373 | VOP_SCL_SET(vop, win, scale_yrgb_x, val); | |
374 | val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, | |
375 | false, vsu_mode, &vskiplines); | |
376 | VOP_SCL_SET(vop, win, scale_yrgb_y, val); | |
377 | ||
1194fffb MY |
378 | VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); |
379 | VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); | |
4c156c21 | 380 | |
1194fffb MY |
381 | VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); |
382 | VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); | |
383 | VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); | |
384 | VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); | |
385 | VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); | |
4c156c21 MY |
386 | if (is_yuv) { |
387 | val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, | |
388 | dst_w, true, 0, NULL); | |
389 | VOP_SCL_SET(vop, win, scale_cbcr_x, val); | |
390 | val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, | |
391 | dst_h, false, vsu_mode, &vskiplines); | |
392 | VOP_SCL_SET(vop, win, scale_cbcr_y, val); | |
393 | ||
1194fffb MY |
394 | VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); |
395 | VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); | |
396 | VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); | |
397 | VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); | |
398 | VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); | |
399 | VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); | |
400 | VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); | |
4c156c21 MY |
401 | } |
402 | } | |
403 | ||
1067219b MY |
404 | static void vop_dsp_hold_valid_irq_enable(struct vop *vop) |
405 | { | |
406 | unsigned long flags; | |
407 | ||
408 | if (WARN_ON(!vop->is_enabled)) | |
409 | return; | |
410 | ||
411 | spin_lock_irqsave(&vop->irq_lock, flags); | |
412 | ||
dbb3d944 | 413 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); |
1067219b MY |
414 | |
415 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
416 | } | |
417 | ||
418 | static void vop_dsp_hold_valid_irq_disable(struct vop *vop) | |
419 | { | |
420 | unsigned long flags; | |
421 | ||
422 | if (WARN_ON(!vop->is_enabled)) | |
423 | return; | |
424 | ||
425 | spin_lock_irqsave(&vop->irq_lock, flags); | |
426 | ||
dbb3d944 | 427 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); |
1067219b MY |
428 | |
429 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
430 | } | |
431 | ||
63ebb9fa | 432 | static void vop_enable(struct drm_crtc *crtc) |
2048e328 MY |
433 | { |
434 | struct vop *vop = to_vop(crtc); | |
435 | int ret; | |
436 | ||
5d82d1a7 MY |
437 | ret = pm_runtime_get_sync(vop->dev); |
438 | if (ret < 0) { | |
439 | dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); | |
440 | return; | |
441 | } | |
442 | ||
2048e328 MY |
443 | ret = clk_enable(vop->hclk); |
444 | if (ret < 0) { | |
445 | dev_err(vop->dev, "failed to enable hclk - %d\n", ret); | |
446 | return; | |
447 | } | |
448 | ||
449 | ret = clk_enable(vop->dclk); | |
450 | if (ret < 0) { | |
451 | dev_err(vop->dev, "failed to enable dclk - %d\n", ret); | |
452 | goto err_disable_hclk; | |
453 | } | |
454 | ||
455 | ret = clk_enable(vop->aclk); | |
456 | if (ret < 0) { | |
457 | dev_err(vop->dev, "failed to enable aclk - %d\n", ret); | |
458 | goto err_disable_dclk; | |
459 | } | |
460 | ||
461 | /* | |
462 | * Slave iommu shares power, irq and clock with vop. It was associated | |
463 | * automatically with this master device via common driver code. | |
464 | * Now that we have enabled the clock we attach it to the shared drm | |
465 | * mapping. | |
466 | */ | |
467 | ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); | |
468 | if (ret) { | |
469 | dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); | |
470 | goto err_disable_aclk; | |
471 | } | |
472 | ||
77faa161 | 473 | memcpy(vop->regs, vop->regsbak, vop->len); |
52ab7891 MY |
474 | /* |
475 | * At here, vop clock & iommu is enable, R/W vop regs would be safe. | |
476 | */ | |
477 | vop->is_enabled = true; | |
478 | ||
2048e328 MY |
479 | spin_lock(&vop->reg_lock); |
480 | ||
481 | VOP_CTRL_SET(vop, standby, 0); | |
482 | ||
483 | spin_unlock(&vop->reg_lock); | |
484 | ||
485 | enable_irq(vop->irq); | |
486 | ||
b5f7b755 | 487 | drm_crtc_vblank_on(crtc); |
2048e328 MY |
488 | |
489 | return; | |
490 | ||
491 | err_disable_aclk: | |
492 | clk_disable(vop->aclk); | |
493 | err_disable_dclk: | |
494 | clk_disable(vop->dclk); | |
495 | err_disable_hclk: | |
496 | clk_disable(vop->hclk); | |
497 | } | |
498 | ||
0ad3675d | 499 | static void vop_crtc_disable(struct drm_crtc *crtc) |
2048e328 MY |
500 | { |
501 | struct vop *vop = to_vop(crtc); | |
3ed6c649 | 502 | int i; |
2048e328 | 503 | |
893b6cad DV |
504 | WARN_ON(vop->event); |
505 | ||
3ed6c649 TV |
506 | /* |
507 | * We need to make sure that all windows are disabled before we | |
508 | * disable that crtc. Otherwise we might try to scan from a destroyed | |
509 | * buffer later. | |
510 | */ | |
511 | for (i = 0; i < vop->data->win_size; i++) { | |
512 | struct vop_win *vop_win = &vop->win[i]; | |
513 | const struct vop_win_data *win = vop_win->data; | |
514 | ||
515 | spin_lock(&vop->reg_lock); | |
516 | VOP_WIN_SET(vop, win, enable, 0); | |
517 | spin_unlock(&vop->reg_lock); | |
518 | } | |
519 | ||
b5f7b755 | 520 | drm_crtc_vblank_off(crtc); |
2048e328 | 521 | |
2048e328 | 522 | /* |
1067219b MY |
523 | * Vop standby will take effect at end of current frame, |
524 | * if dsp hold valid irq happen, it means standby complete. | |
525 | * | |
526 | * we must wait standby complete when we want to disable aclk, | |
527 | * if not, memory bus maybe dead. | |
2048e328 | 528 | */ |
1067219b MY |
529 | reinit_completion(&vop->dsp_hold_completion); |
530 | vop_dsp_hold_valid_irq_enable(vop); | |
531 | ||
2048e328 MY |
532 | spin_lock(&vop->reg_lock); |
533 | ||
534 | VOP_CTRL_SET(vop, standby, 1); | |
535 | ||
536 | spin_unlock(&vop->reg_lock); | |
52ab7891 | 537 | |
1067219b MY |
538 | wait_for_completion(&vop->dsp_hold_completion); |
539 | ||
540 | vop_dsp_hold_valid_irq_disable(vop); | |
541 | ||
542 | disable_irq(vop->irq); | |
543 | ||
52ab7891 | 544 | vop->is_enabled = false; |
1067219b | 545 | |
2048e328 | 546 | /* |
1067219b | 547 | * vop standby complete, so iommu detach is safe. |
2048e328 | 548 | */ |
2048e328 MY |
549 | rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); |
550 | ||
1067219b | 551 | clk_disable(vop->dclk); |
2048e328 MY |
552 | clk_disable(vop->aclk); |
553 | clk_disable(vop->hclk); | |
5d82d1a7 | 554 | pm_runtime_put(vop->dev); |
893b6cad DV |
555 | |
556 | if (crtc->state->event && !crtc->state->active) { | |
557 | spin_lock_irq(&crtc->dev->event_lock); | |
558 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
559 | spin_unlock_irq(&crtc->dev->event_lock); | |
560 | ||
561 | crtc->state->event = NULL; | |
562 | } | |
2048e328 MY |
563 | } |
564 | ||
63ebb9fa | 565 | static void vop_plane_destroy(struct drm_plane *plane) |
2048e328 | 566 | { |
63ebb9fa | 567 | drm_plane_cleanup(plane); |
2048e328 MY |
568 | } |
569 | ||
44d0237a MY |
570 | static int vop_plane_prepare_fb(struct drm_plane *plane, |
571 | const struct drm_plane_state *new_state) | |
572 | { | |
573 | if (plane->state->fb) | |
574 | drm_framebuffer_reference(plane->state->fb); | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
579 | static void vop_plane_cleanup_fb(struct drm_plane *plane, | |
580 | const struct drm_plane_state *old_state) | |
581 | { | |
582 | if (old_state->fb) | |
583 | drm_framebuffer_unreference(old_state->fb); | |
584 | } | |
585 | ||
63ebb9fa MY |
586 | static int vop_plane_atomic_check(struct drm_plane *plane, |
587 | struct drm_plane_state *state) | |
2048e328 | 588 | { |
63ebb9fa | 589 | struct drm_crtc *crtc = state->crtc; |
92915da6 | 590 | struct drm_crtc_state *crtc_state; |
63ebb9fa | 591 | struct drm_framebuffer *fb = state->fb; |
2048e328 | 592 | struct vop_win *vop_win = to_vop_win(plane); |
63ebb9fa | 593 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); |
2048e328 | 594 | const struct vop_win_data *win = vop_win->data; |
2048e328 | 595 | int ret; |
63ebb9fa | 596 | struct drm_rect clip; |
4c156c21 MY |
597 | int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : |
598 | DRM_PLANE_HELPER_NO_SCALING; | |
599 | int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : | |
600 | DRM_PLANE_HELPER_NO_SCALING; | |
2048e328 | 601 | |
63ebb9fa MY |
602 | if (!crtc || !fb) |
603 | goto out_disable; | |
92915da6 JK |
604 | |
605 | crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); | |
606 | if (WARN_ON(!crtc_state)) | |
607 | return -EINVAL; | |
608 | ||
63ebb9fa MY |
609 | clip.x1 = 0; |
610 | clip.y1 = 0; | |
92915da6 JK |
611 | clip.x2 = crtc_state->adjusted_mode.hdisplay; |
612 | clip.y2 = crtc_state->adjusted_mode.vdisplay; | |
63ebb9fa | 613 | |
f9b96be0 VS |
614 | ret = drm_plane_helper_check_state(state, &clip, |
615 | min_scale, max_scale, | |
616 | true, true); | |
2048e328 MY |
617 | if (ret) |
618 | return ret; | |
619 | ||
f9b96be0 | 620 | if (!state->visible) |
63ebb9fa | 621 | goto out_disable; |
2048e328 | 622 | |
63ebb9fa MY |
623 | vop_plane_state->format = vop_convert_format(fb->pixel_format); |
624 | if (vop_plane_state->format < 0) | |
625 | return vop_plane_state->format; | |
84c7f8ca | 626 | |
63ebb9fa MY |
627 | /* |
628 | * Src.x1 can be odd when do clip, but yuv plane start point | |
629 | * need align with 2 pixel. | |
630 | */ | |
f9b96be0 | 631 | if (is_yuv_support(fb->pixel_format) && ((state->src.x1 >> 16) % 2)) |
2048e328 | 632 | return -EINVAL; |
2048e328 | 633 | |
63ebb9fa | 634 | vop_plane_state->enable = true; |
2048e328 | 635 | |
63ebb9fa | 636 | return 0; |
84c7f8ca | 637 | |
63ebb9fa MY |
638 | out_disable: |
639 | vop_plane_state->enable = false; | |
640 | return 0; | |
641 | } | |
2048e328 | 642 | |
63ebb9fa MY |
643 | static void vop_plane_atomic_disable(struct drm_plane *plane, |
644 | struct drm_plane_state *old_state) | |
645 | { | |
646 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state); | |
647 | struct vop_win *vop_win = to_vop_win(plane); | |
648 | const struct vop_win_data *win = vop_win->data; | |
649 | struct vop *vop = to_vop(old_state->crtc); | |
2048e328 | 650 | |
63ebb9fa MY |
651 | if (!old_state->crtc) |
652 | return; | |
2048e328 | 653 | |
4f9d39a7 DV |
654 | spin_lock_irq(&plane->dev->event_lock); |
655 | vop_win->enable = false; | |
656 | vop_win->yrgb_mst = 0; | |
657 | spin_unlock_irq(&plane->dev->event_lock); | |
658 | ||
63ebb9fa | 659 | spin_lock(&vop->reg_lock); |
2048e328 | 660 | |
63ebb9fa | 661 | VOP_WIN_SET(vop, win, enable, 0); |
84c7f8ca | 662 | |
63ebb9fa | 663 | spin_unlock(&vop->reg_lock); |
84c7f8ca | 664 | |
63ebb9fa MY |
665 | vop_plane_state->enable = false; |
666 | } | |
84c7f8ca | 667 | |
63ebb9fa MY |
668 | static void vop_plane_atomic_update(struct drm_plane *plane, |
669 | struct drm_plane_state *old_state) | |
670 | { | |
671 | struct drm_plane_state *state = plane->state; | |
672 | struct drm_crtc *crtc = state->crtc; | |
673 | struct vop_win *vop_win = to_vop_win(plane); | |
674 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); | |
675 | const struct vop_win_data *win = vop_win->data; | |
676 | struct vop *vop = to_vop(state->crtc); | |
677 | struct drm_framebuffer *fb = state->fb; | |
678 | unsigned int actual_w, actual_h; | |
679 | unsigned int dsp_stx, dsp_sty; | |
680 | uint32_t act_info, dsp_info, dsp_st; | |
ac92028e VS |
681 | struct drm_rect *src = &state->src; |
682 | struct drm_rect *dest = &state->dst; | |
63ebb9fa MY |
683 | struct drm_gem_object *obj, *uv_obj; |
684 | struct rockchip_gem_object *rk_obj, *rk_uv_obj; | |
685 | unsigned long offset; | |
686 | dma_addr_t dma_addr; | |
687 | uint32_t val; | |
688 | bool rb_swap; | |
84c7f8ca | 689 | |
2048e328 | 690 | /* |
63ebb9fa | 691 | * can't update plane when vop is disabled. |
2048e328 | 692 | */ |
4f9d39a7 | 693 | if (WARN_ON(!crtc)) |
63ebb9fa | 694 | return; |
2048e328 | 695 | |
63ebb9fa MY |
696 | if (WARN_ON(!vop->is_enabled)) |
697 | return; | |
2048e328 | 698 | |
63ebb9fa MY |
699 | if (!vop_plane_state->enable) { |
700 | vop_plane_atomic_disable(plane, old_state); | |
701 | return; | |
2048e328 | 702 | } |
63ebb9fa MY |
703 | |
704 | obj = rockchip_fb_get_gem_obj(fb, 0); | |
705 | rk_obj = to_rockchip_obj(obj); | |
706 | ||
707 | actual_w = drm_rect_width(src) >> 16; | |
708 | actual_h = drm_rect_height(src) >> 16; | |
709 | act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); | |
710 | ||
711 | dsp_info = (drm_rect_height(dest) - 1) << 16; | |
712 | dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; | |
713 | ||
714 | dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; | |
715 | dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; | |
716 | dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); | |
717 | ||
718 | offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0); | |
719 | offset += (src->y1 >> 16) * fb->pitches[0]; | |
720 | vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; | |
2048e328 | 721 | |
4f9d39a7 DV |
722 | spin_lock_irq(&plane->dev->event_lock); |
723 | vop_win->enable = true; | |
724 | vop_win->yrgb_mst = vop_plane_state->yrgb_mst; | |
725 | spin_unlock_irq(&plane->dev->event_lock); | |
726 | ||
2048e328 MY |
727 | spin_lock(&vop->reg_lock); |
728 | ||
63ebb9fa MY |
729 | VOP_WIN_SET(vop, win, format, vop_plane_state->format); |
730 | VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2); | |
731 | VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst); | |
732 | if (is_yuv_support(fb->pixel_format)) { | |
733 | int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format); | |
734 | int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format); | |
735 | int bpp = drm_format_plane_cpp(fb->pixel_format, 1); | |
736 | ||
737 | uv_obj = rockchip_fb_get_gem_obj(fb, 1); | |
738 | rk_uv_obj = to_rockchip_obj(uv_obj); | |
739 | ||
740 | offset = (src->x1 >> 16) * bpp / hsub; | |
741 | offset += (src->y1 >> 16) * fb->pitches[1] / vsub; | |
742 | ||
743 | dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; | |
744 | VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2); | |
745 | VOP_WIN_SET(vop, win, uv_mst, dma_addr); | |
84c7f8ca | 746 | } |
4c156c21 MY |
747 | |
748 | if (win->phy->scl) | |
749 | scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, | |
63ebb9fa | 750 | drm_rect_width(dest), drm_rect_height(dest), |
4c156c21 MY |
751 | fb->pixel_format); |
752 | ||
63ebb9fa MY |
753 | VOP_WIN_SET(vop, win, act_info, act_info); |
754 | VOP_WIN_SET(vop, win, dsp_info, dsp_info); | |
755 | VOP_WIN_SET(vop, win, dsp_st, dsp_st); | |
4c156c21 | 756 | |
63ebb9fa | 757 | rb_swap = has_rb_swapped(fb->pixel_format); |
85a359f2 | 758 | VOP_WIN_SET(vop, win, rb_swap, rb_swap); |
2048e328 | 759 | |
63ebb9fa | 760 | if (is_alpha_support(fb->pixel_format)) { |
2048e328 MY |
761 | VOP_WIN_SET(vop, win, dst_alpha_ctl, |
762 | DST_FACTOR_M0(ALPHA_SRC_INVERSE)); | |
763 | val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | | |
764 | SRC_ALPHA_M0(ALPHA_STRAIGHT) | | |
765 | SRC_BLEND_M0(ALPHA_PER_PIX) | | |
766 | SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | | |
767 | SRC_FACTOR_M0(ALPHA_ONE); | |
768 | VOP_WIN_SET(vop, win, src_alpha_ctl, val); | |
769 | } else { | |
770 | VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); | |
771 | } | |
772 | ||
773 | VOP_WIN_SET(vop, win, enable, 1); | |
2048e328 | 774 | spin_unlock(&vop->reg_lock); |
2048e328 MY |
775 | } |
776 | ||
63ebb9fa | 777 | static const struct drm_plane_helper_funcs plane_helper_funcs = { |
44d0237a MY |
778 | .prepare_fb = vop_plane_prepare_fb, |
779 | .cleanup_fb = vop_plane_cleanup_fb, | |
63ebb9fa MY |
780 | .atomic_check = vop_plane_atomic_check, |
781 | .atomic_update = vop_plane_atomic_update, | |
782 | .atomic_disable = vop_plane_atomic_disable, | |
783 | }; | |
2048e328 | 784 | |
8ff490ae | 785 | static void vop_atomic_plane_reset(struct drm_plane *plane) |
2048e328 | 786 | { |
63ebb9fa MY |
787 | struct vop_plane_state *vop_plane_state = |
788 | to_vop_plane_state(plane->state); | |
2048e328 | 789 | |
63ebb9fa MY |
790 | if (plane->state && plane->state->fb) |
791 | drm_framebuffer_unreference(plane->state->fb); | |
792 | ||
793 | kfree(vop_plane_state); | |
794 | vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL); | |
795 | if (!vop_plane_state) | |
796 | return; | |
2048e328 | 797 | |
63ebb9fa MY |
798 | plane->state = &vop_plane_state->base; |
799 | plane->state->plane = plane; | |
2048e328 MY |
800 | } |
801 | ||
8ff490ae | 802 | static struct drm_plane_state * |
63ebb9fa | 803 | vop_atomic_plane_duplicate_state(struct drm_plane *plane) |
2048e328 | 804 | { |
63ebb9fa MY |
805 | struct vop_plane_state *old_vop_plane_state; |
806 | struct vop_plane_state *vop_plane_state; | |
2048e328 | 807 | |
63ebb9fa MY |
808 | if (WARN_ON(!plane->state)) |
809 | return NULL; | |
2048e328 | 810 | |
63ebb9fa MY |
811 | old_vop_plane_state = to_vop_plane_state(plane->state); |
812 | vop_plane_state = kmemdup(old_vop_plane_state, | |
813 | sizeof(*vop_plane_state), GFP_KERNEL); | |
814 | if (!vop_plane_state) | |
815 | return NULL; | |
2048e328 | 816 | |
63ebb9fa MY |
817 | __drm_atomic_helper_plane_duplicate_state(plane, |
818 | &vop_plane_state->base); | |
2048e328 | 819 | |
63ebb9fa | 820 | return &vop_plane_state->base; |
2048e328 MY |
821 | } |
822 | ||
63ebb9fa MY |
823 | static void vop_atomic_plane_destroy_state(struct drm_plane *plane, |
824 | struct drm_plane_state *state) | |
2048e328 | 825 | { |
63ebb9fa MY |
826 | struct vop_plane_state *vop_state = to_vop_plane_state(state); |
827 | ||
2f701695 | 828 | __drm_atomic_helper_plane_destroy_state(state); |
63ebb9fa MY |
829 | |
830 | kfree(vop_state); | |
2048e328 MY |
831 | } |
832 | ||
833 | static const struct drm_plane_funcs vop_plane_funcs = { | |
63ebb9fa MY |
834 | .update_plane = drm_atomic_helper_update_plane, |
835 | .disable_plane = drm_atomic_helper_disable_plane, | |
2048e328 | 836 | .destroy = vop_plane_destroy, |
63ebb9fa MY |
837 | .reset = vop_atomic_plane_reset, |
838 | .atomic_duplicate_state = vop_atomic_plane_duplicate_state, | |
839 | .atomic_destroy_state = vop_atomic_plane_destroy_state, | |
2048e328 MY |
840 | }; |
841 | ||
2048e328 MY |
842 | static int vop_crtc_enable_vblank(struct drm_crtc *crtc) |
843 | { | |
844 | struct vop *vop = to_vop(crtc); | |
845 | unsigned long flags; | |
846 | ||
63ebb9fa | 847 | if (WARN_ON(!vop->is_enabled)) |
2048e328 MY |
848 | return -EPERM; |
849 | ||
850 | spin_lock_irqsave(&vop->irq_lock, flags); | |
851 | ||
dbb3d944 | 852 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); |
2048e328 MY |
853 | |
854 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
859 | static void vop_crtc_disable_vblank(struct drm_crtc *crtc) | |
860 | { | |
861 | struct vop *vop = to_vop(crtc); | |
862 | unsigned long flags; | |
863 | ||
63ebb9fa | 864 | if (WARN_ON(!vop->is_enabled)) |
2048e328 | 865 | return; |
31e980c5 | 866 | |
2048e328 | 867 | spin_lock_irqsave(&vop->irq_lock, flags); |
dbb3d944 MY |
868 | |
869 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); | |
870 | ||
2048e328 MY |
871 | spin_unlock_irqrestore(&vop->irq_lock, flags); |
872 | } | |
873 | ||
63ebb9fa MY |
874 | static void vop_crtc_wait_for_update(struct drm_crtc *crtc) |
875 | { | |
876 | struct vop *vop = to_vop(crtc); | |
877 | ||
878 | reinit_completion(&vop->wait_update_complete); | |
879 | WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100)); | |
880 | } | |
881 | ||
2048e328 MY |
882 | static const struct rockchip_crtc_funcs private_crtc_funcs = { |
883 | .enable_vblank = vop_crtc_enable_vblank, | |
884 | .disable_vblank = vop_crtc_disable_vblank, | |
63ebb9fa | 885 | .wait_for_update = vop_crtc_wait_for_update, |
2048e328 MY |
886 | }; |
887 | ||
2048e328 MY |
888 | static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, |
889 | const struct drm_display_mode *mode, | |
890 | struct drm_display_mode *adjusted_mode) | |
891 | { | |
b59b8de3 CZ |
892 | struct vop *vop = to_vop(crtc); |
893 | ||
b59b8de3 CZ |
894 | adjusted_mode->clock = |
895 | clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; | |
896 | ||
2048e328 MY |
897 | return true; |
898 | } | |
899 | ||
63ebb9fa | 900 | static void vop_crtc_enable(struct drm_crtc *crtc) |
2048e328 MY |
901 | { |
902 | struct vop *vop = to_vop(crtc); | |
4e257d9e | 903 | struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); |
63ebb9fa | 904 | struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; |
2048e328 MY |
905 | u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; |
906 | u16 hdisplay = adjusted_mode->hdisplay; | |
907 | u16 htotal = adjusted_mode->htotal; | |
908 | u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; | |
909 | u16 hact_end = hact_st + hdisplay; | |
910 | u16 vdisplay = adjusted_mode->vdisplay; | |
911 | u16 vtotal = adjusted_mode->vtotal; | |
912 | u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; | |
913 | u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; | |
914 | u16 vact_end = vact_st + vdisplay; | |
0a63bfd0 | 915 | uint32_t pin_pol, val; |
2048e328 | 916 | |
893b6cad DV |
917 | WARN_ON(vop->event); |
918 | ||
63ebb9fa | 919 | vop_enable(crtc); |
2048e328 | 920 | /* |
ce3887ed MY |
921 | * If dclk rate is zero, mean that scanout is stop, |
922 | * we don't need wait any more. | |
2048e328 | 923 | */ |
ce3887ed MY |
924 | if (clk_get_rate(vop->dclk)) { |
925 | /* | |
926 | * Rk3288 vop timing register is immediately, when configure | |
927 | * display timing on display time, may cause tearing. | |
928 | * | |
929 | * Vop standby will take effect at end of current frame, | |
930 | * if dsp hold valid irq happen, it means standby complete. | |
931 | * | |
932 | * mode set: | |
933 | * standby and wait complete --> |---- | |
934 | * | display time | |
935 | * |---- | |
936 | * |---> dsp hold irq | |
937 | * configure display timing --> | | |
938 | * standby exit | | |
939 | * | new frame start. | |
940 | */ | |
941 | ||
942 | reinit_completion(&vop->dsp_hold_completion); | |
943 | vop_dsp_hold_valid_irq_enable(vop); | |
944 | ||
945 | spin_lock(&vop->reg_lock); | |
946 | ||
947 | VOP_CTRL_SET(vop, standby, 1); | |
948 | ||
949 | spin_unlock(&vop->reg_lock); | |
950 | ||
951 | wait_for_completion(&vop->dsp_hold_completion); | |
952 | ||
953 | vop_dsp_hold_valid_irq_disable(vop); | |
954 | } | |
2048e328 | 955 | |
0a63bfd0 MY |
956 | pin_pol = 0x8; |
957 | pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; | |
958 | pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); | |
959 | VOP_CTRL_SET(vop, pin_pol, pin_pol); | |
960 | ||
4e257d9e MY |
961 | switch (s->output_type) { |
962 | case DRM_MODE_CONNECTOR_LVDS: | |
963 | VOP_CTRL_SET(vop, rgb_en, 1); | |
0a63bfd0 | 964 | VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol); |
4e257d9e MY |
965 | break; |
966 | case DRM_MODE_CONNECTOR_eDP: | |
0a63bfd0 | 967 | VOP_CTRL_SET(vop, edp_pin_pol, pin_pol); |
4e257d9e MY |
968 | VOP_CTRL_SET(vop, edp_en, 1); |
969 | break; | |
970 | case DRM_MODE_CONNECTOR_HDMIA: | |
0a63bfd0 | 971 | VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol); |
4e257d9e MY |
972 | VOP_CTRL_SET(vop, hdmi_en, 1); |
973 | break; | |
974 | case DRM_MODE_CONNECTOR_DSI: | |
0a63bfd0 | 975 | VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol); |
4e257d9e MY |
976 | VOP_CTRL_SET(vop, mipi_en, 1); |
977 | break; | |
978 | default: | |
979 | DRM_ERROR("unsupport connector_type[%d]\n", s->output_type); | |
980 | } | |
981 | VOP_CTRL_SET(vop, out_mode, s->output_mode); | |
2048e328 MY |
982 | |
983 | VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); | |
984 | val = hact_st << 16; | |
985 | val |= hact_end; | |
986 | VOP_CTRL_SET(vop, hact_st_end, val); | |
987 | VOP_CTRL_SET(vop, hpost_st_end, val); | |
988 | ||
989 | VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); | |
990 | val = vact_st << 16; | |
991 | val |= vact_end; | |
992 | VOP_CTRL_SET(vop, vact_st_end, val); | |
993 | VOP_CTRL_SET(vop, vpost_st_end, val); | |
994 | ||
2048e328 | 995 | clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); |
ce3887ed MY |
996 | |
997 | VOP_CTRL_SET(vop, standby, 0); | |
2048e328 MY |
998 | } |
999 | ||
63ebb9fa MY |
1000 | static void vop_crtc_atomic_flush(struct drm_crtc *crtc, |
1001 | struct drm_crtc_state *old_crtc_state) | |
2048e328 MY |
1002 | { |
1003 | struct vop *vop = to_vop(crtc); | |
2048e328 | 1004 | |
63ebb9fa MY |
1005 | if (WARN_ON(!vop->is_enabled)) |
1006 | return; | |
2048e328 | 1007 | |
63ebb9fa | 1008 | spin_lock(&vop->reg_lock); |
2048e328 | 1009 | |
63ebb9fa | 1010 | vop_cfg_done(vop); |
2048e328 | 1011 | |
63ebb9fa | 1012 | spin_unlock(&vop->reg_lock); |
2048e328 MY |
1013 | } |
1014 | ||
63ebb9fa MY |
1015 | static void vop_crtc_atomic_begin(struct drm_crtc *crtc, |
1016 | struct drm_crtc_state *old_crtc_state) | |
2048e328 | 1017 | { |
63ebb9fa | 1018 | struct vop *vop = to_vop(crtc); |
2048e328 | 1019 | |
893b6cad | 1020 | spin_lock_irq(&crtc->dev->event_lock); |
63ebb9fa MY |
1021 | if (crtc->state->event) { |
1022 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
893b6cad | 1023 | WARN_ON(vop->event); |
2048e328 | 1024 | |
63ebb9fa MY |
1025 | vop->event = crtc->state->event; |
1026 | crtc->state->event = NULL; | |
1027 | } | |
893b6cad | 1028 | spin_unlock_irq(&crtc->dev->event_lock); |
2048e328 MY |
1029 | } |
1030 | ||
63ebb9fa MY |
1031 | static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { |
1032 | .enable = vop_crtc_enable, | |
1033 | .disable = vop_crtc_disable, | |
1034 | .mode_fixup = vop_crtc_mode_fixup, | |
1035 | .atomic_flush = vop_crtc_atomic_flush, | |
1036 | .atomic_begin = vop_crtc_atomic_begin, | |
1037 | }; | |
1038 | ||
2048e328 MY |
1039 | static void vop_crtc_destroy(struct drm_crtc *crtc) |
1040 | { | |
1041 | drm_crtc_cleanup(crtc); | |
1042 | } | |
1043 | ||
dc0b408f JK |
1044 | static void vop_crtc_reset(struct drm_crtc *crtc) |
1045 | { | |
1046 | if (crtc->state) | |
1047 | __drm_atomic_helper_crtc_destroy_state(crtc->state); | |
1048 | kfree(crtc->state); | |
1049 | ||
1050 | crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); | |
1051 | if (crtc->state) | |
1052 | crtc->state->crtc = crtc; | |
1053 | } | |
1054 | ||
4e257d9e MY |
1055 | static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) |
1056 | { | |
1057 | struct rockchip_crtc_state *rockchip_state; | |
1058 | ||
1059 | rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); | |
1060 | if (!rockchip_state) | |
1061 | return NULL; | |
1062 | ||
1063 | __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); | |
1064 | return &rockchip_state->base; | |
1065 | } | |
1066 | ||
1067 | static void vop_crtc_destroy_state(struct drm_crtc *crtc, | |
1068 | struct drm_crtc_state *state) | |
1069 | { | |
1070 | struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); | |
1071 | ||
ec2dc6a0 | 1072 | __drm_atomic_helper_crtc_destroy_state(&s->base); |
4e257d9e MY |
1073 | kfree(s); |
1074 | } | |
1075 | ||
2048e328 | 1076 | static const struct drm_crtc_funcs vop_crtc_funcs = { |
63ebb9fa MY |
1077 | .set_config = drm_atomic_helper_set_config, |
1078 | .page_flip = drm_atomic_helper_page_flip, | |
2048e328 | 1079 | .destroy = vop_crtc_destroy, |
dc0b408f | 1080 | .reset = vop_crtc_reset, |
4e257d9e MY |
1081 | .atomic_duplicate_state = vop_crtc_duplicate_state, |
1082 | .atomic_destroy_state = vop_crtc_destroy_state, | |
2048e328 MY |
1083 | }; |
1084 | ||
63ebb9fa | 1085 | static bool vop_win_pending_is_complete(struct vop_win *vop_win) |
2048e328 | 1086 | { |
63ebb9fa | 1087 | dma_addr_t yrgb_mst; |
2048e328 | 1088 | |
4f9d39a7 | 1089 | if (!vop_win->enable) |
63ebb9fa | 1090 | return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0; |
2048e328 | 1091 | |
63ebb9fa | 1092 | yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data); |
2048e328 | 1093 | |
4f9d39a7 | 1094 | return yrgb_mst == vop_win->yrgb_mst; |
2048e328 MY |
1095 | } |
1096 | ||
63ebb9fa | 1097 | static void vop_handle_vblank(struct vop *vop) |
2048e328 | 1098 | { |
63ebb9fa MY |
1099 | struct drm_device *drm = vop->drm_dev; |
1100 | struct drm_crtc *crtc = &vop->crtc; | |
1101 | unsigned long flags; | |
1102 | int i; | |
2048e328 | 1103 | |
63ebb9fa MY |
1104 | for (i = 0; i < vop->data->win_size; i++) { |
1105 | if (!vop_win_pending_is_complete(&vop->win[i])) | |
1106 | return; | |
2048e328 MY |
1107 | } |
1108 | ||
893b6cad | 1109 | spin_lock_irqsave(&drm->event_lock, flags); |
63ebb9fa | 1110 | if (vop->event) { |
2048e328 | 1111 | |
63ebb9fa MY |
1112 | drm_crtc_send_vblank_event(crtc, vop->event); |
1113 | drm_crtc_vblank_put(crtc); | |
1114 | vop->event = NULL; | |
2048e328 | 1115 | |
2048e328 | 1116 | } |
893b6cad DV |
1117 | spin_unlock_irqrestore(&drm->event_lock, flags); |
1118 | ||
63ebb9fa MY |
1119 | if (!completion_done(&vop->wait_update_complete)) |
1120 | complete(&vop->wait_update_complete); | |
2048e328 MY |
1121 | } |
1122 | ||
1123 | static irqreturn_t vop_isr(int irq, void *data) | |
1124 | { | |
1125 | struct vop *vop = data; | |
b5f7b755 | 1126 | struct drm_crtc *crtc = &vop->crtc; |
dbb3d944 | 1127 | uint32_t active_irqs; |
2048e328 | 1128 | unsigned long flags; |
1067219b | 1129 | int ret = IRQ_NONE; |
2048e328 MY |
1130 | |
1131 | /* | |
dbb3d944 | 1132 | * interrupt register has interrupt status, enable and clear bits, we |
2048e328 MY |
1133 | * must hold irq_lock to avoid a race with enable/disable_vblank(). |
1134 | */ | |
1135 | spin_lock_irqsave(&vop->irq_lock, flags); | |
dbb3d944 MY |
1136 | |
1137 | active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); | |
2048e328 MY |
1138 | /* Clear all active interrupt sources */ |
1139 | if (active_irqs) | |
dbb3d944 MY |
1140 | VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); |
1141 | ||
2048e328 MY |
1142 | spin_unlock_irqrestore(&vop->irq_lock, flags); |
1143 | ||
1144 | /* This is expected for vop iommu irqs, since the irq is shared */ | |
1145 | if (!active_irqs) | |
1146 | return IRQ_NONE; | |
1147 | ||
1067219b MY |
1148 | if (active_irqs & DSP_HOLD_VALID_INTR) { |
1149 | complete(&vop->dsp_hold_completion); | |
1150 | active_irqs &= ~DSP_HOLD_VALID_INTR; | |
1151 | ret = IRQ_HANDLED; | |
2048e328 MY |
1152 | } |
1153 | ||
1067219b | 1154 | if (active_irqs & FS_INTR) { |
b5f7b755 | 1155 | drm_crtc_handle_vblank(crtc); |
63ebb9fa | 1156 | vop_handle_vblank(vop); |
1067219b | 1157 | active_irqs &= ~FS_INTR; |
63ebb9fa | 1158 | ret = IRQ_HANDLED; |
1067219b | 1159 | } |
2048e328 | 1160 | |
1067219b MY |
1161 | /* Unhandled irqs are spurious. */ |
1162 | if (active_irqs) | |
1163 | DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs); | |
1164 | ||
1165 | return ret; | |
2048e328 MY |
1166 | } |
1167 | ||
1168 | static int vop_create_crtc(struct vop *vop) | |
1169 | { | |
1170 | const struct vop_data *vop_data = vop->data; | |
1171 | struct device *dev = vop->dev; | |
1172 | struct drm_device *drm_dev = vop->drm_dev; | |
328b51c0 | 1173 | struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; |
2048e328 MY |
1174 | struct drm_crtc *crtc = &vop->crtc; |
1175 | struct device_node *port; | |
1176 | int ret; | |
1177 | int i; | |
1178 | ||
1179 | /* | |
1180 | * Create drm_plane for primary and cursor planes first, since we need | |
1181 | * to pass them to drm_crtc_init_with_planes, which sets the | |
1182 | * "possible_crtcs" to the newly initialized crtc. | |
1183 | */ | |
1184 | for (i = 0; i < vop_data->win_size; i++) { | |
1185 | struct vop_win *vop_win = &vop->win[i]; | |
1186 | const struct vop_win_data *win_data = vop_win->data; | |
1187 | ||
1188 | if (win_data->type != DRM_PLANE_TYPE_PRIMARY && | |
1189 | win_data->type != DRM_PLANE_TYPE_CURSOR) | |
1190 | continue; | |
1191 | ||
1192 | ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, | |
1193 | 0, &vop_plane_funcs, | |
1194 | win_data->phy->data_formats, | |
1195 | win_data->phy->nformats, | |
b0b3b795 | 1196 | win_data->type, NULL); |
2048e328 MY |
1197 | if (ret) { |
1198 | DRM_ERROR("failed to initialize plane\n"); | |
1199 | goto err_cleanup_planes; | |
1200 | } | |
1201 | ||
1202 | plane = &vop_win->base; | |
63ebb9fa | 1203 | drm_plane_helper_add(plane, &plane_helper_funcs); |
2048e328 MY |
1204 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) |
1205 | primary = plane; | |
1206 | else if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
1207 | cursor = plane; | |
1208 | } | |
1209 | ||
1210 | ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, | |
f9882876 | 1211 | &vop_crtc_funcs, NULL); |
2048e328 | 1212 | if (ret) |
328b51c0 | 1213 | goto err_cleanup_planes; |
2048e328 MY |
1214 | |
1215 | drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); | |
1216 | ||
1217 | /* | |
1218 | * Create drm_planes for overlay windows with possible_crtcs restricted | |
1219 | * to the newly created crtc. | |
1220 | */ | |
1221 | for (i = 0; i < vop_data->win_size; i++) { | |
1222 | struct vop_win *vop_win = &vop->win[i]; | |
1223 | const struct vop_win_data *win_data = vop_win->data; | |
1224 | unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); | |
1225 | ||
1226 | if (win_data->type != DRM_PLANE_TYPE_OVERLAY) | |
1227 | continue; | |
1228 | ||
1229 | ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, | |
1230 | possible_crtcs, | |
1231 | &vop_plane_funcs, | |
1232 | win_data->phy->data_formats, | |
1233 | win_data->phy->nformats, | |
b0b3b795 | 1234 | win_data->type, NULL); |
2048e328 MY |
1235 | if (ret) { |
1236 | DRM_ERROR("failed to initialize overlay plane\n"); | |
1237 | goto err_cleanup_crtc; | |
1238 | } | |
63ebb9fa | 1239 | drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); |
2048e328 MY |
1240 | } |
1241 | ||
1242 | port = of_get_child_by_name(dev->of_node, "port"); | |
1243 | if (!port) { | |
1244 | DRM_ERROR("no port node found in %s\n", | |
1245 | dev->of_node->full_name); | |
328b51c0 | 1246 | ret = -ENOENT; |
2048e328 MY |
1247 | goto err_cleanup_crtc; |
1248 | } | |
1249 | ||
1067219b | 1250 | init_completion(&vop->dsp_hold_completion); |
63ebb9fa | 1251 | init_completion(&vop->wait_update_complete); |
2048e328 | 1252 | crtc->port = port; |
b5f7b755 | 1253 | rockchip_register_crtc_funcs(crtc, &private_crtc_funcs); |
2048e328 MY |
1254 | |
1255 | return 0; | |
1256 | ||
1257 | err_cleanup_crtc: | |
1258 | drm_crtc_cleanup(crtc); | |
1259 | err_cleanup_planes: | |
328b51c0 DA |
1260 | list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, |
1261 | head) | |
2048e328 MY |
1262 | drm_plane_cleanup(plane); |
1263 | return ret; | |
1264 | } | |
1265 | ||
1266 | static void vop_destroy_crtc(struct vop *vop) | |
1267 | { | |
1268 | struct drm_crtc *crtc = &vop->crtc; | |
328b51c0 DA |
1269 | struct drm_device *drm_dev = vop->drm_dev; |
1270 | struct drm_plane *plane, *tmp; | |
2048e328 | 1271 | |
b5f7b755 | 1272 | rockchip_unregister_crtc_funcs(crtc); |
2048e328 | 1273 | of_node_put(crtc->port); |
328b51c0 DA |
1274 | |
1275 | /* | |
1276 | * We need to cleanup the planes now. Why? | |
1277 | * | |
1278 | * The planes are "&vop->win[i].base". That means the memory is | |
1279 | * all part of the big "struct vop" chunk of memory. That memory | |
1280 | * was devm allocated and associated with this component. We need to | |
1281 | * free it ourselves before vop_unbind() finishes. | |
1282 | */ | |
1283 | list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, | |
1284 | head) | |
1285 | vop_plane_destroy(plane); | |
1286 | ||
1287 | /* | |
1288 | * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() | |
1289 | * references the CRTC. | |
1290 | */ | |
2048e328 MY |
1291 | drm_crtc_cleanup(crtc); |
1292 | } | |
1293 | ||
1294 | static int vop_initial(struct vop *vop) | |
1295 | { | |
1296 | const struct vop_data *vop_data = vop->data; | |
1297 | const struct vop_reg_data *init_table = vop_data->init_table; | |
1298 | struct reset_control *ahb_rst; | |
1299 | int i, ret; | |
1300 | ||
1301 | vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); | |
1302 | if (IS_ERR(vop->hclk)) { | |
1303 | dev_err(vop->dev, "failed to get hclk source\n"); | |
1304 | return PTR_ERR(vop->hclk); | |
1305 | } | |
1306 | vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); | |
1307 | if (IS_ERR(vop->aclk)) { | |
1308 | dev_err(vop->dev, "failed to get aclk source\n"); | |
1309 | return PTR_ERR(vop->aclk); | |
1310 | } | |
1311 | vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); | |
1312 | if (IS_ERR(vop->dclk)) { | |
1313 | dev_err(vop->dev, "failed to get dclk source\n"); | |
1314 | return PTR_ERR(vop->dclk); | |
1315 | } | |
1316 | ||
2048e328 MY |
1317 | ret = clk_prepare(vop->dclk); |
1318 | if (ret < 0) { | |
1319 | dev_err(vop->dev, "failed to prepare dclk\n"); | |
d7b53fd9 | 1320 | return ret; |
2048e328 MY |
1321 | } |
1322 | ||
d7b53fd9 SS |
1323 | /* Enable both the hclk and aclk to setup the vop */ |
1324 | ret = clk_prepare_enable(vop->hclk); | |
2048e328 | 1325 | if (ret < 0) { |
d7b53fd9 | 1326 | dev_err(vop->dev, "failed to prepare/enable hclk\n"); |
2048e328 MY |
1327 | goto err_unprepare_dclk; |
1328 | } | |
1329 | ||
d7b53fd9 | 1330 | ret = clk_prepare_enable(vop->aclk); |
2048e328 | 1331 | if (ret < 0) { |
d7b53fd9 SS |
1332 | dev_err(vop->dev, "failed to prepare/enable aclk\n"); |
1333 | goto err_disable_hclk; | |
2048e328 | 1334 | } |
d7b53fd9 | 1335 | |
2048e328 MY |
1336 | /* |
1337 | * do hclk_reset, reset all vop registers. | |
1338 | */ | |
1339 | ahb_rst = devm_reset_control_get(vop->dev, "ahb"); | |
1340 | if (IS_ERR(ahb_rst)) { | |
1341 | dev_err(vop->dev, "failed to get ahb reset\n"); | |
1342 | ret = PTR_ERR(ahb_rst); | |
d7b53fd9 | 1343 | goto err_disable_aclk; |
2048e328 MY |
1344 | } |
1345 | reset_control_assert(ahb_rst); | |
1346 | usleep_range(10, 20); | |
1347 | reset_control_deassert(ahb_rst); | |
1348 | ||
1349 | memcpy(vop->regsbak, vop->regs, vop->len); | |
1350 | ||
1351 | for (i = 0; i < vop_data->table_size; i++) | |
1352 | vop_writel(vop, init_table[i].offset, init_table[i].value); | |
1353 | ||
1354 | for (i = 0; i < vop_data->win_size; i++) { | |
1355 | const struct vop_win_data *win = &vop_data->win[i]; | |
1356 | ||
1357 | VOP_WIN_SET(vop, win, enable, 0); | |
1358 | } | |
1359 | ||
1360 | vop_cfg_done(vop); | |
1361 | ||
1362 | /* | |
1363 | * do dclk_reset, let all config take affect. | |
1364 | */ | |
1365 | vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); | |
1366 | if (IS_ERR(vop->dclk_rst)) { | |
1367 | dev_err(vop->dev, "failed to get dclk reset\n"); | |
1368 | ret = PTR_ERR(vop->dclk_rst); | |
d7b53fd9 | 1369 | goto err_disable_aclk; |
2048e328 MY |
1370 | } |
1371 | reset_control_assert(vop->dclk_rst); | |
1372 | usleep_range(10, 20); | |
1373 | reset_control_deassert(vop->dclk_rst); | |
1374 | ||
1375 | clk_disable(vop->hclk); | |
d7b53fd9 | 1376 | clk_disable(vop->aclk); |
2048e328 | 1377 | |
31e980c5 | 1378 | vop->is_enabled = false; |
2048e328 MY |
1379 | |
1380 | return 0; | |
1381 | ||
d7b53fd9 SS |
1382 | err_disable_aclk: |
1383 | clk_disable_unprepare(vop->aclk); | |
2048e328 | 1384 | err_disable_hclk: |
d7b53fd9 | 1385 | clk_disable_unprepare(vop->hclk); |
2048e328 MY |
1386 | err_unprepare_dclk: |
1387 | clk_unprepare(vop->dclk); | |
2048e328 MY |
1388 | return ret; |
1389 | } | |
1390 | ||
1391 | /* | |
1392 | * Initialize the vop->win array elements. | |
1393 | */ | |
1394 | static void vop_win_init(struct vop *vop) | |
1395 | { | |
1396 | const struct vop_data *vop_data = vop->data; | |
1397 | unsigned int i; | |
1398 | ||
1399 | for (i = 0; i < vop_data->win_size; i++) { | |
1400 | struct vop_win *vop_win = &vop->win[i]; | |
1401 | const struct vop_win_data *win_data = &vop_data->win[i]; | |
1402 | ||
1403 | vop_win->data = win_data; | |
1404 | vop_win->vop = vop; | |
2048e328 MY |
1405 | } |
1406 | } | |
1407 | ||
1408 | static int vop_bind(struct device *dev, struct device *master, void *data) | |
1409 | { | |
1410 | struct platform_device *pdev = to_platform_device(dev); | |
2048e328 MY |
1411 | const struct vop_data *vop_data; |
1412 | struct drm_device *drm_dev = data; | |
1413 | struct vop *vop; | |
1414 | struct resource *res; | |
1415 | size_t alloc_size; | |
3ea68922 | 1416 | int ret, irq; |
2048e328 | 1417 | |
a67719d1 | 1418 | vop_data = of_device_get_match_data(dev); |
2048e328 MY |
1419 | if (!vop_data) |
1420 | return -ENODEV; | |
1421 | ||
1422 | /* Allocate vop struct and its vop_win array */ | |
1423 | alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; | |
1424 | vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); | |
1425 | if (!vop) | |
1426 | return -ENOMEM; | |
1427 | ||
1428 | vop->dev = dev; | |
1429 | vop->data = vop_data; | |
1430 | vop->drm_dev = drm_dev; | |
1431 | dev_set_drvdata(dev, vop); | |
1432 | ||
1433 | vop_win_init(vop); | |
1434 | ||
1435 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1436 | vop->len = resource_size(res); | |
1437 | vop->regs = devm_ioremap_resource(dev, res); | |
1438 | if (IS_ERR(vop->regs)) | |
1439 | return PTR_ERR(vop->regs); | |
1440 | ||
1441 | vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); | |
1442 | if (!vop->regsbak) | |
1443 | return -ENOMEM; | |
1444 | ||
1445 | ret = vop_initial(vop); | |
1446 | if (ret < 0) { | |
1447 | dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); | |
1448 | return ret; | |
1449 | } | |
1450 | ||
3ea68922 HS |
1451 | irq = platform_get_irq(pdev, 0); |
1452 | if (irq < 0) { | |
2048e328 | 1453 | dev_err(dev, "cannot find irq for vop\n"); |
3ea68922 | 1454 | return irq; |
2048e328 | 1455 | } |
3ea68922 | 1456 | vop->irq = (unsigned int)irq; |
2048e328 MY |
1457 | |
1458 | spin_lock_init(&vop->reg_lock); | |
1459 | spin_lock_init(&vop->irq_lock); | |
1460 | ||
1461 | mutex_init(&vop->vsync_mutex); | |
1462 | ||
63ebb9fa MY |
1463 | ret = devm_request_irq(dev, vop->irq, vop_isr, |
1464 | IRQF_SHARED, dev_name(dev), vop); | |
2048e328 MY |
1465 | if (ret) |
1466 | return ret; | |
1467 | ||
1468 | /* IRQ is initially disabled; it gets enabled in power_on */ | |
1469 | disable_irq(vop->irq); | |
1470 | ||
1471 | ret = vop_create_crtc(vop); | |
1472 | if (ret) | |
1473 | return ret; | |
1474 | ||
1475 | pm_runtime_enable(&pdev->dev); | |
1476 | return 0; | |
1477 | } | |
1478 | ||
1479 | static void vop_unbind(struct device *dev, struct device *master, void *data) | |
1480 | { | |
1481 | struct vop *vop = dev_get_drvdata(dev); | |
1482 | ||
1483 | pm_runtime_disable(dev); | |
1484 | vop_destroy_crtc(vop); | |
1485 | } | |
1486 | ||
a67719d1 | 1487 | const struct component_ops vop_component_ops = { |
2048e328 MY |
1488 | .bind = vop_bind, |
1489 | .unbind = vop_unbind, | |
1490 | }; | |
54255e81 | 1491 | EXPORT_SYMBOL_GPL(vop_component_ops); |