Commit | Line | Data |
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f32c4c50 BG |
1 | /* |
2 | * Copyright (C) STMicroelectronics SA 2014 | |
3 | * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics. | |
4 | * License terms: GNU General Public License (GPL), version 2 | |
5 | */ | |
6 | ||
7 | #include <linux/clk.h> | |
8 | #include <linux/component.h> | |
755ce376 | 9 | #include <linux/debugfs.h> |
f32c4c50 BG |
10 | #include <linux/module.h> |
11 | #include <linux/of_gpio.h> | |
12 | #include <linux/platform_device.h> | |
13 | ||
14 | #include <drm/drmP.h> | |
de4b00b0 | 15 | #include <drm/drm_atomic_helper.h> |
f32c4c50 BG |
16 | #include <drm/drm_crtc_helper.h> |
17 | #include <drm/drm_panel.h> | |
18 | ||
19 | #include "sti_awg_utils.h" | |
20 | #include "sti_mixer.h" | |
21 | ||
22 | /* DVO registers */ | |
23 | #define DVO_AWG_DIGSYNC_CTRL 0x0000 | |
24 | #define DVO_DOF_CFG 0x0004 | |
25 | #define DVO_LUT_PROG_LOW 0x0008 | |
26 | #define DVO_LUT_PROG_MID 0x000C | |
27 | #define DVO_LUT_PROG_HIGH 0x0010 | |
28 | #define DVO_DIGSYNC_INSTR_I 0x0100 | |
29 | ||
30 | #define DVO_AWG_CTRL_EN BIT(0) | |
31 | #define DVO_AWG_FRAME_BASED_SYNC BIT(2) | |
32 | ||
33 | #define DVO_DOF_EN_LOWBYTE BIT(0) | |
34 | #define DVO_DOF_EN_MIDBYTE BIT(1) | |
35 | #define DVO_DOF_EN_HIGHBYTE BIT(2) | |
36 | #define DVO_DOF_EN BIT(6) | |
37 | #define DVO_DOF_MOD_COUNT_SHIFT 8 | |
38 | ||
39 | #define DVO_LUT_ZERO 0 | |
40 | #define DVO_LUT_Y_G 1 | |
41 | #define DVO_LUT_Y_G_DEL 2 | |
42 | #define DVO_LUT_CB_B 3 | |
43 | #define DVO_LUT_CB_B_DEL 4 | |
44 | #define DVO_LUT_CR_R 5 | |
45 | #define DVO_LUT_CR_R_DEL 6 | |
46 | #define DVO_LUT_HOLD 7 | |
47 | ||
48 | struct dvo_config { | |
49 | u32 flags; | |
50 | u32 lowbyte; | |
51 | u32 midbyte; | |
52 | u32 highbyte; | |
53 | int (*awg_fwgen_fct)( | |
54 | struct awg_code_generation_params *fw_gen_params, | |
55 | struct awg_timing *timing); | |
56 | }; | |
57 | ||
58 | static struct dvo_config rgb_24bit_de_cfg = { | |
59 | .flags = (0L << DVO_DOF_MOD_COUNT_SHIFT), | |
60 | .lowbyte = DVO_LUT_CR_R, | |
61 | .midbyte = DVO_LUT_Y_G, | |
62 | .highbyte = DVO_LUT_CB_B, | |
63 | .awg_fwgen_fct = sti_awg_generate_code_data_enable_mode, | |
64 | }; | |
65 | ||
66 | /** | |
67 | * STI digital video output structure | |
68 | * | |
69 | * @dev: driver device | |
70 | * @drm_dev: pointer to drm device | |
71 | * @mode: current display mode selected | |
72 | * @regs: dvo registers | |
73 | * @clk_pix: pixel clock for dvo | |
74 | * @clk: clock for dvo | |
75 | * @clk_main_parent: dvo parent clock if main path used | |
76 | * @clk_aux_parent: dvo parent clock if aux path used | |
77 | * @panel_node: panel node reference from device tree | |
78 | * @panel: reference to the panel connected to the dvo | |
79 | * @enabled: true if dvo is enabled else false | |
80 | * @encoder: drm_encoder it is bound | |
81 | */ | |
82 | struct sti_dvo { | |
83 | struct device dev; | |
84 | struct drm_device *drm_dev; | |
85 | struct drm_display_mode mode; | |
86 | void __iomem *regs; | |
87 | struct clk *clk_pix; | |
88 | struct clk *clk; | |
89 | struct clk *clk_main_parent; | |
90 | struct clk *clk_aux_parent; | |
91 | struct device_node *panel_node; | |
92 | struct drm_panel *panel; | |
93 | struct dvo_config *config; | |
94 | bool enabled; | |
95 | struct drm_encoder *encoder; | |
384764c3 | 96 | struct drm_bridge *bridge; |
f32c4c50 BG |
97 | }; |
98 | ||
99 | struct sti_dvo_connector { | |
100 | struct drm_connector drm_connector; | |
101 | struct drm_encoder *encoder; | |
102 | struct sti_dvo *dvo; | |
103 | }; | |
104 | ||
105 | #define to_sti_dvo_connector(x) \ | |
106 | container_of(x, struct sti_dvo_connector, drm_connector) | |
107 | ||
108 | #define BLANKING_LEVEL 16 | |
109 | int dvo_awg_generate_code(struct sti_dvo *dvo, u8 *ram_size, u32 *ram_code) | |
110 | { | |
111 | struct drm_display_mode *mode = &dvo->mode; | |
112 | struct dvo_config *config = dvo->config; | |
113 | struct awg_code_generation_params fw_gen_params; | |
114 | struct awg_timing timing; | |
115 | ||
116 | fw_gen_params.ram_code = ram_code; | |
117 | fw_gen_params.instruction_offset = 0; | |
118 | ||
119 | timing.total_lines = mode->vtotal; | |
120 | timing.active_lines = mode->vdisplay; | |
121 | timing.blanking_lines = mode->vsync_start - mode->vdisplay; | |
122 | timing.trailing_lines = mode->vtotal - mode->vsync_start; | |
123 | timing.total_pixels = mode->htotal; | |
124 | timing.active_pixels = mode->hdisplay; | |
125 | timing.blanking_pixels = mode->hsync_start - mode->hdisplay; | |
126 | timing.trailing_pixels = mode->htotal - mode->hsync_start; | |
127 | timing.blanking_level = BLANKING_LEVEL; | |
128 | ||
129 | if (config->awg_fwgen_fct(&fw_gen_params, &timing)) { | |
130 | DRM_ERROR("AWG firmware not properly generated\n"); | |
131 | return -EINVAL; | |
132 | } | |
133 | ||
134 | *ram_size = fw_gen_params.instruction_offset; | |
135 | ||
136 | return 0; | |
137 | } | |
138 | ||
139 | /* Configure AWG, writing instructions | |
140 | * | |
141 | * @dvo: pointer to DVO structure | |
142 | * @awg_ram_code: pointer to AWG instructions table | |
143 | * @nb: nb of AWG instructions | |
144 | */ | |
145 | static void dvo_awg_configure(struct sti_dvo *dvo, u32 *awg_ram_code, int nb) | |
146 | { | |
147 | int i; | |
148 | ||
149 | DRM_DEBUG_DRIVER("\n"); | |
150 | ||
151 | for (i = 0; i < nb; i++) | |
152 | writel(awg_ram_code[i], | |
153 | dvo->regs + DVO_DIGSYNC_INSTR_I + i * 4); | |
154 | for (i = nb; i < AWG_MAX_INST; i++) | |
155 | writel(0, dvo->regs + DVO_DIGSYNC_INSTR_I + i * 4); | |
156 | ||
157 | writel(DVO_AWG_CTRL_EN, dvo->regs + DVO_AWG_DIGSYNC_CTRL); | |
158 | } | |
159 | ||
755ce376 VA |
160 | #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ |
161 | readl(dvo->regs + reg)) | |
162 | ||
163 | static void dvo_dbg_awg_microcode(struct seq_file *s, void __iomem *reg) | |
164 | { | |
165 | unsigned int i; | |
166 | ||
167 | seq_puts(s, "\n\n"); | |
168 | seq_puts(s, " DVO AWG microcode:"); | |
169 | for (i = 0; i < AWG_MAX_INST; i++) { | |
170 | if (i % 8 == 0) | |
171 | seq_printf(s, "\n %04X:", i); | |
172 | seq_printf(s, " %04X", readl(reg + i * 4)); | |
173 | } | |
174 | } | |
175 | ||
176 | static int dvo_dbg_show(struct seq_file *s, void *data) | |
177 | { | |
178 | struct drm_info_node *node = s->private; | |
179 | struct sti_dvo *dvo = (struct sti_dvo *)node->info_ent->data; | |
180 | struct drm_device *dev = node->minor->dev; | |
181 | int ret; | |
182 | ||
183 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
184 | if (ret) | |
185 | return ret; | |
186 | ||
187 | seq_printf(s, "DVO: (vaddr = 0x%p)", dvo->regs); | |
188 | DBGFS_DUMP(DVO_AWG_DIGSYNC_CTRL); | |
189 | DBGFS_DUMP(DVO_DOF_CFG); | |
190 | DBGFS_DUMP(DVO_LUT_PROG_LOW); | |
191 | DBGFS_DUMP(DVO_LUT_PROG_MID); | |
192 | DBGFS_DUMP(DVO_LUT_PROG_HIGH); | |
193 | dvo_dbg_awg_microcode(s, dvo->regs + DVO_DIGSYNC_INSTR_I); | |
194 | seq_puts(s, "\n"); | |
195 | ||
196 | mutex_unlock(&dev->struct_mutex); | |
197 | return 0; | |
198 | } | |
199 | ||
200 | static struct drm_info_list dvo_debugfs_files[] = { | |
201 | { "dvo", dvo_dbg_show, 0, NULL }, | |
202 | }; | |
203 | ||
204 | static void dvo_debugfs_exit(struct sti_dvo *dvo, struct drm_minor *minor) | |
205 | { | |
206 | drm_debugfs_remove_files(dvo_debugfs_files, | |
207 | ARRAY_SIZE(dvo_debugfs_files), | |
208 | minor); | |
209 | } | |
210 | ||
211 | static int dvo_debugfs_init(struct sti_dvo *dvo, struct drm_minor *minor) | |
212 | { | |
213 | unsigned int i; | |
214 | ||
215 | for (i = 0; i < ARRAY_SIZE(dvo_debugfs_files); i++) | |
216 | dvo_debugfs_files[i].data = dvo; | |
217 | ||
218 | return drm_debugfs_create_files(dvo_debugfs_files, | |
219 | ARRAY_SIZE(dvo_debugfs_files), | |
220 | minor->debugfs_root, minor); | |
221 | } | |
222 | ||
f32c4c50 BG |
223 | static void sti_dvo_disable(struct drm_bridge *bridge) |
224 | { | |
225 | struct sti_dvo *dvo = bridge->driver_private; | |
226 | ||
227 | if (!dvo->enabled) | |
228 | return; | |
229 | ||
230 | DRM_DEBUG_DRIVER("\n"); | |
231 | ||
232 | if (dvo->config->awg_fwgen_fct) | |
233 | writel(0x00000000, dvo->regs + DVO_AWG_DIGSYNC_CTRL); | |
234 | ||
235 | writel(0x00000000, dvo->regs + DVO_DOF_CFG); | |
236 | ||
237 | if (dvo->panel) | |
238 | dvo->panel->funcs->disable(dvo->panel); | |
239 | ||
240 | /* Disable/unprepare dvo clock */ | |
241 | clk_disable_unprepare(dvo->clk_pix); | |
242 | clk_disable_unprepare(dvo->clk); | |
243 | ||
244 | dvo->enabled = false; | |
245 | } | |
246 | ||
247 | static void sti_dvo_pre_enable(struct drm_bridge *bridge) | |
248 | { | |
249 | struct sti_dvo *dvo = bridge->driver_private; | |
250 | struct dvo_config *config = dvo->config; | |
251 | u32 val; | |
252 | ||
253 | DRM_DEBUG_DRIVER("\n"); | |
254 | ||
255 | if (dvo->enabled) | |
256 | return; | |
257 | ||
258 | /* Make sure DVO is disabled */ | |
259 | writel(0x00000000, dvo->regs + DVO_DOF_CFG); | |
260 | writel(0x00000000, dvo->regs + DVO_AWG_DIGSYNC_CTRL); | |
261 | ||
262 | if (config->awg_fwgen_fct) { | |
263 | u8 nb_instr; | |
264 | u32 awg_ram_code[AWG_MAX_INST]; | |
265 | /* Configure AWG */ | |
266 | if (!dvo_awg_generate_code(dvo, &nb_instr, awg_ram_code)) | |
267 | dvo_awg_configure(dvo, awg_ram_code, nb_instr); | |
268 | else | |
269 | return; | |
270 | } | |
271 | ||
272 | /* Prepare/enable clocks */ | |
273 | if (clk_prepare_enable(dvo->clk_pix)) | |
274 | DRM_ERROR("Failed to prepare/enable dvo_pix clk\n"); | |
275 | if (clk_prepare_enable(dvo->clk)) | |
276 | DRM_ERROR("Failed to prepare/enable dvo clk\n"); | |
277 | ||
278 | if (dvo->panel) | |
279 | dvo->panel->funcs->enable(dvo->panel); | |
280 | ||
281 | /* Set LUT */ | |
282 | writel(config->lowbyte, dvo->regs + DVO_LUT_PROG_LOW); | |
283 | writel(config->midbyte, dvo->regs + DVO_LUT_PROG_MID); | |
284 | writel(config->highbyte, dvo->regs + DVO_LUT_PROG_HIGH); | |
285 | ||
286 | /* Digital output formatter config */ | |
287 | val = (config->flags | DVO_DOF_EN); | |
288 | writel(val, dvo->regs + DVO_DOF_CFG); | |
289 | ||
290 | dvo->enabled = true; | |
291 | } | |
292 | ||
293 | static void sti_dvo_set_mode(struct drm_bridge *bridge, | |
294 | struct drm_display_mode *mode, | |
295 | struct drm_display_mode *adjusted_mode) | |
296 | { | |
297 | struct sti_dvo *dvo = bridge->driver_private; | |
298 | struct sti_mixer *mixer = to_sti_mixer(dvo->encoder->crtc); | |
299 | int rate = mode->clock * 1000; | |
300 | struct clk *clkp; | |
301 | int ret; | |
302 | ||
303 | DRM_DEBUG_DRIVER("\n"); | |
304 | ||
305 | memcpy(&dvo->mode, mode, sizeof(struct drm_display_mode)); | |
306 | ||
307 | /* According to the path used (main or aux), the dvo clocks should | |
308 | * have a different parent clock. */ | |
309 | if (mixer->id == STI_MIXER_MAIN) | |
310 | clkp = dvo->clk_main_parent; | |
311 | else | |
312 | clkp = dvo->clk_aux_parent; | |
313 | ||
314 | if (clkp) { | |
315 | clk_set_parent(dvo->clk_pix, clkp); | |
316 | clk_set_parent(dvo->clk, clkp); | |
317 | } | |
318 | ||
319 | /* DVO clocks = compositor clock */ | |
320 | ret = clk_set_rate(dvo->clk_pix, rate); | |
321 | if (ret < 0) { | |
322 | DRM_ERROR("Cannot set rate (%dHz) for dvo_pix clk\n", rate); | |
323 | return; | |
324 | } | |
325 | ||
326 | ret = clk_set_rate(dvo->clk, rate); | |
327 | if (ret < 0) { | |
328 | DRM_ERROR("Cannot set rate (%dHz) for dvo clk\n", rate); | |
329 | return; | |
330 | } | |
331 | ||
332 | /* For now, we only support 24bit data enable (DE) synchro format */ | |
333 | dvo->config = &rgb_24bit_de_cfg; | |
334 | } | |
335 | ||
336 | static void sti_dvo_bridge_nope(struct drm_bridge *bridge) | |
337 | { | |
338 | /* do nothing */ | |
339 | } | |
340 | ||
f32c4c50 BG |
341 | static const struct drm_bridge_funcs sti_dvo_bridge_funcs = { |
342 | .pre_enable = sti_dvo_pre_enable, | |
343 | .enable = sti_dvo_bridge_nope, | |
344 | .disable = sti_dvo_disable, | |
345 | .post_disable = sti_dvo_bridge_nope, | |
346 | .mode_set = sti_dvo_set_mode, | |
f32c4c50 BG |
347 | }; |
348 | ||
349 | static int sti_dvo_connector_get_modes(struct drm_connector *connector) | |
350 | { | |
351 | struct sti_dvo_connector *dvo_connector | |
352 | = to_sti_dvo_connector(connector); | |
353 | struct sti_dvo *dvo = dvo_connector->dvo; | |
354 | ||
355 | if (dvo->panel) | |
356 | return dvo->panel->funcs->get_modes(dvo->panel); | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
361 | #define CLK_TOLERANCE_HZ 50 | |
362 | ||
363 | static int sti_dvo_connector_mode_valid(struct drm_connector *connector, | |
364 | struct drm_display_mode *mode) | |
365 | { | |
366 | int target = mode->clock * 1000; | |
367 | int target_min = target - CLK_TOLERANCE_HZ; | |
368 | int target_max = target + CLK_TOLERANCE_HZ; | |
369 | int result; | |
370 | struct sti_dvo_connector *dvo_connector | |
371 | = to_sti_dvo_connector(connector); | |
372 | struct sti_dvo *dvo = dvo_connector->dvo; | |
373 | ||
374 | result = clk_round_rate(dvo->clk_pix, target); | |
375 | ||
376 | DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n", | |
377 | target, result); | |
378 | ||
379 | if ((result < target_min) || (result > target_max)) { | |
380 | DRM_DEBUG_DRIVER("dvo pixclk=%d not supported\n", target); | |
381 | return MODE_BAD; | |
382 | } | |
383 | ||
384 | return MODE_OK; | |
385 | } | |
386 | ||
387 | struct drm_encoder *sti_dvo_best_encoder(struct drm_connector *connector) | |
388 | { | |
389 | struct sti_dvo_connector *dvo_connector | |
390 | = to_sti_dvo_connector(connector); | |
391 | ||
392 | /* Best encoder is the one associated during connector creation */ | |
393 | return dvo_connector->encoder; | |
394 | } | |
395 | ||
c5de4853 VS |
396 | static const |
397 | struct drm_connector_helper_funcs sti_dvo_connector_helper_funcs = { | |
f32c4c50 BG |
398 | .get_modes = sti_dvo_connector_get_modes, |
399 | .mode_valid = sti_dvo_connector_mode_valid, | |
400 | .best_encoder = sti_dvo_best_encoder, | |
401 | }; | |
402 | ||
403 | static enum drm_connector_status | |
404 | sti_dvo_connector_detect(struct drm_connector *connector, bool force) | |
405 | { | |
406 | struct sti_dvo_connector *dvo_connector | |
407 | = to_sti_dvo_connector(connector); | |
408 | struct sti_dvo *dvo = dvo_connector->dvo; | |
409 | ||
410 | DRM_DEBUG_DRIVER("\n"); | |
411 | ||
974c3bb5 | 412 | if (!dvo->panel) { |
f32c4c50 | 413 | dvo->panel = of_drm_find_panel(dvo->panel_node); |
974c3bb5 VA |
414 | if (dvo->panel) |
415 | drm_panel_attach(dvo->panel, connector); | |
416 | } | |
f32c4c50 BG |
417 | |
418 | if (dvo->panel) | |
974c3bb5 | 419 | return connector_status_connected; |
f32c4c50 BG |
420 | |
421 | return connector_status_disconnected; | |
422 | } | |
423 | ||
424 | static void sti_dvo_connector_destroy(struct drm_connector *connector) | |
425 | { | |
426 | struct sti_dvo_connector *dvo_connector | |
427 | = to_sti_dvo_connector(connector); | |
428 | ||
429 | drm_connector_unregister(connector); | |
430 | drm_connector_cleanup(connector); | |
431 | kfree(dvo_connector); | |
432 | } | |
433 | ||
c5de4853 | 434 | static const struct drm_connector_funcs sti_dvo_connector_funcs = { |
de4b00b0 | 435 | .dpms = drm_atomic_helper_connector_dpms, |
f32c4c50 BG |
436 | .fill_modes = drm_helper_probe_single_connector_modes, |
437 | .detect = sti_dvo_connector_detect, | |
438 | .destroy = sti_dvo_connector_destroy, | |
de4b00b0 BG |
439 | .reset = drm_atomic_helper_connector_reset, |
440 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, | |
441 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
f32c4c50 BG |
442 | }; |
443 | ||
444 | static struct drm_encoder *sti_dvo_find_encoder(struct drm_device *dev) | |
445 | { | |
446 | struct drm_encoder *encoder; | |
447 | ||
448 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
449 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) | |
450 | return encoder; | |
451 | } | |
452 | ||
453 | return NULL; | |
454 | } | |
455 | ||
456 | static int sti_dvo_bind(struct device *dev, struct device *master, void *data) | |
457 | { | |
458 | struct sti_dvo *dvo = dev_get_drvdata(dev); | |
459 | struct drm_device *drm_dev = data; | |
460 | struct drm_encoder *encoder; | |
461 | struct sti_dvo_connector *connector; | |
462 | struct drm_connector *drm_connector; | |
463 | struct drm_bridge *bridge; | |
464 | int err; | |
465 | ||
466 | /* Set the drm device handle */ | |
467 | dvo->drm_dev = drm_dev; | |
468 | ||
469 | encoder = sti_dvo_find_encoder(drm_dev); | |
470 | if (!encoder) | |
471 | return -ENOMEM; | |
472 | ||
473 | connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL); | |
474 | if (!connector) | |
475 | return -ENOMEM; | |
476 | ||
477 | connector->dvo = dvo; | |
478 | ||
479 | bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL); | |
480 | if (!bridge) | |
481 | return -ENOMEM; | |
482 | ||
483 | bridge->driver_private = dvo; | |
384764c3 DA |
484 | bridge->funcs = &sti_dvo_bridge_funcs; |
485 | bridge->of_node = dvo->dev.of_node; | |
486 | err = drm_bridge_add(bridge); | |
487 | if (err) { | |
488 | DRM_ERROR("Failed to add bridge\n"); | |
489 | return err; | |
490 | } | |
f32c4c50 | 491 | |
384764c3 DA |
492 | err = drm_bridge_attach(drm_dev, bridge); |
493 | if (err) { | |
494 | DRM_ERROR("Failed to attach bridge\n"); | |
495 | return err; | |
496 | } | |
497 | ||
498 | dvo->bridge = bridge; | |
f32c4c50 BG |
499 | encoder->bridge = bridge; |
500 | connector->encoder = encoder; | |
501 | dvo->encoder = encoder; | |
502 | ||
503 | drm_connector = (struct drm_connector *)connector; | |
504 | ||
505 | drm_connector->polled = DRM_CONNECTOR_POLL_HPD; | |
506 | ||
507 | drm_connector_init(drm_dev, drm_connector, | |
508 | &sti_dvo_connector_funcs, DRM_MODE_CONNECTOR_LVDS); | |
509 | drm_connector_helper_add(drm_connector, | |
510 | &sti_dvo_connector_helper_funcs); | |
511 | ||
512 | err = drm_connector_register(drm_connector); | |
513 | if (err) | |
514 | goto err_connector; | |
515 | ||
516 | err = drm_mode_connector_attach_encoder(drm_connector, encoder); | |
517 | if (err) { | |
518 | DRM_ERROR("Failed to attach a connector to a encoder\n"); | |
519 | goto err_sysfs; | |
520 | } | |
521 | ||
755ce376 VA |
522 | if (dvo_debugfs_init(dvo, drm_dev->primary)) |
523 | DRM_ERROR("DVO debugfs setup failed\n"); | |
524 | ||
f32c4c50 BG |
525 | return 0; |
526 | ||
527 | err_sysfs: | |
528 | drm_connector_unregister(drm_connector); | |
529 | err_connector: | |
384764c3 | 530 | drm_bridge_remove(bridge); |
f32c4c50 BG |
531 | drm_connector_cleanup(drm_connector); |
532 | return -EINVAL; | |
533 | } | |
534 | ||
535 | static void sti_dvo_unbind(struct device *dev, | |
536 | struct device *master, void *data) | |
537 | { | |
384764c3 | 538 | struct sti_dvo *dvo = dev_get_drvdata(dev); |
755ce376 VA |
539 | struct drm_device *drm_dev = data; |
540 | ||
541 | dvo_debugfs_exit(dvo, drm_dev->primary); | |
384764c3 DA |
542 | |
543 | drm_bridge_remove(dvo->bridge); | |
f32c4c50 BG |
544 | } |
545 | ||
546 | static const struct component_ops sti_dvo_ops = { | |
547 | .bind = sti_dvo_bind, | |
548 | .unbind = sti_dvo_unbind, | |
549 | }; | |
550 | ||
551 | static int sti_dvo_probe(struct platform_device *pdev) | |
552 | { | |
553 | struct device *dev = &pdev->dev; | |
554 | struct sti_dvo *dvo; | |
555 | struct resource *res; | |
556 | struct device_node *np = dev->of_node; | |
557 | ||
558 | DRM_INFO("%s\n", __func__); | |
559 | ||
560 | dvo = devm_kzalloc(dev, sizeof(*dvo), GFP_KERNEL); | |
561 | if (!dvo) { | |
562 | DRM_ERROR("Failed to allocate memory for DVO\n"); | |
563 | return -ENOMEM; | |
564 | } | |
565 | ||
566 | dvo->dev = pdev->dev; | |
567 | ||
568 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvo-reg"); | |
569 | if (!res) { | |
570 | DRM_ERROR("Invalid dvo resource\n"); | |
571 | return -ENOMEM; | |
572 | } | |
573 | dvo->regs = devm_ioremap_nocache(dev, res->start, | |
574 | resource_size(res)); | |
d3c8a0b2 WY |
575 | if (!dvo->regs) |
576 | return -ENOMEM; | |
f32c4c50 BG |
577 | |
578 | dvo->clk_pix = devm_clk_get(dev, "dvo_pix"); | |
579 | if (IS_ERR(dvo->clk_pix)) { | |
580 | DRM_ERROR("Cannot get dvo_pix clock\n"); | |
581 | return PTR_ERR(dvo->clk_pix); | |
582 | } | |
583 | ||
584 | dvo->clk = devm_clk_get(dev, "dvo"); | |
585 | if (IS_ERR(dvo->clk)) { | |
586 | DRM_ERROR("Cannot get dvo clock\n"); | |
587 | return PTR_ERR(dvo->clk); | |
588 | } | |
589 | ||
590 | dvo->clk_main_parent = devm_clk_get(dev, "main_parent"); | |
591 | if (IS_ERR(dvo->clk_main_parent)) { | |
592 | DRM_DEBUG_DRIVER("Cannot get main_parent clock\n"); | |
593 | dvo->clk_main_parent = NULL; | |
594 | } | |
595 | ||
596 | dvo->clk_aux_parent = devm_clk_get(dev, "aux_parent"); | |
597 | if (IS_ERR(dvo->clk_aux_parent)) { | |
598 | DRM_DEBUG_DRIVER("Cannot get aux_parent clock\n"); | |
599 | dvo->clk_aux_parent = NULL; | |
600 | } | |
601 | ||
602 | dvo->panel_node = of_parse_phandle(np, "sti,panel", 0); | |
603 | if (!dvo->panel_node) | |
604 | DRM_ERROR("No panel associated to the dvo output\n"); | |
605 | ||
606 | platform_set_drvdata(pdev, dvo); | |
607 | ||
608 | return component_add(&pdev->dev, &sti_dvo_ops); | |
609 | } | |
610 | ||
611 | static int sti_dvo_remove(struct platform_device *pdev) | |
612 | { | |
613 | component_del(&pdev->dev, &sti_dvo_ops); | |
614 | return 0; | |
615 | } | |
616 | ||
617 | static struct of_device_id dvo_of_match[] = { | |
618 | { .compatible = "st,stih407-dvo", }, | |
619 | { /* end node */ } | |
620 | }; | |
621 | MODULE_DEVICE_TABLE(of, dvo_of_match); | |
622 | ||
623 | struct platform_driver sti_dvo_driver = { | |
624 | .driver = { | |
625 | .name = "sti-dvo", | |
626 | .owner = THIS_MODULE, | |
627 | .of_match_table = dvo_of_match, | |
628 | }, | |
629 | .probe = sti_dvo_probe, | |
630 | .remove = sti_dvo_remove, | |
631 | }; | |
632 | ||
f32c4c50 BG |
633 | MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); |
634 | MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); | |
635 | MODULE_LICENSE("GPL"); |