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5402626c BG |
1 | /* |
2 | * Copyright (C) STMicroelectronics SA 2014 | |
3 | * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics. | |
4 | * License terms: GNU General Public License (GPL), version 2 | |
5 | */ | |
6 | ||
7 | #ifndef _STI_HDMI_H_ | |
8 | #define _STI_HDMI_H_ | |
9 | ||
5671cefb | 10 | #include <linux/hdmi.h> |
5402626c BG |
11 | #include <linux/platform_device.h> |
12 | ||
13 | #include <drm/drmP.h> | |
14 | ||
15 | #define HDMI_STA 0x0010 | |
16 | #define HDMI_STA_DLL_LCK BIT(5) | |
7ea6e6e4 | 17 | #define HDMI_STA_HOT_PLUG BIT(4) |
76569207 | 18 | |
5402626c BG |
19 | struct sti_hdmi; |
20 | ||
21 | struct hdmi_phy_ops { | |
22 | bool (*start)(struct sti_hdmi *hdmi); | |
23 | void (*stop)(struct sti_hdmi *hdmi); | |
24 | }; | |
25 | ||
2c348e50 AP |
26 | struct hdmi_audio_params { |
27 | bool enabled; | |
28 | unsigned int sample_width; | |
29 | unsigned int sample_rate; | |
30 | struct hdmi_audio_infoframe cea; | |
31 | }; | |
32 | ||
ffc4a6a1 VA |
33 | /* values for the framing mode property */ |
34 | enum sti_hdmi_modes { | |
35 | HDMI_MODE_HDMI, | |
36 | HDMI_MODE_DVI, | |
37 | }; | |
38 | ||
39 | static const struct drm_prop_enum_list hdmi_mode_names[] = { | |
40 | { HDMI_MODE_HDMI, "hdmi" }, | |
41 | { HDMI_MODE_DVI, "dvi" }, | |
42 | }; | |
43 | ||
44 | #define DEFAULT_HDMI_MODE HDMI_MODE_HDMI | |
45 | ||
5671cefb VA |
46 | static const struct drm_prop_enum_list colorspace_mode_names[] = { |
47 | { HDMI_COLORSPACE_RGB, "rgb" }, | |
48 | { HDMI_COLORSPACE_YUV422, "yuv422" }, | |
49 | { HDMI_COLORSPACE_YUV444, "yuv444" }, | |
50 | }; | |
51 | ||
52 | #define DEFAULT_COLORSPACE_MODE HDMI_COLORSPACE_RGB | |
53 | ||
5402626c BG |
54 | /** |
55 | * STI hdmi structure | |
56 | * | |
57 | * @dev: driver device | |
58 | * @drm_dev: pointer to drm device | |
59 | * @mode: current display mode selected | |
60 | * @regs: hdmi register | |
61 | * @syscfg: syscfg register for pll rejection configuration | |
62 | * @clk_pix: hdmi pixel clock | |
63 | * @clk_tmds: hdmi tmds clock | |
64 | * @clk_phy: hdmi phy clock | |
65 | * @clk_audio: hdmi audio clock | |
66 | * @irq: hdmi interrupt number | |
67 | * @irq_status: interrupt status register | |
68 | * @phy_ops: phy start/stop operations | |
69 | * @enabled: true if hdmi is enabled else false | |
5402626c BG |
70 | * @hpd: hot plug detect status |
71 | * @wait_event: wait event | |
72 | * @event_received: wait event status | |
73 | * @reset: reset control of the hdmi phy | |
5671cefb VA |
74 | * @ddc_adapt: i2c ddc adapter |
75 | * @colorspace: current colorspace selected | |
ffc4a6a1 | 76 | * @hdmi_mode: select framing for HDMI or DVI |
2c348e50 AP |
77 | * @audio_pdev: ASoC hdmi-codec platform device |
78 | * @audio: hdmi audio parameters. | |
79 | * @drm_connector: hdmi connector | |
5402626c BG |
80 | */ |
81 | struct sti_hdmi { | |
82 | struct device dev; | |
83 | struct drm_device *drm_dev; | |
84 | struct drm_display_mode mode; | |
85 | void __iomem *regs; | |
86 | void __iomem *syscfg; | |
87 | struct clk *clk_pix; | |
88 | struct clk *clk_tmds; | |
89 | struct clk *clk_phy; | |
90 | struct clk *clk_audio; | |
91 | int irq; | |
92 | u32 irq_status; | |
93 | struct hdmi_phy_ops *phy_ops; | |
94 | bool enabled; | |
5402626c BG |
95 | bool hpd; |
96 | wait_queue_head_t wait_event; | |
97 | bool event_received; | |
98 | struct reset_control *reset; | |
41a14623 | 99 | struct i2c_adapter *ddc_adapt; |
5671cefb | 100 | enum hdmi_colorspace colorspace; |
ffc4a6a1 | 101 | enum sti_hdmi_modes hdmi_mode; |
2c348e50 AP |
102 | struct platform_device *audio_pdev; |
103 | struct hdmi_audio_params audio; | |
104 | struct drm_connector *drm_connector; | |
5402626c BG |
105 | }; |
106 | ||
107 | u32 hdmi_read(struct sti_hdmi *hdmi, int offset); | |
108 | void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset); | |
109 | ||
110 | /** | |
111 | * hdmi phy config structure | |
112 | * | |
113 | * A pointer to an array of these structures is passed to a TMDS (HDMI) output | |
114 | * via the control interface to provide board and SoC specific | |
115 | * configurations of the HDMI PHY. Each entry in the array specifies a hardware | |
116 | * specific configuration for a given TMDS clock frequency range. | |
117 | * | |
118 | * @min_tmds_freq: Lower bound of TMDS clock frequency this entry applies to | |
119 | * @max_tmds_freq: Upper bound of TMDS clock frequency this entry applies to | |
120 | * @config: SoC specific register configuration | |
121 | */ | |
122 | struct hdmi_phy_config { | |
123 | u32 min_tmds_freq; | |
124 | u32 max_tmds_freq; | |
125 | u32 config[4]; | |
126 | }; | |
127 | ||
128 | #endif |