Commit | Line | Data |
---|---|---|
d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
d43f81cb | 3 | * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved. |
d8f4a9ed TR |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
4231c6b0 TB |
10 | #ifndef HOST1X_DRM_H |
11 | #define HOST1X_DRM_H 1 | |
d8f4a9ed | 12 | |
e1e90644 TR |
13 | #include <uapi/drm/tegra_drm.h> |
14 | #include <linux/host1x.h> | |
fb36d0ee | 15 | #include <linux/of_gpio.h> |
e1e90644 | 16 | |
d8f4a9ed TR |
17 | #include <drm/drmP.h> |
18 | #include <drm/drm_crtc_helper.h> | |
19 | #include <drm/drm_edid.h> | |
20 | #include <drm/drm_fb_helper.h> | |
d8f4a9ed TR |
21 | #include <drm/drm_fixed.h> |
22 | ||
c134f019 TR |
23 | #include "gem.h" |
24 | ||
ca48080a SW |
25 | struct reset_control; |
26 | ||
de2ba664 AM |
27 | struct tegra_fb { |
28 | struct drm_framebuffer base; | |
29 | struct tegra_bo **planes; | |
30 | unsigned int num_planes; | |
31 | }; | |
32 | ||
b110ef37 | 33 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
de2ba664 AM |
34 | struct tegra_fbdev { |
35 | struct drm_fb_helper base; | |
36 | struct tegra_fb *fb; | |
37 | }; | |
60c2f709 | 38 | #endif |
de2ba664 | 39 | |
386a2a71 | 40 | struct tegra_drm { |
d8f4a9ed | 41 | struct drm_device *drm; |
d8f4a9ed | 42 | |
df06b759 TR |
43 | struct iommu_domain *domain; |
44 | struct drm_mm mm; | |
45 | ||
d8f4a9ed TR |
46 | struct mutex clients_lock; |
47 | struct list_head clients; | |
48 | ||
b110ef37 | 49 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
de2ba664 | 50 | struct tegra_fbdev *fbdev; |
60c2f709 | 51 | #endif |
d1f3e1e0 TR |
52 | |
53 | unsigned int pitch_align; | |
1503ca47 TR |
54 | |
55 | struct { | |
56 | struct drm_atomic_state *state; | |
57 | struct work_struct work; | |
58 | struct mutex lock; | |
59 | } commit; | |
986c58d1 TR |
60 | |
61 | struct drm_atomic_state *state; | |
d8f4a9ed TR |
62 | }; |
63 | ||
53fa7f72 | 64 | struct tegra_drm_client; |
d8f4a9ed | 65 | |
c88c3630 | 66 | struct tegra_drm_context { |
53fa7f72 | 67 | struct tegra_drm_client *client; |
d43f81cb TB |
68 | struct host1x_channel *channel; |
69 | struct list_head list; | |
70 | }; | |
71 | ||
53fa7f72 TR |
72 | struct tegra_drm_client_ops { |
73 | int (*open_channel)(struct tegra_drm_client *client, | |
c88c3630 TR |
74 | struct tegra_drm_context *context); |
75 | void (*close_channel)(struct tegra_drm_context *context); | |
c40f0f1a | 76 | int (*is_addr_reg)(struct device *dev, u32 class, u32 offset); |
c88c3630 | 77 | int (*submit)(struct tegra_drm_context *context, |
d43f81cb TB |
78 | struct drm_tegra_submit *args, struct drm_device *drm, |
79 | struct drm_file *file); | |
80 | }; | |
81 | ||
c40f0f1a TR |
82 | int tegra_drm_submit(struct tegra_drm_context *context, |
83 | struct drm_tegra_submit *args, struct drm_device *drm, | |
84 | struct drm_file *file); | |
85 | ||
53fa7f72 TR |
86 | struct tegra_drm_client { |
87 | struct host1x_client base; | |
776dc384 | 88 | struct list_head list; |
d43f81cb | 89 | |
53fa7f72 | 90 | const struct tegra_drm_client_ops *ops; |
d8f4a9ed TR |
91 | }; |
92 | ||
53fa7f72 | 93 | static inline struct tegra_drm_client * |
776dc384 | 94 | host1x_to_drm_client(struct host1x_client *client) |
53fa7f72 TR |
95 | { |
96 | return container_of(client, struct tegra_drm_client, base); | |
97 | } | |
98 | ||
688c59af TR |
99 | int tegra_drm_register_client(struct tegra_drm *tegra, |
100 | struct tegra_drm_client *client); | |
101 | int tegra_drm_unregister_client(struct tegra_drm *tegra, | |
102 | struct tegra_drm_client *client); | |
776dc384 | 103 | |
688c59af TR |
104 | int tegra_drm_init(struct tegra_drm *tegra, struct drm_device *drm); |
105 | int tegra_drm_exit(struct tegra_drm *tegra); | |
d8f4a9ed | 106 | |
8620fc62 | 107 | struct tegra_dc_soc_info; |
d8f4a9ed TR |
108 | struct tegra_output; |
109 | ||
791ddb1e TR |
110 | struct tegra_dc_stats { |
111 | unsigned long frames; | |
112 | unsigned long vblank; | |
113 | unsigned long underflow; | |
114 | unsigned long overflow; | |
115 | }; | |
116 | ||
d8f4a9ed | 117 | struct tegra_dc { |
776dc384 | 118 | struct host1x_client client; |
42e9ce05 | 119 | struct host1x_syncpt *syncpt; |
d8f4a9ed | 120 | struct device *dev; |
d18d3033 | 121 | spinlock_t lock; |
d8f4a9ed TR |
122 | |
123 | struct drm_crtc base; | |
9c012700 | 124 | int powergate; |
d8f4a9ed TR |
125 | int pipe; |
126 | ||
127 | struct clk *clk; | |
ca48080a | 128 | struct reset_control *rst; |
d8f4a9ed TR |
129 | void __iomem *regs; |
130 | int irq; | |
131 | ||
132 | struct tegra_output *rgb; | |
133 | ||
791ddb1e | 134 | struct tegra_dc_stats stats; |
d8f4a9ed TR |
135 | struct list_head list; |
136 | ||
137 | struct drm_info_list *debugfs_files; | |
138 | struct drm_minor *minor; | |
139 | struct dentry *debugfs; | |
3c03c46a TR |
140 | |
141 | /* page-flip handling */ | |
142 | struct drm_pending_vblank_event *event; | |
8620fc62 TR |
143 | |
144 | const struct tegra_dc_soc_info *soc; | |
df06b759 TR |
145 | |
146 | struct iommu_domain *domain; | |
d8f4a9ed TR |
147 | }; |
148 | ||
53fa7f72 | 149 | static inline struct tegra_dc * |
776dc384 | 150 | host1x_client_to_dc(struct host1x_client *client) |
d8f4a9ed TR |
151 | { |
152 | return container_of(client, struct tegra_dc, client); | |
153 | } | |
154 | ||
155 | static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) | |
156 | { | |
37826519 | 157 | return crtc ? container_of(crtc, struct tegra_dc, base) : NULL; |
d8f4a9ed TR |
158 | } |
159 | ||
03a60569 TR |
160 | static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, |
161 | unsigned long offset) | |
d8f4a9ed | 162 | { |
03a60569 | 163 | writel(value, dc->regs + (offset << 2)); |
d8f4a9ed TR |
164 | } |
165 | ||
03a60569 | 166 | static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned long offset) |
d8f4a9ed | 167 | { |
03a60569 | 168 | return readl(dc->regs + (offset << 2)); |
d8f4a9ed TR |
169 | } |
170 | ||
f34bc787 TR |
171 | struct tegra_dc_window { |
172 | struct { | |
173 | unsigned int x; | |
174 | unsigned int y; | |
175 | unsigned int w; | |
176 | unsigned int h; | |
177 | } src; | |
178 | struct { | |
179 | unsigned int x; | |
180 | unsigned int y; | |
181 | unsigned int w; | |
182 | unsigned int h; | |
183 | } dst; | |
184 | unsigned int bits_per_pixel; | |
f34bc787 TR |
185 | unsigned int stride[2]; |
186 | unsigned long base[3]; | |
db7fbdfd | 187 | bool bottom_up; |
c134f019 TR |
188 | |
189 | struct tegra_bo_tiling tiling; | |
8f604f8c TR |
190 | u32 format; |
191 | u32 swap; | |
f34bc787 TR |
192 | }; |
193 | ||
194 | /* from dc.c */ | |
42e9ce05 | 195 | u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc); |
688c59af TR |
196 | void tegra_dc_enable_vblank(struct tegra_dc *dc); |
197 | void tegra_dc_disable_vblank(struct tegra_dc *dc); | |
62b9e063 | 198 | void tegra_dc_commit(struct tegra_dc *dc); |
ca915b10 TR |
199 | int tegra_dc_state_setup_clock(struct tegra_dc *dc, |
200 | struct drm_crtc_state *crtc_state, | |
201 | struct clk *clk, unsigned long pclk, | |
202 | unsigned int div); | |
f34bc787 | 203 | |
d8f4a9ed TR |
204 | struct tegra_output { |
205 | struct device_node *of_node; | |
206 | struct device *dev; | |
207 | ||
9be7d864 | 208 | struct drm_panel *panel; |
d8f4a9ed TR |
209 | struct i2c_adapter *ddc; |
210 | const struct edid *edid; | |
211 | unsigned int hpd_irq; | |
212 | int hpd_gpio; | |
fb36d0ee | 213 | enum of_gpio_flags hpd_gpio_flags; |
d8f4a9ed TR |
214 | |
215 | struct drm_encoder encoder; | |
216 | struct drm_connector connector; | |
217 | }; | |
218 | ||
219 | static inline struct tegra_output *encoder_to_output(struct drm_encoder *e) | |
220 | { | |
221 | return container_of(e, struct tegra_output, encoder); | |
222 | } | |
223 | ||
224 | static inline struct tegra_output *connector_to_output(struct drm_connector *c) | |
225 | { | |
226 | return container_of(c, struct tegra_output, connector); | |
227 | } | |
228 | ||
d8f4a9ed | 229 | /* from rgb.c */ |
688c59af TR |
230 | int tegra_dc_rgb_probe(struct tegra_dc *dc); |
231 | int tegra_dc_rgb_remove(struct tegra_dc *dc); | |
232 | int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); | |
233 | int tegra_dc_rgb_exit(struct tegra_dc *dc); | |
d8f4a9ed TR |
234 | |
235 | /* from output.c */ | |
688c59af | 236 | int tegra_output_probe(struct tegra_output *output); |
328ec69e | 237 | void tegra_output_remove(struct tegra_output *output); |
688c59af | 238 | int tegra_output_init(struct drm_device *drm, struct tegra_output *output); |
328ec69e | 239 | void tegra_output_exit(struct tegra_output *output); |
d8f4a9ed | 240 | |
132085d8 TR |
241 | int tegra_output_connector_get_modes(struct drm_connector *connector); |
242 | struct drm_encoder * | |
243 | tegra_output_connector_best_encoder(struct drm_connector *connector); | |
244 | enum drm_connector_status | |
245 | tegra_output_connector_detect(struct drm_connector *connector, bool force); | |
246 | void tegra_output_connector_destroy(struct drm_connector *connector); | |
247 | ||
248 | void tegra_output_encoder_destroy(struct drm_encoder *encoder); | |
249 | ||
6b6b6042 | 250 | /* from dpaux.c */ |
6b6b6042 | 251 | struct drm_dp_link; |
6b6b6042 | 252 | |
9542c237 TR |
253 | struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np); |
254 | enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux); | |
255 | int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output); | |
256 | int drm_dp_aux_detach(struct drm_dp_aux *aux); | |
257 | int drm_dp_aux_enable(struct drm_dp_aux *aux); | |
258 | int drm_dp_aux_disable(struct drm_dp_aux *aux); | |
259 | int drm_dp_aux_prepare(struct drm_dp_aux *aux, u8 encoding); | |
260 | int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link, | |
261 | u8 pattern); | |
6b6b6042 | 262 | |
d8f4a9ed | 263 | /* from fb.c */ |
de2ba664 AM |
264 | struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer, |
265 | unsigned int index); | |
db7fbdfd | 266 | bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer); |
c134f019 TR |
267 | int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, |
268 | struct tegra_bo_tiling *tiling); | |
f9914214 TR |
269 | struct drm_framebuffer *tegra_fb_create(struct drm_device *drm, |
270 | struct drm_file *file, | |
1eb83451 | 271 | const struct drm_mode_fb_cmd2 *cmd); |
e2215321 | 272 | int tegra_drm_fb_prepare(struct drm_device *drm); |
1d1e6fe9 | 273 | void tegra_drm_fb_free(struct drm_device *drm); |
688c59af TR |
274 | int tegra_drm_fb_init(struct drm_device *drm); |
275 | void tegra_drm_fb_exit(struct drm_device *drm); | |
986c58d1 TR |
276 | void tegra_drm_fb_suspend(struct drm_device *drm); |
277 | void tegra_drm_fb_resume(struct drm_device *drm); | |
b110ef37 | 278 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
688c59af | 279 | void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev); |
f9914214 | 280 | void tegra_fb_output_poll_changed(struct drm_device *drm); |
60c2f709 | 281 | #endif |
d8f4a9ed | 282 | |
776dc384 TR |
283 | extern struct platform_driver tegra_dc_driver; |
284 | extern struct platform_driver tegra_hdmi_driver; | |
473112e4 | 285 | extern struct platform_driver tegra_dsi_driver; |
6b6b6042 | 286 | extern struct platform_driver tegra_dpaux_driver; |
473112e4 | 287 | extern struct platform_driver tegra_sor_driver; |
776dc384 | 288 | extern struct platform_driver tegra_gr2d_driver; |
5f60ed0d | 289 | extern struct platform_driver tegra_gr3d_driver; |
d8f4a9ed | 290 | |
4231c6b0 | 291 | #endif /* HOST1X_DRM_H */ |