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6b6b6042 TR |
1 | /* |
2 | * Copyright (C) 2013 NVIDIA Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <linux/clk.h> | |
b299221c | 10 | #include <linux/clk-provider.h> |
a82752e1 | 11 | #include <linux/debugfs.h> |
6fad8f66 | 12 | #include <linux/gpio.h> |
6b6b6042 | 13 | #include <linux/io.h> |
459cc2c6 | 14 | #include <linux/of_device.h> |
6b6b6042 | 15 | #include <linux/platform_device.h> |
aaff8bd2 | 16 | #include <linux/pm_runtime.h> |
459cc2c6 | 17 | #include <linux/regulator/consumer.h> |
6b6b6042 | 18 | #include <linux/reset.h> |
306a7f91 | 19 | |
7232398a | 20 | #include <soc/tegra/pmc.h> |
6b6b6042 | 21 | |
4aa3df71 | 22 | #include <drm/drm_atomic_helper.h> |
6b6b6042 | 23 | #include <drm/drm_dp_helper.h> |
6fad8f66 | 24 | #include <drm/drm_panel.h> |
6b6b6042 TR |
25 | |
26 | #include "dc.h" | |
27 | #include "drm.h" | |
28 | #include "sor.h" | |
29 | ||
459cc2c6 TR |
30 | #define SOR_REKEY 0x38 |
31 | ||
32 | struct tegra_sor_hdmi_settings { | |
33 | unsigned long frequency; | |
34 | ||
35 | u8 vcocap; | |
36 | u8 ichpmp; | |
37 | u8 loadadj; | |
38 | u8 termadj; | |
39 | u8 tx_pu; | |
40 | u8 bg_vref; | |
41 | ||
42 | u8 drive_current[4]; | |
43 | u8 preemphasis[4]; | |
44 | }; | |
45 | ||
46 | #if 1 | |
47 | static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { | |
48 | { | |
49 | .frequency = 54000000, | |
50 | .vcocap = 0x0, | |
51 | .ichpmp = 0x1, | |
52 | .loadadj = 0x3, | |
53 | .termadj = 0x9, | |
54 | .tx_pu = 0x10, | |
55 | .bg_vref = 0x8, | |
56 | .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, | |
57 | .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, | |
58 | }, { | |
59 | .frequency = 75000000, | |
60 | .vcocap = 0x3, | |
61 | .ichpmp = 0x1, | |
62 | .loadadj = 0x3, | |
63 | .termadj = 0x9, | |
64 | .tx_pu = 0x40, | |
65 | .bg_vref = 0x8, | |
66 | .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, | |
67 | .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, | |
68 | }, { | |
69 | .frequency = 150000000, | |
70 | .vcocap = 0x3, | |
71 | .ichpmp = 0x1, | |
72 | .loadadj = 0x3, | |
73 | .termadj = 0x9, | |
74 | .tx_pu = 0x66, | |
75 | .bg_vref = 0x8, | |
76 | .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, | |
77 | .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, | |
78 | }, { | |
79 | .frequency = 300000000, | |
80 | .vcocap = 0x3, | |
81 | .ichpmp = 0x1, | |
82 | .loadadj = 0x3, | |
83 | .termadj = 0x9, | |
84 | .tx_pu = 0x66, | |
85 | .bg_vref = 0xa, | |
86 | .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, | |
87 | .preemphasis = { 0x00, 0x17, 0x17, 0x17 }, | |
88 | }, { | |
89 | .frequency = 600000000, | |
90 | .vcocap = 0x3, | |
91 | .ichpmp = 0x1, | |
92 | .loadadj = 0x3, | |
93 | .termadj = 0x9, | |
94 | .tx_pu = 0x66, | |
95 | .bg_vref = 0x8, | |
96 | .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, | |
97 | .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, | |
98 | }, | |
99 | }; | |
100 | #else | |
101 | static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { | |
102 | { | |
103 | .frequency = 75000000, | |
104 | .vcocap = 0x3, | |
105 | .ichpmp = 0x1, | |
106 | .loadadj = 0x3, | |
107 | .termadj = 0x9, | |
108 | .tx_pu = 0x40, | |
109 | .bg_vref = 0x8, | |
110 | .drive_current = { 0x29, 0x29, 0x29, 0x29 }, | |
111 | .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, | |
112 | }, { | |
113 | .frequency = 150000000, | |
114 | .vcocap = 0x3, | |
115 | .ichpmp = 0x1, | |
116 | .loadadj = 0x3, | |
117 | .termadj = 0x9, | |
118 | .tx_pu = 0x66, | |
119 | .bg_vref = 0x8, | |
120 | .drive_current = { 0x30, 0x37, 0x37, 0x37 }, | |
121 | .preemphasis = { 0x01, 0x02, 0x02, 0x02 }, | |
122 | }, { | |
123 | .frequency = 300000000, | |
124 | .vcocap = 0x3, | |
125 | .ichpmp = 0x6, | |
126 | .loadadj = 0x3, | |
127 | .termadj = 0x9, | |
128 | .tx_pu = 0x66, | |
129 | .bg_vref = 0xf, | |
130 | .drive_current = { 0x30, 0x37, 0x37, 0x37 }, | |
131 | .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e }, | |
132 | }, { | |
133 | .frequency = 600000000, | |
134 | .vcocap = 0x3, | |
135 | .ichpmp = 0xa, | |
136 | .loadadj = 0x3, | |
137 | .termadj = 0xb, | |
138 | .tx_pu = 0x66, | |
139 | .bg_vref = 0xe, | |
140 | .drive_current = { 0x35, 0x3e, 0x3e, 0x3e }, | |
141 | .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f }, | |
142 | }, | |
143 | }; | |
144 | #endif | |
145 | ||
146 | struct tegra_sor_soc { | |
147 | bool supports_edp; | |
148 | bool supports_lvds; | |
149 | bool supports_hdmi; | |
150 | bool supports_dp; | |
151 | ||
152 | const struct tegra_sor_hdmi_settings *settings; | |
153 | unsigned int num_settings; | |
30b49435 TR |
154 | |
155 | const u8 *xbar_cfg; | |
459cc2c6 TR |
156 | }; |
157 | ||
158 | struct tegra_sor; | |
159 | ||
160 | struct tegra_sor_ops { | |
161 | const char *name; | |
162 | int (*probe)(struct tegra_sor *sor); | |
163 | int (*remove)(struct tegra_sor *sor); | |
164 | }; | |
165 | ||
6b6b6042 TR |
166 | struct tegra_sor { |
167 | struct host1x_client client; | |
168 | struct tegra_output output; | |
169 | struct device *dev; | |
170 | ||
459cc2c6 | 171 | const struct tegra_sor_soc *soc; |
6b6b6042 TR |
172 | void __iomem *regs; |
173 | ||
174 | struct reset_control *rst; | |
175 | struct clk *clk_parent; | |
b299221c | 176 | struct clk *clk_brick; |
6b6b6042 | 177 | struct clk *clk_safe; |
618dee39 | 178 | struct clk *clk_src; |
6b6b6042 TR |
179 | struct clk *clk_dp; |
180 | struct clk *clk; | |
181 | ||
9542c237 | 182 | struct drm_dp_aux *aux; |
6b6b6042 | 183 | |
dab16336 TR |
184 | struct drm_info_list *debugfs_files; |
185 | struct drm_minor *minor; | |
a82752e1 | 186 | struct dentry *debugfs; |
459cc2c6 TR |
187 | |
188 | const struct tegra_sor_ops *ops; | |
189 | ||
190 | /* for HDMI 2.0 */ | |
191 | struct tegra_sor_hdmi_settings *settings; | |
192 | unsigned int num_settings; | |
193 | ||
194 | struct regulator *avdd_io_supply; | |
195 | struct regulator *vdd_pll_supply; | |
196 | struct regulator *hdmi_supply; | |
6b6b6042 TR |
197 | }; |
198 | ||
c31efa7a TR |
199 | struct tegra_sor_state { |
200 | struct drm_connector_state base; | |
201 | ||
202 | unsigned int bpc; | |
203 | }; | |
204 | ||
205 | static inline struct tegra_sor_state * | |
206 | to_sor_state(struct drm_connector_state *state) | |
207 | { | |
208 | return container_of(state, struct tegra_sor_state, base); | |
209 | } | |
210 | ||
34fa183b TR |
211 | struct tegra_sor_config { |
212 | u32 bits_per_pixel; | |
213 | ||
214 | u32 active_polarity; | |
215 | u32 active_count; | |
216 | u32 tu_size; | |
217 | u32 active_frac; | |
218 | u32 watermark; | |
7890b576 TR |
219 | |
220 | u32 hblank_symbols; | |
221 | u32 vblank_symbols; | |
34fa183b TR |
222 | }; |
223 | ||
6b6b6042 TR |
224 | static inline struct tegra_sor * |
225 | host1x_client_to_sor(struct host1x_client *client) | |
226 | { | |
227 | return container_of(client, struct tegra_sor, client); | |
228 | } | |
229 | ||
230 | static inline struct tegra_sor *to_sor(struct tegra_output *output) | |
231 | { | |
232 | return container_of(output, struct tegra_sor, output); | |
233 | } | |
234 | ||
28fe2076 | 235 | static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset) |
6b6b6042 TR |
236 | { |
237 | return readl(sor->regs + (offset << 2)); | |
238 | } | |
239 | ||
28fe2076 | 240 | static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, |
6b6b6042 TR |
241 | unsigned long offset) |
242 | { | |
243 | writel(value, sor->regs + (offset << 2)); | |
244 | } | |
245 | ||
25bb2cec TR |
246 | static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) |
247 | { | |
248 | int err; | |
249 | ||
250 | clk_disable_unprepare(sor->clk); | |
251 | ||
252 | err = clk_set_parent(sor->clk, parent); | |
253 | if (err < 0) | |
254 | return err; | |
255 | ||
256 | err = clk_prepare_enable(sor->clk); | |
257 | if (err < 0) | |
258 | return err; | |
259 | ||
260 | return 0; | |
261 | } | |
262 | ||
b299221c TR |
263 | struct tegra_clk_sor_brick { |
264 | struct clk_hw hw; | |
265 | struct tegra_sor *sor; | |
266 | }; | |
267 | ||
268 | static inline struct tegra_clk_sor_brick *to_brick(struct clk_hw *hw) | |
269 | { | |
270 | return container_of(hw, struct tegra_clk_sor_brick, hw); | |
271 | } | |
272 | ||
273 | static const char * const tegra_clk_sor_brick_parents[] = { | |
274 | "pll_d2_out0", "pll_dp" | |
275 | }; | |
276 | ||
277 | static int tegra_clk_sor_brick_set_parent(struct clk_hw *hw, u8 index) | |
278 | { | |
279 | struct tegra_clk_sor_brick *brick = to_brick(hw); | |
280 | struct tegra_sor *sor = brick->sor; | |
281 | u32 value; | |
282 | ||
283 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); | |
284 | value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; | |
285 | ||
286 | switch (index) { | |
287 | case 0: | |
288 | value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; | |
289 | break; | |
290 | ||
291 | case 1: | |
292 | value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; | |
293 | break; | |
294 | } | |
295 | ||
296 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); | |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
301 | static u8 tegra_clk_sor_brick_get_parent(struct clk_hw *hw) | |
302 | { | |
303 | struct tegra_clk_sor_brick *brick = to_brick(hw); | |
304 | struct tegra_sor *sor = brick->sor; | |
305 | u8 parent = U8_MAX; | |
306 | u32 value; | |
307 | ||
308 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); | |
309 | ||
310 | switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) { | |
311 | case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK: | |
312 | case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK: | |
313 | parent = 0; | |
314 | break; | |
315 | ||
316 | case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK: | |
317 | case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK: | |
318 | parent = 1; | |
319 | break; | |
320 | } | |
321 | ||
322 | return parent; | |
323 | } | |
324 | ||
325 | static const struct clk_ops tegra_clk_sor_brick_ops = { | |
326 | .set_parent = tegra_clk_sor_brick_set_parent, | |
327 | .get_parent = tegra_clk_sor_brick_get_parent, | |
328 | }; | |
329 | ||
330 | static struct clk *tegra_clk_sor_brick_register(struct tegra_sor *sor, | |
331 | const char *name) | |
332 | { | |
333 | struct tegra_clk_sor_brick *brick; | |
334 | struct clk_init_data init; | |
335 | struct clk *clk; | |
336 | ||
337 | brick = devm_kzalloc(sor->dev, sizeof(*brick), GFP_KERNEL); | |
338 | if (!brick) | |
339 | return ERR_PTR(-ENOMEM); | |
340 | ||
341 | brick->sor = sor; | |
342 | ||
343 | init.name = name; | |
344 | init.flags = 0; | |
345 | init.parent_names = tegra_clk_sor_brick_parents; | |
346 | init.num_parents = ARRAY_SIZE(tegra_clk_sor_brick_parents); | |
347 | init.ops = &tegra_clk_sor_brick_ops; | |
348 | ||
349 | brick->hw.init = &init; | |
350 | ||
351 | clk = devm_clk_register(sor->dev, &brick->hw); | |
352 | if (IS_ERR(clk)) | |
353 | kfree(brick); | |
354 | ||
355 | return clk; | |
356 | } | |
357 | ||
6b6b6042 TR |
358 | static int tegra_sor_dp_train_fast(struct tegra_sor *sor, |
359 | struct drm_dp_link *link) | |
360 | { | |
6b6b6042 TR |
361 | unsigned int i; |
362 | u8 pattern; | |
28fe2076 | 363 | u32 value; |
6b6b6042 TR |
364 | int err; |
365 | ||
366 | /* setup lane parameters */ | |
367 | value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | | |
368 | SOR_LANE_DRIVE_CURRENT_LANE2(0x40) | | |
369 | SOR_LANE_DRIVE_CURRENT_LANE1(0x40) | | |
370 | SOR_LANE_DRIVE_CURRENT_LANE0(0x40); | |
a9a9e4fd | 371 | tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); |
6b6b6042 TR |
372 | |
373 | value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | | |
374 | SOR_LANE_PREEMPHASIS_LANE2(0x0f) | | |
375 | SOR_LANE_PREEMPHASIS_LANE1(0x0f) | | |
376 | SOR_LANE_PREEMPHASIS_LANE0(0x0f); | |
a9a9e4fd | 377 | tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); |
6b6b6042 | 378 | |
a9a9e4fd TR |
379 | value = SOR_LANE_POSTCURSOR_LANE3(0x00) | |
380 | SOR_LANE_POSTCURSOR_LANE2(0x00) | | |
381 | SOR_LANE_POSTCURSOR_LANE1(0x00) | | |
382 | SOR_LANE_POSTCURSOR_LANE0(0x00); | |
383 | tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); | |
6b6b6042 TR |
384 | |
385 | /* disable LVDS mode */ | |
386 | tegra_sor_writel(sor, 0, SOR_LVDS); | |
387 | ||
a9a9e4fd | 388 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
6b6b6042 TR |
389 | value |= SOR_DP_PADCTL_TX_PU_ENABLE; |
390 | value &= ~SOR_DP_PADCTL_TX_PU_MASK; | |
391 | value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ | |
a9a9e4fd | 392 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
6b6b6042 | 393 | |
a9a9e4fd | 394 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
6b6b6042 TR |
395 | value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | |
396 | SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0; | |
a9a9e4fd | 397 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
6b6b6042 TR |
398 | |
399 | usleep_range(10, 100); | |
400 | ||
a9a9e4fd | 401 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
6b6b6042 TR |
402 | value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | |
403 | SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); | |
a9a9e4fd | 404 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
6b6b6042 | 405 | |
9542c237 | 406 | err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B); |
6b6b6042 TR |
407 | if (err < 0) |
408 | return err; | |
409 | ||
410 | for (i = 0, value = 0; i < link->num_lanes; i++) { | |
411 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | | |
412 | SOR_DP_TPG_SCRAMBLER_NONE | | |
413 | SOR_DP_TPG_PATTERN_TRAIN1; | |
414 | value = (value << 8) | lane; | |
415 | } | |
416 | ||
417 | tegra_sor_writel(sor, value, SOR_DP_TPG); | |
418 | ||
419 | pattern = DP_TRAINING_PATTERN_1; | |
420 | ||
9542c237 | 421 | err = drm_dp_aux_train(sor->aux, link, pattern); |
6b6b6042 TR |
422 | if (err < 0) |
423 | return err; | |
424 | ||
a9a9e4fd | 425 | value = tegra_sor_readl(sor, SOR_DP_SPARE0); |
6b6b6042 TR |
426 | value |= SOR_DP_SPARE_SEQ_ENABLE; |
427 | value &= ~SOR_DP_SPARE_PANEL_INTERNAL; | |
428 | value |= SOR_DP_SPARE_MACRO_SOR_CLK; | |
a9a9e4fd | 429 | tegra_sor_writel(sor, value, SOR_DP_SPARE0); |
6b6b6042 TR |
430 | |
431 | for (i = 0, value = 0; i < link->num_lanes; i++) { | |
432 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | | |
433 | SOR_DP_TPG_SCRAMBLER_NONE | | |
434 | SOR_DP_TPG_PATTERN_TRAIN2; | |
435 | value = (value << 8) | lane; | |
436 | } | |
437 | ||
438 | tegra_sor_writel(sor, value, SOR_DP_TPG); | |
439 | ||
440 | pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2; | |
441 | ||
9542c237 | 442 | err = drm_dp_aux_train(sor->aux, link, pattern); |
6b6b6042 TR |
443 | if (err < 0) |
444 | return err; | |
445 | ||
446 | for (i = 0, value = 0; i < link->num_lanes; i++) { | |
447 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | | |
448 | SOR_DP_TPG_SCRAMBLER_GALIOS | | |
449 | SOR_DP_TPG_PATTERN_NONE; | |
450 | value = (value << 8) | lane; | |
451 | } | |
452 | ||
453 | tegra_sor_writel(sor, value, SOR_DP_TPG); | |
454 | ||
455 | pattern = DP_TRAINING_PATTERN_DISABLE; | |
456 | ||
9542c237 | 457 | err = drm_dp_aux_train(sor->aux, link, pattern); |
6b6b6042 TR |
458 | if (err < 0) |
459 | return err; | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
459cc2c6 TR |
464 | static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor) |
465 | { | |
466 | u32 mask = 0x08, adj = 0, value; | |
467 | ||
468 | /* enable pad calibration logic */ | |
469 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); | |
470 | value &= ~SOR_DP_PADCTL_PAD_CAL_PD; | |
471 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); | |
472 | ||
473 | value = tegra_sor_readl(sor, SOR_PLL1); | |
474 | value |= SOR_PLL1_TMDS_TERM; | |
475 | tegra_sor_writel(sor, value, SOR_PLL1); | |
476 | ||
477 | while (mask) { | |
478 | adj |= mask; | |
479 | ||
480 | value = tegra_sor_readl(sor, SOR_PLL1); | |
481 | value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; | |
482 | value |= SOR_PLL1_TMDS_TERMADJ(adj); | |
483 | tegra_sor_writel(sor, value, SOR_PLL1); | |
484 | ||
485 | usleep_range(100, 200); | |
486 | ||
487 | value = tegra_sor_readl(sor, SOR_PLL1); | |
488 | if (value & SOR_PLL1_TERM_COMPOUT) | |
489 | adj &= ~mask; | |
490 | ||
491 | mask >>= 1; | |
492 | } | |
493 | ||
494 | value = tegra_sor_readl(sor, SOR_PLL1); | |
495 | value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; | |
496 | value |= SOR_PLL1_TMDS_TERMADJ(adj); | |
497 | tegra_sor_writel(sor, value, SOR_PLL1); | |
498 | ||
499 | /* disable pad calibration logic */ | |
500 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); | |
501 | value |= SOR_DP_PADCTL_PAD_CAL_PD; | |
502 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); | |
503 | } | |
504 | ||
6b6b6042 TR |
505 | static void tegra_sor_super_update(struct tegra_sor *sor) |
506 | { | |
a9a9e4fd TR |
507 | tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); |
508 | tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); | |
509 | tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); | |
6b6b6042 TR |
510 | } |
511 | ||
512 | static void tegra_sor_update(struct tegra_sor *sor) | |
513 | { | |
a9a9e4fd TR |
514 | tegra_sor_writel(sor, 0, SOR_STATE0); |
515 | tegra_sor_writel(sor, 1, SOR_STATE0); | |
516 | tegra_sor_writel(sor, 0, SOR_STATE0); | |
6b6b6042 TR |
517 | } |
518 | ||
519 | static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) | |
520 | { | |
28fe2076 | 521 | u32 value; |
6b6b6042 TR |
522 | |
523 | value = tegra_sor_readl(sor, SOR_PWM_DIV); | |
524 | value &= ~SOR_PWM_DIV_MASK; | |
525 | value |= 0x400; /* period */ | |
526 | tegra_sor_writel(sor, value, SOR_PWM_DIV); | |
527 | ||
528 | value = tegra_sor_readl(sor, SOR_PWM_CTL); | |
529 | value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; | |
530 | value |= 0x400; /* duty cycle */ | |
531 | value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ | |
532 | value |= SOR_PWM_CTL_TRIGGER; | |
533 | tegra_sor_writel(sor, value, SOR_PWM_CTL); | |
534 | ||
535 | timeout = jiffies + msecs_to_jiffies(timeout); | |
536 | ||
537 | while (time_before(jiffies, timeout)) { | |
538 | value = tegra_sor_readl(sor, SOR_PWM_CTL); | |
539 | if ((value & SOR_PWM_CTL_TRIGGER) == 0) | |
540 | return 0; | |
541 | ||
542 | usleep_range(25, 100); | |
543 | } | |
544 | ||
545 | return -ETIMEDOUT; | |
546 | } | |
547 | ||
548 | static int tegra_sor_attach(struct tegra_sor *sor) | |
549 | { | |
550 | unsigned long value, timeout; | |
551 | ||
552 | /* wake up in normal mode */ | |
a9a9e4fd | 553 | value = tegra_sor_readl(sor, SOR_SUPER_STATE1); |
6b6b6042 TR |
554 | value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; |
555 | value |= SOR_SUPER_STATE_MODE_NORMAL; | |
a9a9e4fd | 556 | tegra_sor_writel(sor, value, SOR_SUPER_STATE1); |
6b6b6042 TR |
557 | tegra_sor_super_update(sor); |
558 | ||
559 | /* attach */ | |
a9a9e4fd | 560 | value = tegra_sor_readl(sor, SOR_SUPER_STATE1); |
6b6b6042 | 561 | value |= SOR_SUPER_STATE_ATTACHED; |
a9a9e4fd | 562 | tegra_sor_writel(sor, value, SOR_SUPER_STATE1); |
6b6b6042 TR |
563 | tegra_sor_super_update(sor); |
564 | ||
565 | timeout = jiffies + msecs_to_jiffies(250); | |
566 | ||
567 | while (time_before(jiffies, timeout)) { | |
568 | value = tegra_sor_readl(sor, SOR_TEST); | |
569 | if ((value & SOR_TEST_ATTACHED) != 0) | |
570 | return 0; | |
571 | ||
572 | usleep_range(25, 100); | |
573 | } | |
574 | ||
575 | return -ETIMEDOUT; | |
576 | } | |
577 | ||
578 | static int tegra_sor_wakeup(struct tegra_sor *sor) | |
579 | { | |
6b6b6042 TR |
580 | unsigned long value, timeout; |
581 | ||
6b6b6042 TR |
582 | timeout = jiffies + msecs_to_jiffies(250); |
583 | ||
584 | /* wait for head to wake up */ | |
585 | while (time_before(jiffies, timeout)) { | |
586 | value = tegra_sor_readl(sor, SOR_TEST); | |
587 | value &= SOR_TEST_HEAD_MODE_MASK; | |
588 | ||
589 | if (value == SOR_TEST_HEAD_MODE_AWAKE) | |
590 | return 0; | |
591 | ||
592 | usleep_range(25, 100); | |
593 | } | |
594 | ||
595 | return -ETIMEDOUT; | |
596 | } | |
597 | ||
598 | static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) | |
599 | { | |
28fe2076 | 600 | u32 value; |
6b6b6042 TR |
601 | |
602 | value = tegra_sor_readl(sor, SOR_PWR); | |
603 | value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; | |
604 | tegra_sor_writel(sor, value, SOR_PWR); | |
605 | ||
606 | timeout = jiffies + msecs_to_jiffies(timeout); | |
607 | ||
608 | while (time_before(jiffies, timeout)) { | |
609 | value = tegra_sor_readl(sor, SOR_PWR); | |
610 | if ((value & SOR_PWR_TRIGGER) == 0) | |
611 | return 0; | |
612 | ||
613 | usleep_range(25, 100); | |
614 | } | |
615 | ||
616 | return -ETIMEDOUT; | |
617 | } | |
618 | ||
34fa183b TR |
619 | struct tegra_sor_params { |
620 | /* number of link clocks per line */ | |
621 | unsigned int num_clocks; | |
622 | /* ratio between input and output */ | |
623 | u64 ratio; | |
624 | /* precision factor */ | |
625 | u64 precision; | |
626 | ||
627 | unsigned int active_polarity; | |
628 | unsigned int active_count; | |
629 | unsigned int active_frac; | |
630 | unsigned int tu_size; | |
631 | unsigned int error; | |
632 | }; | |
633 | ||
634 | static int tegra_sor_compute_params(struct tegra_sor *sor, | |
635 | struct tegra_sor_params *params, | |
636 | unsigned int tu_size) | |
637 | { | |
638 | u64 active_sym, active_count, frac, approx; | |
639 | u32 active_polarity, active_frac = 0; | |
640 | const u64 f = params->precision; | |
641 | s64 error; | |
642 | ||
643 | active_sym = params->ratio * tu_size; | |
644 | active_count = div_u64(active_sym, f) * f; | |
645 | frac = active_sym - active_count; | |
646 | ||
647 | /* fraction < 0.5 */ | |
648 | if (frac >= (f / 2)) { | |
649 | active_polarity = 1; | |
650 | frac = f - frac; | |
651 | } else { | |
652 | active_polarity = 0; | |
653 | } | |
654 | ||
655 | if (frac != 0) { | |
656 | frac = div_u64(f * f, frac); /* 1/fraction */ | |
657 | if (frac <= (15 * f)) { | |
658 | active_frac = div_u64(frac, f); | |
659 | ||
660 | /* round up */ | |
661 | if (active_polarity) | |
662 | active_frac++; | |
663 | } else { | |
664 | active_frac = active_polarity ? 1 : 15; | |
665 | } | |
666 | } | |
667 | ||
668 | if (active_frac == 1) | |
669 | active_polarity = 0; | |
670 | ||
671 | if (active_polarity == 1) { | |
672 | if (active_frac) { | |
673 | approx = active_count + (active_frac * (f - 1)) * f; | |
674 | approx = div_u64(approx, active_frac * f); | |
675 | } else { | |
676 | approx = active_count + f; | |
677 | } | |
678 | } else { | |
679 | if (active_frac) | |
680 | approx = active_count + div_u64(f, active_frac); | |
681 | else | |
682 | approx = active_count; | |
683 | } | |
684 | ||
685 | error = div_s64(active_sym - approx, tu_size); | |
686 | error *= params->num_clocks; | |
687 | ||
79211c8e | 688 | if (error <= 0 && abs(error) < params->error) { |
34fa183b TR |
689 | params->active_count = div_u64(active_count, f); |
690 | params->active_polarity = active_polarity; | |
691 | params->active_frac = active_frac; | |
79211c8e | 692 | params->error = abs(error); |
34fa183b TR |
693 | params->tu_size = tu_size; |
694 | ||
695 | if (error == 0) | |
696 | return true; | |
697 | } | |
698 | ||
699 | return false; | |
700 | } | |
701 | ||
a198359e TR |
702 | static int tegra_sor_compute_config(struct tegra_sor *sor, |
703 | const struct drm_display_mode *mode, | |
704 | struct tegra_sor_config *config, | |
705 | struct drm_dp_link *link) | |
34fa183b TR |
706 | { |
707 | const u64 f = 100000, link_rate = link->rate * 1000; | |
708 | const u64 pclk = mode->clock * 1000; | |
7890b576 | 709 | u64 input, output, watermark, num; |
34fa183b | 710 | struct tegra_sor_params params; |
34fa183b TR |
711 | u32 num_syms_per_line; |
712 | unsigned int i; | |
713 | ||
714 | if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel) | |
715 | return -EINVAL; | |
716 | ||
717 | output = link_rate * 8 * link->num_lanes; | |
718 | input = pclk * config->bits_per_pixel; | |
719 | ||
720 | if (input >= output) | |
721 | return -ERANGE; | |
722 | ||
723 | memset(¶ms, 0, sizeof(params)); | |
724 | params.ratio = div64_u64(input * f, output); | |
725 | params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); | |
726 | params.precision = f; | |
727 | params.error = 64 * f; | |
728 | params.tu_size = 64; | |
729 | ||
730 | for (i = params.tu_size; i >= 32; i--) | |
731 | if (tegra_sor_compute_params(sor, ¶ms, i)) | |
732 | break; | |
733 | ||
734 | if (params.active_frac == 0) { | |
735 | config->active_polarity = 0; | |
736 | config->active_count = params.active_count; | |
737 | ||
738 | if (!params.active_polarity) | |
739 | config->active_count--; | |
740 | ||
741 | config->tu_size = params.tu_size; | |
742 | config->active_frac = 1; | |
743 | } else { | |
744 | config->active_polarity = params.active_polarity; | |
745 | config->active_count = params.active_count; | |
746 | config->active_frac = params.active_frac; | |
747 | config->tu_size = params.tu_size; | |
748 | } | |
749 | ||
750 | dev_dbg(sor->dev, | |
751 | "polarity: %d active count: %d tu size: %d active frac: %d\n", | |
752 | config->active_polarity, config->active_count, | |
753 | config->tu_size, config->active_frac); | |
754 | ||
755 | watermark = params.ratio * config->tu_size * (f - params.ratio); | |
756 | watermark = div_u64(watermark, f); | |
757 | ||
758 | watermark = div_u64(watermark + params.error, f); | |
759 | config->watermark = watermark + (config->bits_per_pixel / 8) + 2; | |
760 | num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * | |
761 | (link->num_lanes * 8); | |
762 | ||
763 | if (config->watermark > 30) { | |
764 | config->watermark = 30; | |
765 | dev_err(sor->dev, | |
766 | "unable to compute TU size, forcing watermark to %u\n", | |
767 | config->watermark); | |
768 | } else if (config->watermark > num_syms_per_line) { | |
769 | config->watermark = num_syms_per_line; | |
770 | dev_err(sor->dev, "watermark too high, forcing to %u\n", | |
771 | config->watermark); | |
772 | } | |
773 | ||
7890b576 TR |
774 | /* compute the number of symbols per horizontal blanking interval */ |
775 | num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; | |
776 | config->hblank_symbols = div_u64(num, pclk); | |
777 | ||
778 | if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) | |
779 | config->hblank_symbols -= 3; | |
780 | ||
781 | config->hblank_symbols -= 12 / link->num_lanes; | |
782 | ||
783 | /* compute the number of symbols per vertical blanking interval */ | |
784 | num = (mode->hdisplay - 25) * link_rate; | |
785 | config->vblank_symbols = div_u64(num, pclk); | |
786 | config->vblank_symbols -= 36 / link->num_lanes + 4; | |
787 | ||
788 | dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, | |
789 | config->vblank_symbols); | |
790 | ||
34fa183b TR |
791 | return 0; |
792 | } | |
793 | ||
402f6bcd TR |
794 | static void tegra_sor_apply_config(struct tegra_sor *sor, |
795 | const struct tegra_sor_config *config) | |
796 | { | |
797 | u32 value; | |
798 | ||
799 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); | |
800 | value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; | |
801 | value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); | |
802 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); | |
803 | ||
804 | value = tegra_sor_readl(sor, SOR_DP_CONFIG0); | |
805 | value &= ~SOR_DP_CONFIG_WATERMARK_MASK; | |
806 | value |= SOR_DP_CONFIG_WATERMARK(config->watermark); | |
807 | ||
808 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; | |
809 | value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); | |
810 | ||
811 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; | |
812 | value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); | |
813 | ||
814 | if (config->active_polarity) | |
815 | value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; | |
816 | else | |
817 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; | |
818 | ||
819 | value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; | |
820 | value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; | |
821 | tegra_sor_writel(sor, value, SOR_DP_CONFIG0); | |
822 | ||
823 | value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); | |
824 | value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; | |
825 | value |= config->hblank_symbols & 0xffff; | |
826 | tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); | |
827 | ||
828 | value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); | |
829 | value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; | |
830 | value |= config->vblank_symbols & 0xffff; | |
831 | tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); | |
832 | } | |
833 | ||
2bd1dd39 TR |
834 | static void tegra_sor_mode_set(struct tegra_sor *sor, |
835 | const struct drm_display_mode *mode, | |
c31efa7a | 836 | struct tegra_sor_state *state) |
2bd1dd39 TR |
837 | { |
838 | struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); | |
839 | unsigned int vbe, vse, hbe, hse, vbs, hbs; | |
840 | u32 value; | |
841 | ||
842 | value = tegra_sor_readl(sor, SOR_STATE1); | |
843 | value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; | |
844 | value &= ~SOR_STATE_ASY_CRC_MODE_MASK; | |
845 | value &= ~SOR_STATE_ASY_OWNER_MASK; | |
846 | ||
847 | value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | | |
848 | SOR_STATE_ASY_OWNER(dc->pipe + 1); | |
849 | ||
850 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) | |
851 | value &= ~SOR_STATE_ASY_HSYNCPOL; | |
852 | ||
853 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
854 | value |= SOR_STATE_ASY_HSYNCPOL; | |
855 | ||
856 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) | |
857 | value &= ~SOR_STATE_ASY_VSYNCPOL; | |
858 | ||
859 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
860 | value |= SOR_STATE_ASY_VSYNCPOL; | |
861 | ||
c31efa7a TR |
862 | switch (state->bpc) { |
863 | case 16: | |
864 | value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444; | |
865 | break; | |
866 | ||
867 | case 12: | |
868 | value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444; | |
869 | break; | |
870 | ||
871 | case 10: | |
872 | value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444; | |
873 | break; | |
874 | ||
2bd1dd39 TR |
875 | case 8: |
876 | value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; | |
877 | break; | |
878 | ||
879 | case 6: | |
880 | value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; | |
881 | break; | |
882 | ||
883 | default: | |
c31efa7a | 884 | value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; |
2bd1dd39 TR |
885 | break; |
886 | } | |
887 | ||
888 | tegra_sor_writel(sor, value, SOR_STATE1); | |
889 | ||
890 | /* | |
891 | * TODO: The video timing programming below doesn't seem to match the | |
892 | * register definitions. | |
893 | */ | |
894 | ||
895 | value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); | |
896 | tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe)); | |
897 | ||
898 | /* sync end = sync width - 1 */ | |
899 | vse = mode->vsync_end - mode->vsync_start - 1; | |
900 | hse = mode->hsync_end - mode->hsync_start - 1; | |
901 | ||
902 | value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); | |
903 | tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe)); | |
904 | ||
905 | /* blank end = sync end + back porch */ | |
906 | vbe = vse + (mode->vtotal - mode->vsync_end); | |
907 | hbe = hse + (mode->htotal - mode->hsync_end); | |
908 | ||
909 | value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); | |
910 | tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe)); | |
911 | ||
912 | /* blank start = blank end + active */ | |
913 | vbs = vbe + mode->vdisplay; | |
914 | hbs = hbe + mode->hdisplay; | |
915 | ||
916 | value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); | |
917 | tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe)); | |
918 | ||
919 | /* XXX interlacing support */ | |
920 | tegra_sor_writel(sor, 0x001, SOR_HEAD_STATE5(dc->pipe)); | |
921 | } | |
922 | ||
6fad8f66 TR |
923 | static int tegra_sor_detach(struct tegra_sor *sor) |
924 | { | |
925 | unsigned long value, timeout; | |
926 | ||
927 | /* switch to safe mode */ | |
a9a9e4fd | 928 | value = tegra_sor_readl(sor, SOR_SUPER_STATE1); |
6fad8f66 | 929 | value &= ~SOR_SUPER_STATE_MODE_NORMAL; |
a9a9e4fd | 930 | tegra_sor_writel(sor, value, SOR_SUPER_STATE1); |
6fad8f66 TR |
931 | tegra_sor_super_update(sor); |
932 | ||
933 | timeout = jiffies + msecs_to_jiffies(250); | |
934 | ||
935 | while (time_before(jiffies, timeout)) { | |
936 | value = tegra_sor_readl(sor, SOR_PWR); | |
937 | if (value & SOR_PWR_MODE_SAFE) | |
938 | break; | |
939 | } | |
940 | ||
941 | if ((value & SOR_PWR_MODE_SAFE) == 0) | |
942 | return -ETIMEDOUT; | |
943 | ||
944 | /* go to sleep */ | |
a9a9e4fd | 945 | value = tegra_sor_readl(sor, SOR_SUPER_STATE1); |
6fad8f66 | 946 | value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; |
a9a9e4fd | 947 | tegra_sor_writel(sor, value, SOR_SUPER_STATE1); |
6fad8f66 TR |
948 | tegra_sor_super_update(sor); |
949 | ||
950 | /* detach */ | |
a9a9e4fd | 951 | value = tegra_sor_readl(sor, SOR_SUPER_STATE1); |
6fad8f66 | 952 | value &= ~SOR_SUPER_STATE_ATTACHED; |
a9a9e4fd | 953 | tegra_sor_writel(sor, value, SOR_SUPER_STATE1); |
6fad8f66 TR |
954 | tegra_sor_super_update(sor); |
955 | ||
956 | timeout = jiffies + msecs_to_jiffies(250); | |
957 | ||
958 | while (time_before(jiffies, timeout)) { | |
959 | value = tegra_sor_readl(sor, SOR_TEST); | |
960 | if ((value & SOR_TEST_ATTACHED) == 0) | |
961 | break; | |
962 | ||
963 | usleep_range(25, 100); | |
964 | } | |
965 | ||
966 | if ((value & SOR_TEST_ATTACHED) != 0) | |
967 | return -ETIMEDOUT; | |
968 | ||
969 | return 0; | |
970 | } | |
971 | ||
972 | static int tegra_sor_power_down(struct tegra_sor *sor) | |
973 | { | |
974 | unsigned long value, timeout; | |
975 | int err; | |
976 | ||
977 | value = tegra_sor_readl(sor, SOR_PWR); | |
978 | value &= ~SOR_PWR_NORMAL_STATE_PU; | |
979 | value |= SOR_PWR_TRIGGER; | |
980 | tegra_sor_writel(sor, value, SOR_PWR); | |
981 | ||
982 | timeout = jiffies + msecs_to_jiffies(250); | |
983 | ||
984 | while (time_before(jiffies, timeout)) { | |
985 | value = tegra_sor_readl(sor, SOR_PWR); | |
986 | if ((value & SOR_PWR_TRIGGER) == 0) | |
987 | return 0; | |
988 | ||
989 | usleep_range(25, 100); | |
990 | } | |
991 | ||
992 | if ((value & SOR_PWR_TRIGGER) != 0) | |
993 | return -ETIMEDOUT; | |
994 | ||
25bb2cec TR |
995 | /* switch to safe parent clock */ |
996 | err = tegra_sor_set_parent_clock(sor, sor->clk_safe); | |
6fad8f66 TR |
997 | if (err < 0) |
998 | dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); | |
999 | ||
a9a9e4fd | 1000 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
6fad8f66 TR |
1001 | value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | |
1002 | SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); | |
a9a9e4fd | 1003 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
6fad8f66 TR |
1004 | |
1005 | /* stop lane sequencer */ | |
1006 | value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | | |
1007 | SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; | |
1008 | tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); | |
1009 | ||
1010 | timeout = jiffies + msecs_to_jiffies(250); | |
1011 | ||
1012 | while (time_before(jiffies, timeout)) { | |
1013 | value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); | |
1014 | if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) | |
1015 | break; | |
1016 | ||
1017 | usleep_range(25, 100); | |
1018 | } | |
1019 | ||
1020 | if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) | |
1021 | return -ETIMEDOUT; | |
1022 | ||
a9a9e4fd TR |
1023 | value = tegra_sor_readl(sor, SOR_PLL2); |
1024 | value |= SOR_PLL2_PORT_POWERDOWN; | |
1025 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6fad8f66 TR |
1026 | |
1027 | usleep_range(20, 100); | |
1028 | ||
a9a9e4fd TR |
1029 | value = tegra_sor_readl(sor, SOR_PLL0); |
1030 | value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; | |
1031 | tegra_sor_writel(sor, value, SOR_PLL0); | |
6fad8f66 | 1032 | |
a9a9e4fd TR |
1033 | value = tegra_sor_readl(sor, SOR_PLL2); |
1034 | value |= SOR_PLL2_SEQ_PLLCAPPD; | |
1035 | value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; | |
1036 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6fad8f66 TR |
1037 | |
1038 | usleep_range(20, 100); | |
1039 | ||
1040 | return 0; | |
1041 | } | |
1042 | ||
6fad8f66 TR |
1043 | static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) |
1044 | { | |
1045 | u32 value; | |
1046 | ||
1047 | timeout = jiffies + msecs_to_jiffies(timeout); | |
1048 | ||
1049 | while (time_before(jiffies, timeout)) { | |
a9a9e4fd TR |
1050 | value = tegra_sor_readl(sor, SOR_CRCA); |
1051 | if (value & SOR_CRCA_VALID) | |
6fad8f66 TR |
1052 | return 0; |
1053 | ||
1054 | usleep_range(100, 200); | |
1055 | } | |
1056 | ||
1057 | return -ETIMEDOUT; | |
1058 | } | |
1059 | ||
530239a8 | 1060 | static int tegra_sor_show_crc(struct seq_file *s, void *data) |
6fad8f66 | 1061 | { |
530239a8 TR |
1062 | struct drm_info_node *node = s->private; |
1063 | struct tegra_sor *sor = node->info_ent->data; | |
850bab44 TR |
1064 | struct drm_crtc *crtc = sor->output.encoder.crtc; |
1065 | struct drm_device *drm = node->minor->dev; | |
530239a8 | 1066 | int err = 0; |
6fad8f66 TR |
1067 | u32 value; |
1068 | ||
850bab44 | 1069 | drm_modeset_lock_all(drm); |
6fad8f66 | 1070 | |
850bab44 TR |
1071 | if (!crtc || !crtc->state->active) { |
1072 | err = -EBUSY; | |
6fad8f66 TR |
1073 | goto unlock; |
1074 | } | |
1075 | ||
a9a9e4fd | 1076 | value = tegra_sor_readl(sor, SOR_STATE1); |
6fad8f66 | 1077 | value &= ~SOR_STATE_ASY_CRC_MODE_MASK; |
a9a9e4fd | 1078 | tegra_sor_writel(sor, value, SOR_STATE1); |
6fad8f66 TR |
1079 | |
1080 | value = tegra_sor_readl(sor, SOR_CRC_CNTRL); | |
1081 | value |= SOR_CRC_CNTRL_ENABLE; | |
1082 | tegra_sor_writel(sor, value, SOR_CRC_CNTRL); | |
1083 | ||
1084 | value = tegra_sor_readl(sor, SOR_TEST); | |
1085 | value &= ~SOR_TEST_CRC_POST_SERIALIZE; | |
1086 | tegra_sor_writel(sor, value, SOR_TEST); | |
1087 | ||
1088 | err = tegra_sor_crc_wait(sor, 100); | |
1089 | if (err < 0) | |
1090 | goto unlock; | |
1091 | ||
a9a9e4fd TR |
1092 | tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); |
1093 | value = tegra_sor_readl(sor, SOR_CRCB); | |
6fad8f66 | 1094 | |
530239a8 | 1095 | seq_printf(s, "%08x\n", value); |
6fad8f66 TR |
1096 | |
1097 | unlock: | |
850bab44 | 1098 | drm_modeset_unlock_all(drm); |
6fad8f66 TR |
1099 | return err; |
1100 | } | |
1101 | ||
dab16336 TR |
1102 | static int tegra_sor_show_regs(struct seq_file *s, void *data) |
1103 | { | |
1104 | struct drm_info_node *node = s->private; | |
1105 | struct tegra_sor *sor = node->info_ent->data; | |
850bab44 TR |
1106 | struct drm_crtc *crtc = sor->output.encoder.crtc; |
1107 | struct drm_device *drm = node->minor->dev; | |
1108 | int err = 0; | |
1109 | ||
1110 | drm_modeset_lock_all(drm); | |
1111 | ||
1112 | if (!crtc || !crtc->state->active) { | |
1113 | err = -EBUSY; | |
1114 | goto unlock; | |
1115 | } | |
dab16336 TR |
1116 | |
1117 | #define DUMP_REG(name) \ | |
1118 | seq_printf(s, "%-38s %#05x %08x\n", #name, name, \ | |
1119 | tegra_sor_readl(sor, name)) | |
1120 | ||
1121 | DUMP_REG(SOR_CTXSW); | |
a9a9e4fd TR |
1122 | DUMP_REG(SOR_SUPER_STATE0); |
1123 | DUMP_REG(SOR_SUPER_STATE1); | |
1124 | DUMP_REG(SOR_STATE0); | |
1125 | DUMP_REG(SOR_STATE1); | |
1126 | DUMP_REG(SOR_HEAD_STATE0(0)); | |
1127 | DUMP_REG(SOR_HEAD_STATE0(1)); | |
1128 | DUMP_REG(SOR_HEAD_STATE1(0)); | |
1129 | DUMP_REG(SOR_HEAD_STATE1(1)); | |
1130 | DUMP_REG(SOR_HEAD_STATE2(0)); | |
1131 | DUMP_REG(SOR_HEAD_STATE2(1)); | |
1132 | DUMP_REG(SOR_HEAD_STATE3(0)); | |
1133 | DUMP_REG(SOR_HEAD_STATE3(1)); | |
1134 | DUMP_REG(SOR_HEAD_STATE4(0)); | |
1135 | DUMP_REG(SOR_HEAD_STATE4(1)); | |
1136 | DUMP_REG(SOR_HEAD_STATE5(0)); | |
1137 | DUMP_REG(SOR_HEAD_STATE5(1)); | |
dab16336 TR |
1138 | DUMP_REG(SOR_CRC_CNTRL); |
1139 | DUMP_REG(SOR_DP_DEBUG_MVID); | |
1140 | DUMP_REG(SOR_CLK_CNTRL); | |
1141 | DUMP_REG(SOR_CAP); | |
1142 | DUMP_REG(SOR_PWR); | |
1143 | DUMP_REG(SOR_TEST); | |
a9a9e4fd TR |
1144 | DUMP_REG(SOR_PLL0); |
1145 | DUMP_REG(SOR_PLL1); | |
1146 | DUMP_REG(SOR_PLL2); | |
1147 | DUMP_REG(SOR_PLL3); | |
dab16336 TR |
1148 | DUMP_REG(SOR_CSTM); |
1149 | DUMP_REG(SOR_LVDS); | |
a9a9e4fd TR |
1150 | DUMP_REG(SOR_CRCA); |
1151 | DUMP_REG(SOR_CRCB); | |
dab16336 TR |
1152 | DUMP_REG(SOR_BLANK); |
1153 | DUMP_REG(SOR_SEQ_CTL); | |
1154 | DUMP_REG(SOR_LANE_SEQ_CTL); | |
1155 | DUMP_REG(SOR_SEQ_INST(0)); | |
1156 | DUMP_REG(SOR_SEQ_INST(1)); | |
1157 | DUMP_REG(SOR_SEQ_INST(2)); | |
1158 | DUMP_REG(SOR_SEQ_INST(3)); | |
1159 | DUMP_REG(SOR_SEQ_INST(4)); | |
1160 | DUMP_REG(SOR_SEQ_INST(5)); | |
1161 | DUMP_REG(SOR_SEQ_INST(6)); | |
1162 | DUMP_REG(SOR_SEQ_INST(7)); | |
1163 | DUMP_REG(SOR_SEQ_INST(8)); | |
1164 | DUMP_REG(SOR_SEQ_INST(9)); | |
1165 | DUMP_REG(SOR_SEQ_INST(10)); | |
1166 | DUMP_REG(SOR_SEQ_INST(11)); | |
1167 | DUMP_REG(SOR_SEQ_INST(12)); | |
1168 | DUMP_REG(SOR_SEQ_INST(13)); | |
1169 | DUMP_REG(SOR_SEQ_INST(14)); | |
1170 | DUMP_REG(SOR_SEQ_INST(15)); | |
1171 | DUMP_REG(SOR_PWM_DIV); | |
1172 | DUMP_REG(SOR_PWM_CTL); | |
a9a9e4fd TR |
1173 | DUMP_REG(SOR_VCRC_A0); |
1174 | DUMP_REG(SOR_VCRC_A1); | |
1175 | DUMP_REG(SOR_VCRC_B0); | |
1176 | DUMP_REG(SOR_VCRC_B1); | |
1177 | DUMP_REG(SOR_CCRC_A0); | |
1178 | DUMP_REG(SOR_CCRC_A1); | |
1179 | DUMP_REG(SOR_CCRC_B0); | |
1180 | DUMP_REG(SOR_CCRC_B1); | |
1181 | DUMP_REG(SOR_EDATA_A0); | |
1182 | DUMP_REG(SOR_EDATA_A1); | |
1183 | DUMP_REG(SOR_EDATA_B0); | |
1184 | DUMP_REG(SOR_EDATA_B1); | |
1185 | DUMP_REG(SOR_COUNT_A0); | |
1186 | DUMP_REG(SOR_COUNT_A1); | |
1187 | DUMP_REG(SOR_COUNT_B0); | |
1188 | DUMP_REG(SOR_COUNT_B1); | |
1189 | DUMP_REG(SOR_DEBUG_A0); | |
1190 | DUMP_REG(SOR_DEBUG_A1); | |
1191 | DUMP_REG(SOR_DEBUG_B0); | |
1192 | DUMP_REG(SOR_DEBUG_B1); | |
dab16336 TR |
1193 | DUMP_REG(SOR_TRIG); |
1194 | DUMP_REG(SOR_MSCHECK); | |
1195 | DUMP_REG(SOR_XBAR_CTRL); | |
1196 | DUMP_REG(SOR_XBAR_POL); | |
a9a9e4fd TR |
1197 | DUMP_REG(SOR_DP_LINKCTL0); |
1198 | DUMP_REG(SOR_DP_LINKCTL1); | |
1199 | DUMP_REG(SOR_LANE_DRIVE_CURRENT0); | |
1200 | DUMP_REG(SOR_LANE_DRIVE_CURRENT1); | |
1201 | DUMP_REG(SOR_LANE4_DRIVE_CURRENT0); | |
1202 | DUMP_REG(SOR_LANE4_DRIVE_CURRENT1); | |
1203 | DUMP_REG(SOR_LANE_PREEMPHASIS0); | |
1204 | DUMP_REG(SOR_LANE_PREEMPHASIS1); | |
1205 | DUMP_REG(SOR_LANE4_PREEMPHASIS0); | |
1206 | DUMP_REG(SOR_LANE4_PREEMPHASIS1); | |
1207 | DUMP_REG(SOR_LANE_POSTCURSOR0); | |
1208 | DUMP_REG(SOR_LANE_POSTCURSOR1); | |
1209 | DUMP_REG(SOR_DP_CONFIG0); | |
1210 | DUMP_REG(SOR_DP_CONFIG1); | |
1211 | DUMP_REG(SOR_DP_MN0); | |
1212 | DUMP_REG(SOR_DP_MN1); | |
1213 | DUMP_REG(SOR_DP_PADCTL0); | |
1214 | DUMP_REG(SOR_DP_PADCTL1); | |
1215 | DUMP_REG(SOR_DP_DEBUG0); | |
1216 | DUMP_REG(SOR_DP_DEBUG1); | |
1217 | DUMP_REG(SOR_DP_SPARE0); | |
1218 | DUMP_REG(SOR_DP_SPARE1); | |
dab16336 TR |
1219 | DUMP_REG(SOR_DP_AUDIO_CTRL); |
1220 | DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS); | |
1221 | DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS); | |
1222 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER); | |
a9a9e4fd TR |
1223 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK0); |
1224 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK1); | |
1225 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK2); | |
1226 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK3); | |
1227 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK4); | |
1228 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK5); | |
1229 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK6); | |
dab16336 TR |
1230 | DUMP_REG(SOR_DP_TPG); |
1231 | DUMP_REG(SOR_DP_TPG_CONFIG); | |
a9a9e4fd TR |
1232 | DUMP_REG(SOR_DP_LQ_CSTM0); |
1233 | DUMP_REG(SOR_DP_LQ_CSTM1); | |
1234 | DUMP_REG(SOR_DP_LQ_CSTM2); | |
dab16336 TR |
1235 | |
1236 | #undef DUMP_REG | |
1237 | ||
850bab44 TR |
1238 | unlock: |
1239 | drm_modeset_unlock_all(drm); | |
1240 | return err; | |
dab16336 TR |
1241 | } |
1242 | ||
1243 | static const struct drm_info_list debugfs_files[] = { | |
530239a8 | 1244 | { "crc", tegra_sor_show_crc, 0, NULL }, |
dab16336 TR |
1245 | { "regs", tegra_sor_show_regs, 0, NULL }, |
1246 | }; | |
1247 | ||
6fad8f66 TR |
1248 | static int tegra_sor_debugfs_init(struct tegra_sor *sor, |
1249 | struct drm_minor *minor) | |
6b6b6042 | 1250 | { |
459cc2c6 | 1251 | const char *name = sor->soc->supports_dp ? "sor1" : "sor"; |
dab16336 | 1252 | unsigned int i; |
530239a8 | 1253 | int err; |
6fad8f66 | 1254 | |
459cc2c6 | 1255 | sor->debugfs = debugfs_create_dir(name, minor->debugfs_root); |
6fad8f66 TR |
1256 | if (!sor->debugfs) |
1257 | return -ENOMEM; | |
1258 | ||
dab16336 TR |
1259 | sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), |
1260 | GFP_KERNEL); | |
1261 | if (!sor->debugfs_files) { | |
1262 | err = -ENOMEM; | |
1263 | goto remove; | |
1264 | } | |
1265 | ||
1266 | for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) | |
1267 | sor->debugfs_files[i].data = sor; | |
1268 | ||
1269 | err = drm_debugfs_create_files(sor->debugfs_files, | |
1270 | ARRAY_SIZE(debugfs_files), | |
1271 | sor->debugfs, minor); | |
1272 | if (err < 0) | |
1273 | goto free; | |
1274 | ||
3ff1f22c TR |
1275 | sor->minor = minor; |
1276 | ||
530239a8 | 1277 | return 0; |
6fad8f66 | 1278 | |
dab16336 TR |
1279 | free: |
1280 | kfree(sor->debugfs_files); | |
1281 | sor->debugfs_files = NULL; | |
6fad8f66 | 1282 | remove: |
dab16336 | 1283 | debugfs_remove_recursive(sor->debugfs); |
6fad8f66 TR |
1284 | sor->debugfs = NULL; |
1285 | return err; | |
1286 | } | |
1287 | ||
4009c224 | 1288 | static void tegra_sor_debugfs_exit(struct tegra_sor *sor) |
6fad8f66 | 1289 | { |
dab16336 TR |
1290 | drm_debugfs_remove_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files), |
1291 | sor->minor); | |
1292 | sor->minor = NULL; | |
1293 | ||
1294 | kfree(sor->debugfs_files); | |
066d30f8 | 1295 | sor->debugfs_files = NULL; |
dab16336 TR |
1296 | |
1297 | debugfs_remove_recursive(sor->debugfs); | |
066d30f8 | 1298 | sor->debugfs = NULL; |
6fad8f66 TR |
1299 | } |
1300 | ||
c31efa7a TR |
1301 | static void tegra_sor_connector_reset(struct drm_connector *connector) |
1302 | { | |
1303 | struct tegra_sor_state *state; | |
1304 | ||
1305 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
1306 | if (!state) | |
1307 | return; | |
1308 | ||
1309 | if (connector->state) { | |
1310 | __drm_atomic_helper_connector_destroy_state(connector->state); | |
1311 | kfree(connector->state); | |
1312 | } | |
1313 | ||
1314 | __drm_atomic_helper_connector_reset(connector, &state->base); | |
1315 | } | |
1316 | ||
6fad8f66 TR |
1317 | static enum drm_connector_status |
1318 | tegra_sor_connector_detect(struct drm_connector *connector, bool force) | |
1319 | { | |
1320 | struct tegra_output *output = connector_to_output(connector); | |
1321 | struct tegra_sor *sor = to_sor(output); | |
1322 | ||
9542c237 TR |
1323 | if (sor->aux) |
1324 | return drm_dp_aux_detect(sor->aux); | |
6fad8f66 | 1325 | |
459cc2c6 | 1326 | return tegra_output_connector_detect(connector, force); |
6fad8f66 TR |
1327 | } |
1328 | ||
c31efa7a TR |
1329 | static struct drm_connector_state * |
1330 | tegra_sor_connector_duplicate_state(struct drm_connector *connector) | |
1331 | { | |
1332 | struct tegra_sor_state *state = to_sor_state(connector->state); | |
1333 | struct tegra_sor_state *copy; | |
1334 | ||
1335 | copy = kmemdup(state, sizeof(*state), GFP_KERNEL); | |
1336 | if (!copy) | |
1337 | return NULL; | |
1338 | ||
1339 | __drm_atomic_helper_connector_duplicate_state(connector, ©->base); | |
1340 | ||
1341 | return ©->base; | |
1342 | } | |
1343 | ||
6fad8f66 | 1344 | static const struct drm_connector_funcs tegra_sor_connector_funcs = { |
850bab44 | 1345 | .dpms = drm_atomic_helper_connector_dpms, |
c31efa7a | 1346 | .reset = tegra_sor_connector_reset, |
6fad8f66 TR |
1347 | .detect = tegra_sor_connector_detect, |
1348 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1349 | .destroy = tegra_output_connector_destroy, | |
c31efa7a | 1350 | .atomic_duplicate_state = tegra_sor_connector_duplicate_state, |
4aa3df71 | 1351 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
6fad8f66 TR |
1352 | }; |
1353 | ||
1354 | static int tegra_sor_connector_get_modes(struct drm_connector *connector) | |
1355 | { | |
1356 | struct tegra_output *output = connector_to_output(connector); | |
1357 | struct tegra_sor *sor = to_sor(output); | |
1358 | int err; | |
1359 | ||
9542c237 TR |
1360 | if (sor->aux) |
1361 | drm_dp_aux_enable(sor->aux); | |
6fad8f66 TR |
1362 | |
1363 | err = tegra_output_connector_get_modes(connector); | |
1364 | ||
9542c237 TR |
1365 | if (sor->aux) |
1366 | drm_dp_aux_disable(sor->aux); | |
6fad8f66 TR |
1367 | |
1368 | return err; | |
1369 | } | |
1370 | ||
1371 | static enum drm_mode_status | |
1372 | tegra_sor_connector_mode_valid(struct drm_connector *connector, | |
1373 | struct drm_display_mode *mode) | |
1374 | { | |
64ea25c3 TR |
1375 | /* HDMI 2.0 modes are not yet supported */ |
1376 | if (mode->clock > 340000) | |
1377 | return MODE_NOCLOCK; | |
1378 | ||
6fad8f66 TR |
1379 | return MODE_OK; |
1380 | } | |
1381 | ||
1382 | static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = { | |
1383 | .get_modes = tegra_sor_connector_get_modes, | |
1384 | .mode_valid = tegra_sor_connector_mode_valid, | |
6fad8f66 TR |
1385 | }; |
1386 | ||
1387 | static const struct drm_encoder_funcs tegra_sor_encoder_funcs = { | |
1388 | .destroy = tegra_output_encoder_destroy, | |
1389 | }; | |
1390 | ||
850bab44 | 1391 | static void tegra_sor_edp_disable(struct drm_encoder *encoder) |
6fad8f66 | 1392 | { |
850bab44 TR |
1393 | struct tegra_output *output = encoder_to_output(encoder); |
1394 | struct tegra_dc *dc = to_tegra_dc(encoder->crtc); | |
1395 | struct tegra_sor *sor = to_sor(output); | |
1396 | u32 value; | |
1397 | int err; | |
6fad8f66 | 1398 | |
850bab44 TR |
1399 | if (output->panel) |
1400 | drm_panel_disable(output->panel); | |
6fad8f66 | 1401 | |
850bab44 TR |
1402 | err = tegra_sor_detach(sor); |
1403 | if (err < 0) | |
1404 | dev_err(sor->dev, "failed to detach SOR: %d\n", err); | |
1405 | ||
1406 | tegra_sor_writel(sor, 0, SOR_STATE1); | |
1407 | tegra_sor_update(sor); | |
1408 | ||
1409 | /* | |
1410 | * The following accesses registers of the display controller, so make | |
1411 | * sure it's only executed when the output is attached to one. | |
1412 | */ | |
1413 | if (dc) { | |
1414 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
1415 | value &= ~SOR_ENABLE; | |
1416 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
1417 | ||
1418 | tegra_dc_commit(dc); | |
1419 | } | |
1420 | ||
1421 | err = tegra_sor_power_down(sor); | |
1422 | if (err < 0) | |
1423 | dev_err(sor->dev, "failed to power down SOR: %d\n", err); | |
1424 | ||
9542c237 TR |
1425 | if (sor->aux) { |
1426 | err = drm_dp_aux_disable(sor->aux); | |
850bab44 TR |
1427 | if (err < 0) |
1428 | dev_err(sor->dev, "failed to disable DP: %d\n", err); | |
1429 | } | |
1430 | ||
1431 | err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS); | |
1432 | if (err < 0) | |
1433 | dev_err(sor->dev, "failed to power off I/O rail: %d\n", err); | |
1434 | ||
1435 | if (output->panel) | |
1436 | drm_panel_unprepare(output->panel); | |
1437 | ||
aaff8bd2 | 1438 | pm_runtime_put(sor->dev); |
6fad8f66 TR |
1439 | } |
1440 | ||
459cc2c6 TR |
1441 | #if 0 |
1442 | static int calc_h_ref_to_sync(const struct drm_display_mode *mode, | |
1443 | unsigned int *value) | |
1444 | { | |
1445 | unsigned int hfp, hsw, hbp, a = 0, b; | |
1446 | ||
1447 | hfp = mode->hsync_start - mode->hdisplay; | |
1448 | hsw = mode->hsync_end - mode->hsync_start; | |
1449 | hbp = mode->htotal - mode->hsync_end; | |
1450 | ||
1451 | pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp); | |
1452 | ||
1453 | b = hfp - 1; | |
1454 | ||
1455 | pr_info("a: %u, b: %u\n", a, b); | |
1456 | pr_info("a + hsw + hbp = %u\n", a + hsw + hbp); | |
1457 | ||
1458 | if (a + hsw + hbp <= 11) { | |
1459 | a = 1 + 11 - hsw - hbp; | |
1460 | pr_info("a: %u\n", a); | |
1461 | } | |
1462 | ||
1463 | if (a > b) | |
1464 | return -EINVAL; | |
1465 | ||
1466 | if (hsw < 1) | |
1467 | return -EINVAL; | |
1468 | ||
1469 | if (mode->hdisplay < 16) | |
1470 | return -EINVAL; | |
1471 | ||
1472 | if (value) { | |
1473 | if (b > a && a % 2) | |
1474 | *value = a + 1; | |
1475 | else | |
1476 | *value = a; | |
1477 | } | |
1478 | ||
1479 | return 0; | |
1480 | } | |
1481 | #endif | |
1482 | ||
850bab44 | 1483 | static void tegra_sor_edp_enable(struct drm_encoder *encoder) |
6fad8f66 | 1484 | { |
850bab44 | 1485 | struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; |
6fad8f66 TR |
1486 | struct tegra_output *output = encoder_to_output(encoder); |
1487 | struct tegra_dc *dc = to_tegra_dc(encoder->crtc); | |
6b6b6042 | 1488 | struct tegra_sor *sor = to_sor(output); |
34fa183b | 1489 | struct tegra_sor_config config; |
c31efa7a | 1490 | struct tegra_sor_state *state; |
34fa183b | 1491 | struct drm_dp_link link; |
01b9bea0 | 1492 | u8 rate, lanes; |
2bd1dd39 | 1493 | unsigned int i; |
86f5c52d | 1494 | int err = 0; |
28fe2076 | 1495 | u32 value; |
86f5c52d | 1496 | |
c31efa7a | 1497 | state = to_sor_state(output->connector.state); |
6b6b6042 | 1498 | |
aaff8bd2 | 1499 | pm_runtime_get_sync(sor->dev); |
6b6b6042 | 1500 | |
6fad8f66 TR |
1501 | if (output->panel) |
1502 | drm_panel_prepare(output->panel); | |
1503 | ||
01b9bea0 TR |
1504 | err = drm_dp_aux_enable(sor->aux); |
1505 | if (err < 0) | |
1506 | dev_err(sor->dev, "failed to enable DP: %d\n", err); | |
34fa183b | 1507 | |
01b9bea0 TR |
1508 | err = drm_dp_link_probe(sor->aux, &link); |
1509 | if (err < 0) { | |
1510 | dev_err(sor->dev, "failed to probe eDP link: %d\n", err); | |
1511 | return; | |
6b6b6042 TR |
1512 | } |
1513 | ||
25bb2cec TR |
1514 | /* switch to safe parent clock */ |
1515 | err = tegra_sor_set_parent_clock(sor, sor->clk_safe); | |
6b6b6042 TR |
1516 | if (err < 0) |
1517 | dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); | |
1518 | ||
34fa183b | 1519 | memset(&config, 0, sizeof(config)); |
c31efa7a | 1520 | config.bits_per_pixel = state->bpc * 3; |
34fa183b | 1521 | |
a198359e | 1522 | err = tegra_sor_compute_config(sor, mode, &config, &link); |
34fa183b | 1523 | if (err < 0) |
a198359e | 1524 | dev_err(sor->dev, "failed to compute configuration: %d\n", err); |
34fa183b | 1525 | |
6b6b6042 TR |
1526 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
1527 | value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; | |
1528 | value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; | |
1529 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); | |
1530 | ||
a9a9e4fd TR |
1531 | value = tegra_sor_readl(sor, SOR_PLL2); |
1532 | value &= ~SOR_PLL2_BANDGAP_POWERDOWN; | |
1533 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6b6b6042 TR |
1534 | usleep_range(20, 100); |
1535 | ||
a9a9e4fd TR |
1536 | value = tegra_sor_readl(sor, SOR_PLL3); |
1537 | value |= SOR_PLL3_PLL_VDD_MODE_3V3; | |
1538 | tegra_sor_writel(sor, value, SOR_PLL3); | |
6b6b6042 | 1539 | |
a9a9e4fd TR |
1540 | value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST | |
1541 | SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT; | |
1542 | tegra_sor_writel(sor, value, SOR_PLL0); | |
6b6b6042 | 1543 | |
a9a9e4fd TR |
1544 | value = tegra_sor_readl(sor, SOR_PLL2); |
1545 | value |= SOR_PLL2_SEQ_PLLCAPPD; | |
1546 | value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; | |
1547 | value |= SOR_PLL2_LVDS_ENABLE; | |
1548 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6b6b6042 | 1549 | |
a9a9e4fd TR |
1550 | value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM; |
1551 | tegra_sor_writel(sor, value, SOR_PLL1); | |
6b6b6042 TR |
1552 | |
1553 | while (true) { | |
a9a9e4fd TR |
1554 | value = tegra_sor_readl(sor, SOR_PLL2); |
1555 | if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0) | |
6b6b6042 TR |
1556 | break; |
1557 | ||
1558 | usleep_range(250, 1000); | |
1559 | } | |
1560 | ||
a9a9e4fd TR |
1561 | value = tegra_sor_readl(sor, SOR_PLL2); |
1562 | value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; | |
1563 | value &= ~SOR_PLL2_PORT_POWERDOWN; | |
1564 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6b6b6042 TR |
1565 | |
1566 | /* | |
1567 | * power up | |
1568 | */ | |
1569 | ||
1570 | /* set safe link bandwidth (1.62 Gbps) */ | |
1571 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); | |
1572 | value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; | |
1573 | value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; | |
1574 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); | |
1575 | ||
1576 | /* step 1 */ | |
a9a9e4fd TR |
1577 | value = tegra_sor_readl(sor, SOR_PLL2); |
1578 | value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN | | |
1579 | SOR_PLL2_BANDGAP_POWERDOWN; | |
1580 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6b6b6042 | 1581 | |
a9a9e4fd TR |
1582 | value = tegra_sor_readl(sor, SOR_PLL0); |
1583 | value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; | |
1584 | tegra_sor_writel(sor, value, SOR_PLL0); | |
6b6b6042 | 1585 | |
a9a9e4fd | 1586 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
6b6b6042 | 1587 | value &= ~SOR_DP_PADCTL_PAD_CAL_PD; |
a9a9e4fd | 1588 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
6b6b6042 TR |
1589 | |
1590 | /* step 2 */ | |
1591 | err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); | |
850bab44 | 1592 | if (err < 0) |
6b6b6042 | 1593 | dev_err(sor->dev, "failed to power on I/O rail: %d\n", err); |
6b6b6042 TR |
1594 | |
1595 | usleep_range(5, 100); | |
1596 | ||
1597 | /* step 3 */ | |
a9a9e4fd TR |
1598 | value = tegra_sor_readl(sor, SOR_PLL2); |
1599 | value &= ~SOR_PLL2_BANDGAP_POWERDOWN; | |
1600 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6b6b6042 TR |
1601 | |
1602 | usleep_range(20, 100); | |
1603 | ||
1604 | /* step 4 */ | |
a9a9e4fd TR |
1605 | value = tegra_sor_readl(sor, SOR_PLL0); |
1606 | value &= ~SOR_PLL0_VCOPD; | |
1607 | value &= ~SOR_PLL0_PWR; | |
1608 | tegra_sor_writel(sor, value, SOR_PLL0); | |
6b6b6042 | 1609 | |
a9a9e4fd TR |
1610 | value = tegra_sor_readl(sor, SOR_PLL2); |
1611 | value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; | |
1612 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6b6b6042 TR |
1613 | |
1614 | usleep_range(200, 1000); | |
1615 | ||
1616 | /* step 5 */ | |
a9a9e4fd TR |
1617 | value = tegra_sor_readl(sor, SOR_PLL2); |
1618 | value &= ~SOR_PLL2_PORT_POWERDOWN; | |
1619 | tegra_sor_writel(sor, value, SOR_PLL2); | |
6b6b6042 | 1620 | |
30b49435 TR |
1621 | /* XXX not in TRM */ |
1622 | for (value = 0, i = 0; i < 5; i++) | |
1623 | value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | | |
1624 | SOR_XBAR_CTRL_LINK1_XSEL(i, i); | |
1625 | ||
1626 | tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); | |
1627 | tegra_sor_writel(sor, value, SOR_XBAR_CTRL); | |
1628 | ||
25bb2cec TR |
1629 | /* switch to DP parent clock */ |
1630 | err = tegra_sor_set_parent_clock(sor, sor->clk_dp); | |
6b6b6042 | 1631 | if (err < 0) |
25bb2cec | 1632 | dev_err(sor->dev, "failed to set parent clock: %d\n", err); |
6b6b6042 | 1633 | |
899451b7 | 1634 | /* power DP lanes */ |
a9a9e4fd | 1635 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
899451b7 TR |
1636 | |
1637 | if (link.num_lanes <= 2) | |
1638 | value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); | |
1639 | else | |
1640 | value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2; | |
1641 | ||
1642 | if (link.num_lanes <= 1) | |
1643 | value &= ~SOR_DP_PADCTL_PD_TXD_1; | |
1644 | else | |
1645 | value |= SOR_DP_PADCTL_PD_TXD_1; | |
1646 | ||
1647 | if (link.num_lanes == 0) | |
1648 | value &= ~SOR_DP_PADCTL_PD_TXD_0; | |
1649 | else | |
1650 | value |= SOR_DP_PADCTL_PD_TXD_0; | |
1651 | ||
a9a9e4fd | 1652 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
6b6b6042 | 1653 | |
a9a9e4fd | 1654 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); |
6b6b6042 | 1655 | value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; |
0c90a184 | 1656 | value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes); |
a9a9e4fd | 1657 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); |
6b6b6042 TR |
1658 | |
1659 | /* start lane sequencer */ | |
1660 | value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | | |
1661 | SOR_LANE_SEQ_CTL_POWER_STATE_UP; | |
1662 | tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); | |
1663 | ||
1664 | while (true) { | |
1665 | value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); | |
1666 | if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) | |
1667 | break; | |
1668 | ||
1669 | usleep_range(250, 1000); | |
1670 | } | |
1671 | ||
a4263fed | 1672 | /* set link bandwidth */ |
6b6b6042 TR |
1673 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
1674 | value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; | |
a4263fed | 1675 | value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; |
6b6b6042 TR |
1676 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); |
1677 | ||
402f6bcd TR |
1678 | tegra_sor_apply_config(sor, &config); |
1679 | ||
1680 | /* enable link */ | |
a9a9e4fd | 1681 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); |
6b6b6042 | 1682 | value |= SOR_DP_LINKCTL_ENABLE; |
6b6b6042 | 1683 | value |= SOR_DP_LINKCTL_ENHANCED_FRAME; |
a9a9e4fd | 1684 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); |
6b6b6042 TR |
1685 | |
1686 | for (i = 0, value = 0; i < 4; i++) { | |
1687 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | | |
1688 | SOR_DP_TPG_SCRAMBLER_GALIOS | | |
1689 | SOR_DP_TPG_PATTERN_NONE; | |
1690 | value = (value << 8) | lane; | |
1691 | } | |
1692 | ||
1693 | tegra_sor_writel(sor, value, SOR_DP_TPG); | |
1694 | ||
6b6b6042 | 1695 | /* enable pad calibration logic */ |
a9a9e4fd | 1696 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
6b6b6042 | 1697 | value |= SOR_DP_PADCTL_PAD_CAL_PD; |
a9a9e4fd | 1698 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
6b6b6042 | 1699 | |
01b9bea0 TR |
1700 | err = drm_dp_link_probe(sor->aux, &link); |
1701 | if (err < 0) | |
1702 | dev_err(sor->dev, "failed to probe eDP link: %d\n", err); | |
6b6b6042 | 1703 | |
01b9bea0 TR |
1704 | err = drm_dp_link_power_up(sor->aux, &link); |
1705 | if (err < 0) | |
1706 | dev_err(sor->dev, "failed to power up eDP link: %d\n", err); | |
6b6b6042 | 1707 | |
01b9bea0 TR |
1708 | err = drm_dp_link_configure(sor->aux, &link); |
1709 | if (err < 0) | |
1710 | dev_err(sor->dev, "failed to configure eDP link: %d\n", err); | |
6b6b6042 | 1711 | |
01b9bea0 TR |
1712 | rate = drm_dp_link_rate_to_bw_code(link.rate); |
1713 | lanes = link.num_lanes; | |
6b6b6042 | 1714 | |
01b9bea0 TR |
1715 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
1716 | value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; | |
1717 | value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); | |
1718 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); | |
6b6b6042 | 1719 | |
01b9bea0 TR |
1720 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); |
1721 | value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; | |
1722 | value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); | |
6b6b6042 | 1723 | |
01b9bea0 TR |
1724 | if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) |
1725 | value |= SOR_DP_LINKCTL_ENHANCED_FRAME; | |
6b6b6042 | 1726 | |
01b9bea0 | 1727 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); |
6b6b6042 | 1728 | |
01b9bea0 | 1729 | /* disable training pattern generator */ |
6b6b6042 | 1730 | |
01b9bea0 TR |
1731 | for (i = 0; i < link.num_lanes; i++) { |
1732 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | | |
1733 | SOR_DP_TPG_SCRAMBLER_GALIOS | | |
1734 | SOR_DP_TPG_PATTERN_NONE; | |
1735 | value = (value << 8) | lane; | |
1736 | } | |
6b6b6042 | 1737 | |
01b9bea0 | 1738 | tegra_sor_writel(sor, value, SOR_DP_TPG); |
6b6b6042 | 1739 | |
01b9bea0 TR |
1740 | err = tegra_sor_dp_train_fast(sor, &link); |
1741 | if (err < 0) | |
1742 | dev_err(sor->dev, "DP fast link training failed: %d\n", err); | |
6b6b6042 | 1743 | |
01b9bea0 | 1744 | dev_dbg(sor->dev, "fast link training succeeded\n"); |
6b6b6042 TR |
1745 | |
1746 | err = tegra_sor_power_up(sor, 250); | |
850bab44 | 1747 | if (err < 0) |
6b6b6042 | 1748 | dev_err(sor->dev, "failed to power up SOR: %d\n", err); |
6b6b6042 | 1749 | |
6fad8f66 TR |
1750 | /* CSTM (LVDS, link A/B, upper) */ |
1751 | value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | | |
1752 | SOR_CSTM_UPPER; | |
1753 | tegra_sor_writel(sor, value, SOR_CSTM); | |
1754 | ||
2bd1dd39 TR |
1755 | /* use DP-A protocol */ |
1756 | value = tegra_sor_readl(sor, SOR_STATE1); | |
1757 | value &= ~SOR_STATE_ASY_PROTOCOL_MASK; | |
1758 | value |= SOR_STATE_ASY_PROTOCOL_DP_A; | |
1759 | tegra_sor_writel(sor, value, SOR_STATE1); | |
1760 | ||
c31efa7a | 1761 | tegra_sor_mode_set(sor, mode, state); |
2bd1dd39 | 1762 | |
6fad8f66 TR |
1763 | /* PWM setup */ |
1764 | err = tegra_sor_setup_pwm(sor, 250); | |
850bab44 | 1765 | if (err < 0) |
6fad8f66 | 1766 | dev_err(sor->dev, "failed to setup PWM: %d\n", err); |
6b6b6042 | 1767 | |
666cb873 TR |
1768 | tegra_sor_update(sor); |
1769 | ||
6fad8f66 TR |
1770 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
1771 | value |= SOR_ENABLE; | |
1772 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
6b6b6042 | 1773 | |
666cb873 | 1774 | tegra_dc_commit(dc); |
6b6b6042 | 1775 | |
6fad8f66 | 1776 | err = tegra_sor_attach(sor); |
850bab44 | 1777 | if (err < 0) |
6fad8f66 | 1778 | dev_err(sor->dev, "failed to attach SOR: %d\n", err); |
6b6b6042 | 1779 | |
6fad8f66 | 1780 | err = tegra_sor_wakeup(sor); |
850bab44 | 1781 | if (err < 0) |
6fad8f66 | 1782 | dev_err(sor->dev, "failed to enable DC: %d\n", err); |
6b6b6042 | 1783 | |
6fad8f66 TR |
1784 | if (output->panel) |
1785 | drm_panel_enable(output->panel); | |
a82752e1 TR |
1786 | } |
1787 | ||
82f1511c TR |
1788 | static int |
1789 | tegra_sor_encoder_atomic_check(struct drm_encoder *encoder, | |
1790 | struct drm_crtc_state *crtc_state, | |
1791 | struct drm_connector_state *conn_state) | |
1792 | { | |
1793 | struct tegra_output *output = encoder_to_output(encoder); | |
c31efa7a | 1794 | struct tegra_sor_state *state = to_sor_state(conn_state); |
82f1511c TR |
1795 | struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); |
1796 | unsigned long pclk = crtc_state->mode.clock * 1000; | |
1797 | struct tegra_sor *sor = to_sor(output); | |
c31efa7a | 1798 | struct drm_display_info *info; |
82f1511c TR |
1799 | int err; |
1800 | ||
c31efa7a TR |
1801 | info = &output->connector.display_info; |
1802 | ||
82f1511c TR |
1803 | err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, |
1804 | pclk, 0); | |
1805 | if (err < 0) { | |
1806 | dev_err(output->dev, "failed to setup CRTC state: %d\n", err); | |
1807 | return err; | |
1808 | } | |
1809 | ||
c31efa7a TR |
1810 | switch (info->bpc) { |
1811 | case 8: | |
1812 | case 6: | |
1813 | state->bpc = info->bpc; | |
1814 | break; | |
1815 | ||
1816 | default: | |
1817 | DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc); | |
1818 | state->bpc = 8; | |
1819 | break; | |
1820 | } | |
1821 | ||
82f1511c TR |
1822 | return 0; |
1823 | } | |
1824 | ||
459cc2c6 | 1825 | static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = { |
850bab44 TR |
1826 | .disable = tegra_sor_edp_disable, |
1827 | .enable = tegra_sor_edp_enable, | |
82f1511c | 1828 | .atomic_check = tegra_sor_encoder_atomic_check, |
a82752e1 TR |
1829 | }; |
1830 | ||
459cc2c6 TR |
1831 | static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size) |
1832 | { | |
1833 | u32 value = 0; | |
1834 | size_t i; | |
1835 | ||
1836 | for (i = size; i > 0; i--) | |
1837 | value = (value << 8) | ptr[i - 1]; | |
1838 | ||
1839 | return value; | |
1840 | } | |
1841 | ||
1842 | static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, | |
1843 | const void *data, size_t size) | |
1844 | { | |
1845 | const u8 *ptr = data; | |
1846 | unsigned long offset; | |
1847 | size_t i, j; | |
1848 | u32 value; | |
1849 | ||
1850 | switch (ptr[0]) { | |
1851 | case HDMI_INFOFRAME_TYPE_AVI: | |
1852 | offset = SOR_HDMI_AVI_INFOFRAME_HEADER; | |
1853 | break; | |
1854 | ||
1855 | case HDMI_INFOFRAME_TYPE_AUDIO: | |
1856 | offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER; | |
1857 | break; | |
1858 | ||
1859 | case HDMI_INFOFRAME_TYPE_VENDOR: | |
1860 | offset = SOR_HDMI_VSI_INFOFRAME_HEADER; | |
1861 | break; | |
1862 | ||
1863 | default: | |
1864 | dev_err(sor->dev, "unsupported infoframe type: %02x\n", | |
1865 | ptr[0]); | |
1866 | return; | |
1867 | } | |
1868 | ||
1869 | value = INFOFRAME_HEADER_TYPE(ptr[0]) | | |
1870 | INFOFRAME_HEADER_VERSION(ptr[1]) | | |
1871 | INFOFRAME_HEADER_LEN(ptr[2]); | |
1872 | tegra_sor_writel(sor, value, offset); | |
1873 | offset++; | |
1874 | ||
1875 | /* | |
1876 | * Each subpack contains 7 bytes, divided into: | |
1877 | * - subpack_low: bytes 0 - 3 | |
1878 | * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) | |
1879 | */ | |
1880 | for (i = 3, j = 0; i < size; i += 7, j += 8) { | |
1881 | size_t rem = size - i, num = min_t(size_t, rem, 4); | |
1882 | ||
1883 | value = tegra_sor_hdmi_subpack(&ptr[i], num); | |
1884 | tegra_sor_writel(sor, value, offset++); | |
1885 | ||
1886 | num = min_t(size_t, rem - num, 3); | |
1887 | ||
1888 | value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); | |
1889 | tegra_sor_writel(sor, value, offset++); | |
1890 | } | |
1891 | } | |
1892 | ||
1893 | static int | |
1894 | tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, | |
1895 | const struct drm_display_mode *mode) | |
1896 | { | |
1897 | u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; | |
1898 | struct hdmi_avi_infoframe frame; | |
1899 | u32 value; | |
1900 | int err; | |
1901 | ||
1902 | /* disable AVI infoframe */ | |
1903 | value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); | |
1904 | value &= ~INFOFRAME_CTRL_SINGLE; | |
1905 | value &= ~INFOFRAME_CTRL_OTHER; | |
1906 | value &= ~INFOFRAME_CTRL_ENABLE; | |
1907 | tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); | |
1908 | ||
1909 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); | |
1910 | if (err < 0) { | |
1911 | dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); | |
1912 | return err; | |
1913 | } | |
1914 | ||
1915 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); | |
1916 | if (err < 0) { | |
1917 | dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); | |
1918 | return err; | |
1919 | } | |
1920 | ||
1921 | tegra_sor_hdmi_write_infopack(sor, buffer, err); | |
1922 | ||
1923 | /* enable AVI infoframe */ | |
1924 | value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); | |
1925 | value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; | |
1926 | value |= INFOFRAME_CTRL_ENABLE; | |
1927 | tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); | |
1928 | ||
1929 | return 0; | |
1930 | } | |
1931 | ||
1932 | static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) | |
1933 | { | |
1934 | u32 value; | |
1935 | ||
1936 | value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); | |
1937 | value &= ~INFOFRAME_CTRL_ENABLE; | |
1938 | tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); | |
1939 | } | |
1940 | ||
1941 | static struct tegra_sor_hdmi_settings * | |
1942 | tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) | |
1943 | { | |
1944 | unsigned int i; | |
1945 | ||
1946 | for (i = 0; i < sor->num_settings; i++) | |
1947 | if (frequency <= sor->settings[i].frequency) | |
1948 | return &sor->settings[i]; | |
1949 | ||
1950 | return NULL; | |
1951 | } | |
1952 | ||
1953 | static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) | |
1954 | { | |
1955 | struct tegra_output *output = encoder_to_output(encoder); | |
1956 | struct tegra_dc *dc = to_tegra_dc(encoder->crtc); | |
1957 | struct tegra_sor *sor = to_sor(output); | |
1958 | u32 value; | |
1959 | int err; | |
1960 | ||
1961 | err = tegra_sor_detach(sor); | |
1962 | if (err < 0) | |
1963 | dev_err(sor->dev, "failed to detach SOR: %d\n", err); | |
1964 | ||
1965 | tegra_sor_writel(sor, 0, SOR_STATE1); | |
1966 | tegra_sor_update(sor); | |
1967 | ||
1968 | /* disable display to SOR clock */ | |
1969 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
1970 | value &= ~SOR1_TIMING_CYA; | |
1971 | value &= ~SOR1_ENABLE; | |
1972 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
1973 | ||
1974 | tegra_dc_commit(dc); | |
1975 | ||
1976 | err = tegra_sor_power_down(sor); | |
1977 | if (err < 0) | |
1978 | dev_err(sor->dev, "failed to power down SOR: %d\n", err); | |
1979 | ||
1980 | err = tegra_io_rail_power_off(TEGRA_IO_RAIL_HDMI); | |
1981 | if (err < 0) | |
1982 | dev_err(sor->dev, "failed to power off HDMI rail: %d\n", err); | |
1983 | ||
aaff8bd2 | 1984 | pm_runtime_put(sor->dev); |
459cc2c6 TR |
1985 | } |
1986 | ||
1987 | static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) | |
1988 | { | |
1989 | struct tegra_output *output = encoder_to_output(encoder); | |
1990 | unsigned int h_ref_to_sync = 1, pulse_start, max_ac; | |
1991 | struct tegra_dc *dc = to_tegra_dc(encoder->crtc); | |
459cc2c6 TR |
1992 | struct tegra_sor_hdmi_settings *settings; |
1993 | struct tegra_sor *sor = to_sor(output); | |
c31efa7a | 1994 | struct tegra_sor_state *state; |
459cc2c6 | 1995 | struct drm_display_mode *mode; |
30b49435 | 1996 | unsigned int div, i; |
459cc2c6 TR |
1997 | u32 value; |
1998 | int err; | |
1999 | ||
c31efa7a | 2000 | state = to_sor_state(output->connector.state); |
459cc2c6 | 2001 | mode = &encoder->crtc->state->adjusted_mode; |
459cc2c6 | 2002 | |
aaff8bd2 | 2003 | pm_runtime_get_sync(sor->dev); |
459cc2c6 | 2004 | |
25bb2cec TR |
2005 | /* switch to safe parent clock */ |
2006 | err = tegra_sor_set_parent_clock(sor, sor->clk_safe); | |
459cc2c6 TR |
2007 | if (err < 0) |
2008 | dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); | |
2009 | ||
2010 | div = clk_get_rate(sor->clk) / 1000000 * 4; | |
2011 | ||
2012 | err = tegra_io_rail_power_on(TEGRA_IO_RAIL_HDMI); | |
2013 | if (err < 0) | |
2014 | dev_err(sor->dev, "failed to power on HDMI rail: %d\n", err); | |
2015 | ||
2016 | usleep_range(20, 100); | |
2017 | ||
2018 | value = tegra_sor_readl(sor, SOR_PLL2); | |
2019 | value &= ~SOR_PLL2_BANDGAP_POWERDOWN; | |
2020 | tegra_sor_writel(sor, value, SOR_PLL2); | |
2021 | ||
2022 | usleep_range(20, 100); | |
2023 | ||
2024 | value = tegra_sor_readl(sor, SOR_PLL3); | |
2025 | value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; | |
2026 | tegra_sor_writel(sor, value, SOR_PLL3); | |
2027 | ||
2028 | value = tegra_sor_readl(sor, SOR_PLL0); | |
2029 | value &= ~SOR_PLL0_VCOPD; | |
2030 | value &= ~SOR_PLL0_PWR; | |
2031 | tegra_sor_writel(sor, value, SOR_PLL0); | |
2032 | ||
2033 | value = tegra_sor_readl(sor, SOR_PLL2); | |
2034 | value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; | |
2035 | tegra_sor_writel(sor, value, SOR_PLL2); | |
2036 | ||
2037 | usleep_range(200, 400); | |
2038 | ||
2039 | value = tegra_sor_readl(sor, SOR_PLL2); | |
2040 | value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; | |
2041 | value &= ~SOR_PLL2_PORT_POWERDOWN; | |
2042 | tegra_sor_writel(sor, value, SOR_PLL2); | |
2043 | ||
2044 | usleep_range(20, 100); | |
2045 | ||
2046 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); | |
2047 | value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | | |
2048 | SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; | |
2049 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); | |
2050 | ||
2051 | while (true) { | |
2052 | value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); | |
2053 | if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) | |
2054 | break; | |
2055 | ||
2056 | usleep_range(250, 1000); | |
2057 | } | |
2058 | ||
2059 | value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | | |
2060 | SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5); | |
2061 | tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); | |
2062 | ||
2063 | while (true) { | |
2064 | value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); | |
2065 | if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) | |
2066 | break; | |
2067 | ||
2068 | usleep_range(250, 1000); | |
2069 | } | |
2070 | ||
2071 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); | |
2072 | value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; | |
2073 | value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; | |
2074 | ||
2075 | if (mode->clock < 340000) | |
2076 | value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; | |
2077 | else | |
2078 | value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; | |
2079 | ||
2080 | value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; | |
2081 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); | |
2082 | ||
2083 | value = tegra_sor_readl(sor, SOR_DP_SPARE0); | |
2084 | value |= SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; | |
2085 | value &= ~SOR_DP_SPARE_PANEL_INTERNAL; | |
2086 | value |= SOR_DP_SPARE_SEQ_ENABLE; | |
2087 | tegra_sor_writel(sor, value, SOR_DP_SPARE0); | |
2088 | ||
2089 | value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | | |
2090 | SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8); | |
2091 | tegra_sor_writel(sor, value, SOR_SEQ_CTL); | |
2092 | ||
2093 | value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | | |
2094 | SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1); | |
2095 | tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); | |
2096 | tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); | |
2097 | ||
2098 | /* program the reference clock */ | |
2099 | value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); | |
2100 | tegra_sor_writel(sor, value, SOR_REFCLK); | |
2101 | ||
30b49435 TR |
2102 | /* XXX not in TRM */ |
2103 | for (value = 0, i = 0; i < 5; i++) | |
2104 | value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | | |
2105 | SOR_XBAR_CTRL_LINK1_XSEL(i, i); | |
459cc2c6 TR |
2106 | |
2107 | tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); | |
30b49435 | 2108 | tegra_sor_writel(sor, value, SOR_XBAR_CTRL); |
459cc2c6 | 2109 | |
25bb2cec | 2110 | /* switch to parent clock */ |
618dee39 TR |
2111 | err = clk_set_parent(sor->clk_src, sor->clk_parent); |
2112 | if (err < 0) | |
2113 | dev_err(sor->dev, "failed to set source clock: %d\n", err); | |
2114 | ||
2115 | err = tegra_sor_set_parent_clock(sor, sor->clk_src); | |
459cc2c6 TR |
2116 | if (err < 0) |
2117 | dev_err(sor->dev, "failed to set parent clock: %d\n", err); | |
2118 | ||
2119 | value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); | |
2120 | ||
2121 | /* XXX is this the proper check? */ | |
2122 | if (mode->clock < 75000) | |
2123 | value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; | |
2124 | ||
2125 | tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); | |
2126 | ||
2127 | max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32; | |
2128 | ||
2129 | value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | | |
2130 | SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY); | |
2131 | tegra_sor_writel(sor, value, SOR_HDMI_CTRL); | |
2132 | ||
2133 | /* H_PULSE2 setup */ | |
2134 | pulse_start = h_ref_to_sync + (mode->hsync_end - mode->hsync_start) + | |
2135 | (mode->htotal - mode->hsync_end) - 10; | |
2136 | ||
2137 | value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | | |
2138 | PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL; | |
2139 | tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); | |
2140 | ||
2141 | value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); | |
2142 | tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); | |
2143 | ||
2144 | value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); | |
2145 | value |= H_PULSE2_ENABLE; | |
2146 | tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); | |
2147 | ||
2148 | /* infoframe setup */ | |
2149 | err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); | |
2150 | if (err < 0) | |
2151 | dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); | |
2152 | ||
2153 | /* XXX HDMI audio support not implemented yet */ | |
2154 | tegra_sor_hdmi_disable_audio_infoframe(sor); | |
2155 | ||
2156 | /* use single TMDS protocol */ | |
2157 | value = tegra_sor_readl(sor, SOR_STATE1); | |
2158 | value &= ~SOR_STATE_ASY_PROTOCOL_MASK; | |
2159 | value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; | |
2160 | tegra_sor_writel(sor, value, SOR_STATE1); | |
2161 | ||
2162 | /* power up pad calibration */ | |
2163 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); | |
2164 | value &= ~SOR_DP_PADCTL_PAD_CAL_PD; | |
2165 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); | |
2166 | ||
2167 | /* production settings */ | |
2168 | settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); | |
db8b42fb DC |
2169 | if (!settings) { |
2170 | dev_err(sor->dev, "no settings for pixel clock %d Hz\n", | |
2171 | mode->clock * 1000); | |
459cc2c6 TR |
2172 | return; |
2173 | } | |
2174 | ||
2175 | value = tegra_sor_readl(sor, SOR_PLL0); | |
2176 | value &= ~SOR_PLL0_ICHPMP_MASK; | |
2177 | value &= ~SOR_PLL0_VCOCAP_MASK; | |
2178 | value |= SOR_PLL0_ICHPMP(settings->ichpmp); | |
2179 | value |= SOR_PLL0_VCOCAP(settings->vcocap); | |
2180 | tegra_sor_writel(sor, value, SOR_PLL0); | |
2181 | ||
2182 | tegra_sor_dp_term_calibrate(sor); | |
2183 | ||
2184 | value = tegra_sor_readl(sor, SOR_PLL1); | |
2185 | value &= ~SOR_PLL1_LOADADJ_MASK; | |
2186 | value |= SOR_PLL1_LOADADJ(settings->loadadj); | |
2187 | tegra_sor_writel(sor, value, SOR_PLL1); | |
2188 | ||
2189 | value = tegra_sor_readl(sor, SOR_PLL3); | |
2190 | value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; | |
2191 | value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref); | |
2192 | tegra_sor_writel(sor, value, SOR_PLL3); | |
2193 | ||
2194 | value = settings->drive_current[0] << 24 | | |
2195 | settings->drive_current[1] << 16 | | |
2196 | settings->drive_current[2] << 8 | | |
2197 | settings->drive_current[3] << 0; | |
2198 | tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); | |
2199 | ||
2200 | value = settings->preemphasis[0] << 24 | | |
2201 | settings->preemphasis[1] << 16 | | |
2202 | settings->preemphasis[2] << 8 | | |
2203 | settings->preemphasis[3] << 0; | |
2204 | tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); | |
2205 | ||
2206 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); | |
2207 | value &= ~SOR_DP_PADCTL_TX_PU_MASK; | |
2208 | value |= SOR_DP_PADCTL_TX_PU_ENABLE; | |
2209 | value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu); | |
2210 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); | |
2211 | ||
2212 | /* power down pad calibration */ | |
2213 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); | |
2214 | value |= SOR_DP_PADCTL_PAD_CAL_PD; | |
2215 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); | |
2216 | ||
2217 | /* miscellaneous display controller settings */ | |
2218 | value = VSYNC_H_POSITION(1); | |
2219 | tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); | |
2220 | ||
2221 | value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); | |
2222 | value &= ~DITHER_CONTROL_MASK; | |
2223 | value &= ~BASE_COLOR_SIZE_MASK; | |
2224 | ||
c31efa7a | 2225 | switch (state->bpc) { |
459cc2c6 TR |
2226 | case 6: |
2227 | value |= BASE_COLOR_SIZE_666; | |
2228 | break; | |
2229 | ||
2230 | case 8: | |
2231 | value |= BASE_COLOR_SIZE_888; | |
2232 | break; | |
2233 | ||
2234 | default: | |
c31efa7a TR |
2235 | WARN(1, "%u bits-per-color not supported\n", state->bpc); |
2236 | value |= BASE_COLOR_SIZE_888; | |
459cc2c6 TR |
2237 | break; |
2238 | } | |
2239 | ||
2240 | tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); | |
2241 | ||
2242 | err = tegra_sor_power_up(sor, 250); | |
2243 | if (err < 0) | |
2244 | dev_err(sor->dev, "failed to power up SOR: %d\n", err); | |
2245 | ||
2bd1dd39 | 2246 | /* configure dynamic range of output */ |
459cc2c6 TR |
2247 | value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); |
2248 | value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; | |
2249 | value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; | |
2250 | tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); | |
2251 | ||
2bd1dd39 | 2252 | /* configure colorspace */ |
459cc2c6 TR |
2253 | value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); |
2254 | value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; | |
2255 | value |= SOR_HEAD_STATE_COLORSPACE_RGB; | |
2256 | tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); | |
2257 | ||
c31efa7a | 2258 | tegra_sor_mode_set(sor, mode, state); |
459cc2c6 TR |
2259 | |
2260 | tegra_sor_update(sor); | |
2261 | ||
2262 | err = tegra_sor_attach(sor); | |
2263 | if (err < 0) | |
2264 | dev_err(sor->dev, "failed to attach SOR: %d\n", err); | |
2265 | ||
2266 | /* enable display to SOR clock and generate HDMI preamble */ | |
2267 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
2268 | value |= SOR1_ENABLE | SOR1_TIMING_CYA; | |
2269 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
2270 | ||
2271 | tegra_dc_commit(dc); | |
2272 | ||
2273 | err = tegra_sor_wakeup(sor); | |
2274 | if (err < 0) | |
2275 | dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); | |
2276 | } | |
2277 | ||
2278 | static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = { | |
2279 | .disable = tegra_sor_hdmi_disable, | |
2280 | .enable = tegra_sor_hdmi_enable, | |
2281 | .atomic_check = tegra_sor_encoder_atomic_check, | |
2282 | }; | |
2283 | ||
6b6b6042 TR |
2284 | static int tegra_sor_init(struct host1x_client *client) |
2285 | { | |
9910f5c4 | 2286 | struct drm_device *drm = dev_get_drvdata(client->parent); |
459cc2c6 | 2287 | const struct drm_encoder_helper_funcs *helpers = NULL; |
6b6b6042 | 2288 | struct tegra_sor *sor = host1x_client_to_sor(client); |
459cc2c6 TR |
2289 | int connector = DRM_MODE_CONNECTOR_Unknown; |
2290 | int encoder = DRM_MODE_ENCODER_NONE; | |
6b6b6042 TR |
2291 | int err; |
2292 | ||
9542c237 | 2293 | if (!sor->aux) { |
459cc2c6 TR |
2294 | if (sor->soc->supports_hdmi) { |
2295 | connector = DRM_MODE_CONNECTOR_HDMIA; | |
2296 | encoder = DRM_MODE_ENCODER_TMDS; | |
2297 | helpers = &tegra_sor_hdmi_helpers; | |
2298 | } else if (sor->soc->supports_lvds) { | |
2299 | connector = DRM_MODE_CONNECTOR_LVDS; | |
2300 | encoder = DRM_MODE_ENCODER_LVDS; | |
2301 | } | |
2302 | } else { | |
2303 | if (sor->soc->supports_edp) { | |
2304 | connector = DRM_MODE_CONNECTOR_eDP; | |
2305 | encoder = DRM_MODE_ENCODER_TMDS; | |
2306 | helpers = &tegra_sor_edp_helpers; | |
2307 | } else if (sor->soc->supports_dp) { | |
2308 | connector = DRM_MODE_CONNECTOR_DisplayPort; | |
2309 | encoder = DRM_MODE_ENCODER_TMDS; | |
2310 | } | |
2311 | } | |
6b6b6042 | 2312 | |
6b6b6042 | 2313 | sor->output.dev = sor->dev; |
6b6b6042 | 2314 | |
6fad8f66 TR |
2315 | drm_connector_init(drm, &sor->output.connector, |
2316 | &tegra_sor_connector_funcs, | |
459cc2c6 | 2317 | connector); |
6fad8f66 TR |
2318 | drm_connector_helper_add(&sor->output.connector, |
2319 | &tegra_sor_connector_helper_funcs); | |
2320 | sor->output.connector.dpms = DRM_MODE_DPMS_OFF; | |
2321 | ||
6fad8f66 | 2322 | drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs, |
13a3d91f | 2323 | encoder, NULL); |
459cc2c6 | 2324 | drm_encoder_helper_add(&sor->output.encoder, helpers); |
6fad8f66 TR |
2325 | |
2326 | drm_mode_connector_attach_encoder(&sor->output.connector, | |
2327 | &sor->output.encoder); | |
2328 | drm_connector_register(&sor->output.connector); | |
2329 | ||
ea130b24 TR |
2330 | err = tegra_output_init(drm, &sor->output); |
2331 | if (err < 0) { | |
2332 | dev_err(client->dev, "failed to initialize output: %d\n", err); | |
2333 | return err; | |
2334 | } | |
6fad8f66 | 2335 | |
ea130b24 | 2336 | sor->output.encoder.possible_crtcs = 0x3; |
6b6b6042 | 2337 | |
a82752e1 | 2338 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
1b0c7b48 | 2339 | err = tegra_sor_debugfs_init(sor, drm->primary); |
a82752e1 TR |
2340 | if (err < 0) |
2341 | dev_err(sor->dev, "debugfs setup failed: %d\n", err); | |
2342 | } | |
2343 | ||
9542c237 TR |
2344 | if (sor->aux) { |
2345 | err = drm_dp_aux_attach(sor->aux, &sor->output); | |
6b6b6042 TR |
2346 | if (err < 0) { |
2347 | dev_err(sor->dev, "failed to attach DP: %d\n", err); | |
2348 | return err; | |
2349 | } | |
2350 | } | |
2351 | ||
535a65db TV |
2352 | /* |
2353 | * XXX: Remove this reset once proper hand-over from firmware to | |
2354 | * kernel is possible. | |
2355 | */ | |
f8c79120 JH |
2356 | if (sor->rst) { |
2357 | err = reset_control_assert(sor->rst); | |
2358 | if (err < 0) { | |
2359 | dev_err(sor->dev, "failed to assert SOR reset: %d\n", | |
2360 | err); | |
2361 | return err; | |
2362 | } | |
535a65db TV |
2363 | } |
2364 | ||
6fad8f66 TR |
2365 | err = clk_prepare_enable(sor->clk); |
2366 | if (err < 0) { | |
2367 | dev_err(sor->dev, "failed to enable clock: %d\n", err); | |
2368 | return err; | |
2369 | } | |
2370 | ||
535a65db TV |
2371 | usleep_range(1000, 3000); |
2372 | ||
f8c79120 JH |
2373 | if (sor->rst) { |
2374 | err = reset_control_deassert(sor->rst); | |
2375 | if (err < 0) { | |
2376 | dev_err(sor->dev, "failed to deassert SOR reset: %d\n", | |
2377 | err); | |
2378 | return err; | |
2379 | } | |
535a65db TV |
2380 | } |
2381 | ||
6fad8f66 TR |
2382 | err = clk_prepare_enable(sor->clk_safe); |
2383 | if (err < 0) | |
2384 | return err; | |
2385 | ||
2386 | err = clk_prepare_enable(sor->clk_dp); | |
2387 | if (err < 0) | |
2388 | return err; | |
2389 | ||
6b6b6042 TR |
2390 | return 0; |
2391 | } | |
2392 | ||
2393 | static int tegra_sor_exit(struct host1x_client *client) | |
2394 | { | |
2395 | struct tegra_sor *sor = host1x_client_to_sor(client); | |
2396 | int err; | |
2397 | ||
328ec69e TR |
2398 | tegra_output_exit(&sor->output); |
2399 | ||
9542c237 TR |
2400 | if (sor->aux) { |
2401 | err = drm_dp_aux_detach(sor->aux); | |
6b6b6042 TR |
2402 | if (err < 0) { |
2403 | dev_err(sor->dev, "failed to detach DP: %d\n", err); | |
2404 | return err; | |
2405 | } | |
2406 | } | |
2407 | ||
6fad8f66 TR |
2408 | clk_disable_unprepare(sor->clk_safe); |
2409 | clk_disable_unprepare(sor->clk_dp); | |
2410 | clk_disable_unprepare(sor->clk); | |
2411 | ||
4009c224 TR |
2412 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
2413 | tegra_sor_debugfs_exit(sor); | |
a82752e1 | 2414 | |
6b6b6042 TR |
2415 | return 0; |
2416 | } | |
2417 | ||
2418 | static const struct host1x_client_ops sor_client_ops = { | |
2419 | .init = tegra_sor_init, | |
2420 | .exit = tegra_sor_exit, | |
2421 | }; | |
2422 | ||
459cc2c6 TR |
2423 | static const struct tegra_sor_ops tegra_sor_edp_ops = { |
2424 | .name = "eDP", | |
2425 | }; | |
2426 | ||
2427 | static int tegra_sor_hdmi_probe(struct tegra_sor *sor) | |
2428 | { | |
2429 | int err; | |
2430 | ||
2431 | sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io"); | |
2432 | if (IS_ERR(sor->avdd_io_supply)) { | |
2433 | dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n", | |
2434 | PTR_ERR(sor->avdd_io_supply)); | |
2435 | return PTR_ERR(sor->avdd_io_supply); | |
2436 | } | |
2437 | ||
2438 | err = regulator_enable(sor->avdd_io_supply); | |
2439 | if (err < 0) { | |
2440 | dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", | |
2441 | err); | |
2442 | return err; | |
2443 | } | |
2444 | ||
2445 | sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll"); | |
2446 | if (IS_ERR(sor->vdd_pll_supply)) { | |
2447 | dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n", | |
2448 | PTR_ERR(sor->vdd_pll_supply)); | |
2449 | return PTR_ERR(sor->vdd_pll_supply); | |
2450 | } | |
2451 | ||
2452 | err = regulator_enable(sor->vdd_pll_supply); | |
2453 | if (err < 0) { | |
2454 | dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", | |
2455 | err); | |
2456 | return err; | |
2457 | } | |
2458 | ||
2459 | sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); | |
2460 | if (IS_ERR(sor->hdmi_supply)) { | |
2461 | dev_err(sor->dev, "cannot get HDMI supply: %ld\n", | |
2462 | PTR_ERR(sor->hdmi_supply)); | |
2463 | return PTR_ERR(sor->hdmi_supply); | |
2464 | } | |
2465 | ||
2466 | err = regulator_enable(sor->hdmi_supply); | |
2467 | if (err < 0) { | |
2468 | dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); | |
2469 | return err; | |
2470 | } | |
2471 | ||
2472 | return 0; | |
2473 | } | |
2474 | ||
2475 | static int tegra_sor_hdmi_remove(struct tegra_sor *sor) | |
2476 | { | |
2477 | regulator_disable(sor->hdmi_supply); | |
2478 | regulator_disable(sor->vdd_pll_supply); | |
2479 | regulator_disable(sor->avdd_io_supply); | |
2480 | ||
2481 | return 0; | |
2482 | } | |
2483 | ||
2484 | static const struct tegra_sor_ops tegra_sor_hdmi_ops = { | |
2485 | .name = "HDMI", | |
2486 | .probe = tegra_sor_hdmi_probe, | |
2487 | .remove = tegra_sor_hdmi_remove, | |
2488 | }; | |
2489 | ||
30b49435 TR |
2490 | static const u8 tegra124_sor_xbar_cfg[5] = { |
2491 | 0, 1, 2, 3, 4 | |
2492 | }; | |
2493 | ||
459cc2c6 TR |
2494 | static const struct tegra_sor_soc tegra124_sor = { |
2495 | .supports_edp = true, | |
2496 | .supports_lvds = true, | |
2497 | .supports_hdmi = false, | |
2498 | .supports_dp = false, | |
30b49435 | 2499 | .xbar_cfg = tegra124_sor_xbar_cfg, |
459cc2c6 TR |
2500 | }; |
2501 | ||
2502 | static const struct tegra_sor_soc tegra210_sor = { | |
2503 | .supports_edp = true, | |
2504 | .supports_lvds = false, | |
2505 | .supports_hdmi = false, | |
2506 | .supports_dp = false, | |
30b49435 TR |
2507 | .xbar_cfg = tegra124_sor_xbar_cfg, |
2508 | }; | |
2509 | ||
2510 | static const u8 tegra210_sor_xbar_cfg[5] = { | |
2511 | 2, 1, 0, 3, 4 | |
459cc2c6 TR |
2512 | }; |
2513 | ||
2514 | static const struct tegra_sor_soc tegra210_sor1 = { | |
2515 | .supports_edp = false, | |
2516 | .supports_lvds = false, | |
2517 | .supports_hdmi = true, | |
2518 | .supports_dp = true, | |
2519 | ||
2520 | .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults), | |
2521 | .settings = tegra210_sor_hdmi_defaults, | |
30b49435 TR |
2522 | |
2523 | .xbar_cfg = tegra210_sor_xbar_cfg, | |
459cc2c6 TR |
2524 | }; |
2525 | ||
2526 | static const struct of_device_id tegra_sor_of_match[] = { | |
2527 | { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 }, | |
2528 | { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor }, | |
2529 | { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor }, | |
2530 | { }, | |
2531 | }; | |
2532 | MODULE_DEVICE_TABLE(of, tegra_sor_of_match); | |
2533 | ||
6b6b6042 TR |
2534 | static int tegra_sor_probe(struct platform_device *pdev) |
2535 | { | |
459cc2c6 | 2536 | const struct of_device_id *match; |
6b6b6042 TR |
2537 | struct device_node *np; |
2538 | struct tegra_sor *sor; | |
2539 | struct resource *regs; | |
2540 | int err; | |
2541 | ||
459cc2c6 TR |
2542 | match = of_match_device(tegra_sor_of_match, &pdev->dev); |
2543 | ||
6b6b6042 TR |
2544 | sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); |
2545 | if (!sor) | |
2546 | return -ENOMEM; | |
2547 | ||
2548 | sor->output.dev = sor->dev = &pdev->dev; | |
459cc2c6 TR |
2549 | sor->soc = match->data; |
2550 | ||
2551 | sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, | |
2552 | sor->soc->num_settings * | |
2553 | sizeof(*sor->settings), | |
2554 | GFP_KERNEL); | |
2555 | if (!sor->settings) | |
2556 | return -ENOMEM; | |
2557 | ||
2558 | sor->num_settings = sor->soc->num_settings; | |
6b6b6042 TR |
2559 | |
2560 | np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); | |
2561 | if (np) { | |
9542c237 | 2562 | sor->aux = drm_dp_aux_find_by_of_node(np); |
6b6b6042 TR |
2563 | of_node_put(np); |
2564 | ||
9542c237 | 2565 | if (!sor->aux) |
6b6b6042 TR |
2566 | return -EPROBE_DEFER; |
2567 | } | |
2568 | ||
9542c237 | 2569 | if (!sor->aux) { |
459cc2c6 TR |
2570 | if (sor->soc->supports_hdmi) { |
2571 | sor->ops = &tegra_sor_hdmi_ops; | |
2572 | } else if (sor->soc->supports_lvds) { | |
2573 | dev_err(&pdev->dev, "LVDS not supported yet\n"); | |
2574 | return -ENODEV; | |
2575 | } else { | |
2576 | dev_err(&pdev->dev, "unknown (non-DP) support\n"); | |
2577 | return -ENODEV; | |
2578 | } | |
2579 | } else { | |
2580 | if (sor->soc->supports_edp) { | |
2581 | sor->ops = &tegra_sor_edp_ops; | |
2582 | } else if (sor->soc->supports_dp) { | |
2583 | dev_err(&pdev->dev, "DisplayPort not supported yet\n"); | |
2584 | return -ENODEV; | |
2585 | } else { | |
2586 | dev_err(&pdev->dev, "unknown (DP) support\n"); | |
2587 | return -ENODEV; | |
2588 | } | |
2589 | } | |
2590 | ||
6b6b6042 | 2591 | err = tegra_output_probe(&sor->output); |
4dbdc740 TR |
2592 | if (err < 0) { |
2593 | dev_err(&pdev->dev, "failed to probe output: %d\n", err); | |
6b6b6042 | 2594 | return err; |
4dbdc740 | 2595 | } |
6b6b6042 | 2596 | |
459cc2c6 TR |
2597 | if (sor->ops && sor->ops->probe) { |
2598 | err = sor->ops->probe(sor); | |
2599 | if (err < 0) { | |
2600 | dev_err(&pdev->dev, "failed to probe %s: %d\n", | |
2601 | sor->ops->name, err); | |
2602 | goto output; | |
2603 | } | |
2604 | } | |
2605 | ||
6b6b6042 TR |
2606 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2607 | sor->regs = devm_ioremap_resource(&pdev->dev, regs); | |
459cc2c6 TR |
2608 | if (IS_ERR(sor->regs)) { |
2609 | err = PTR_ERR(sor->regs); | |
2610 | goto remove; | |
2611 | } | |
6b6b6042 | 2612 | |
f8c79120 JH |
2613 | if (!pdev->dev.pm_domain) { |
2614 | sor->rst = devm_reset_control_get(&pdev->dev, "sor"); | |
2615 | if (IS_ERR(sor->rst)) { | |
2616 | err = PTR_ERR(sor->rst); | |
2617 | dev_err(&pdev->dev, "failed to get reset control: %d\n", | |
2618 | err); | |
2619 | goto remove; | |
2620 | } | |
4dbdc740 | 2621 | } |
6b6b6042 TR |
2622 | |
2623 | sor->clk = devm_clk_get(&pdev->dev, NULL); | |
4dbdc740 | 2624 | if (IS_ERR(sor->clk)) { |
459cc2c6 TR |
2625 | err = PTR_ERR(sor->clk); |
2626 | dev_err(&pdev->dev, "failed to get module clock: %d\n", err); | |
2627 | goto remove; | |
4dbdc740 | 2628 | } |
6b6b6042 | 2629 | |
618dee39 TR |
2630 | if (sor->soc->supports_hdmi || sor->soc->supports_dp) { |
2631 | sor->clk_src = devm_clk_get(&pdev->dev, "source"); | |
2632 | if (IS_ERR(sor->clk_src)) { | |
2633 | err = PTR_ERR(sor->clk_src); | |
2634 | dev_err(sor->dev, "failed to get source clock: %d\n", | |
2635 | err); | |
2636 | goto remove; | |
2637 | } | |
2638 | } | |
2639 | ||
6b6b6042 | 2640 | sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); |
4dbdc740 | 2641 | if (IS_ERR(sor->clk_parent)) { |
459cc2c6 TR |
2642 | err = PTR_ERR(sor->clk_parent); |
2643 | dev_err(&pdev->dev, "failed to get parent clock: %d\n", err); | |
2644 | goto remove; | |
4dbdc740 | 2645 | } |
6b6b6042 | 2646 | |
6b6b6042 | 2647 | sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); |
4dbdc740 | 2648 | if (IS_ERR(sor->clk_safe)) { |
459cc2c6 TR |
2649 | err = PTR_ERR(sor->clk_safe); |
2650 | dev_err(&pdev->dev, "failed to get safe clock: %d\n", err); | |
2651 | goto remove; | |
4dbdc740 | 2652 | } |
6b6b6042 | 2653 | |
6b6b6042 | 2654 | sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); |
4dbdc740 | 2655 | if (IS_ERR(sor->clk_dp)) { |
459cc2c6 TR |
2656 | err = PTR_ERR(sor->clk_dp); |
2657 | dev_err(&pdev->dev, "failed to get DP clock: %d\n", err); | |
2658 | goto remove; | |
4dbdc740 | 2659 | } |
6b6b6042 | 2660 | |
aaff8bd2 TR |
2661 | platform_set_drvdata(pdev, sor); |
2662 | pm_runtime_enable(&pdev->dev); | |
2663 | ||
b299221c TR |
2664 | pm_runtime_get_sync(&pdev->dev); |
2665 | sor->clk_brick = tegra_clk_sor_brick_register(sor, "sor1_brick"); | |
2666 | pm_runtime_put(&pdev->dev); | |
2667 | ||
2668 | if (IS_ERR(sor->clk_brick)) { | |
2669 | err = PTR_ERR(sor->clk_brick); | |
2670 | dev_err(&pdev->dev, "failed to register SOR clock: %d\n", err); | |
2671 | goto remove; | |
2672 | } | |
2673 | ||
6b6b6042 TR |
2674 | INIT_LIST_HEAD(&sor->client.list); |
2675 | sor->client.ops = &sor_client_ops; | |
2676 | sor->client.dev = &pdev->dev; | |
2677 | ||
2678 | err = host1x_client_register(&sor->client); | |
2679 | if (err < 0) { | |
2680 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", | |
2681 | err); | |
459cc2c6 | 2682 | goto remove; |
6b6b6042 TR |
2683 | } |
2684 | ||
6b6b6042 | 2685 | return 0; |
459cc2c6 TR |
2686 | |
2687 | remove: | |
2688 | if (sor->ops && sor->ops->remove) | |
2689 | sor->ops->remove(sor); | |
2690 | output: | |
2691 | tegra_output_remove(&sor->output); | |
2692 | return err; | |
6b6b6042 TR |
2693 | } |
2694 | ||
2695 | static int tegra_sor_remove(struct platform_device *pdev) | |
2696 | { | |
2697 | struct tegra_sor *sor = platform_get_drvdata(pdev); | |
2698 | int err; | |
2699 | ||
aaff8bd2 TR |
2700 | pm_runtime_disable(&pdev->dev); |
2701 | ||
6b6b6042 TR |
2702 | err = host1x_client_unregister(&sor->client); |
2703 | if (err < 0) { | |
2704 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", | |
2705 | err); | |
2706 | return err; | |
2707 | } | |
2708 | ||
459cc2c6 TR |
2709 | if (sor->ops && sor->ops->remove) { |
2710 | err = sor->ops->remove(sor); | |
2711 | if (err < 0) | |
2712 | dev_err(&pdev->dev, "failed to remove SOR: %d\n", err); | |
2713 | } | |
2714 | ||
328ec69e | 2715 | tegra_output_remove(&sor->output); |
6b6b6042 TR |
2716 | |
2717 | return 0; | |
2718 | } | |
2719 | ||
aaff8bd2 TR |
2720 | #ifdef CONFIG_PM |
2721 | static int tegra_sor_suspend(struct device *dev) | |
2722 | { | |
2723 | struct tegra_sor *sor = dev_get_drvdata(dev); | |
2724 | int err; | |
2725 | ||
f8c79120 JH |
2726 | if (sor->rst) { |
2727 | err = reset_control_assert(sor->rst); | |
2728 | if (err < 0) { | |
2729 | dev_err(dev, "failed to assert reset: %d\n", err); | |
2730 | return err; | |
2731 | } | |
aaff8bd2 TR |
2732 | } |
2733 | ||
2734 | usleep_range(1000, 2000); | |
2735 | ||
2736 | clk_disable_unprepare(sor->clk); | |
2737 | ||
2738 | return 0; | |
2739 | } | |
2740 | ||
2741 | static int tegra_sor_resume(struct device *dev) | |
2742 | { | |
2743 | struct tegra_sor *sor = dev_get_drvdata(dev); | |
2744 | int err; | |
2745 | ||
2746 | err = clk_prepare_enable(sor->clk); | |
2747 | if (err < 0) { | |
2748 | dev_err(dev, "failed to enable clock: %d\n", err); | |
2749 | return err; | |
2750 | } | |
2751 | ||
2752 | usleep_range(1000, 2000); | |
2753 | ||
f8c79120 JH |
2754 | if (sor->rst) { |
2755 | err = reset_control_deassert(sor->rst); | |
2756 | if (err < 0) { | |
2757 | dev_err(dev, "failed to deassert reset: %d\n", err); | |
2758 | clk_disable_unprepare(sor->clk); | |
2759 | return err; | |
2760 | } | |
aaff8bd2 TR |
2761 | } |
2762 | ||
2763 | return 0; | |
2764 | } | |
2765 | #endif | |
2766 | ||
2767 | static const struct dev_pm_ops tegra_sor_pm_ops = { | |
2768 | SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL) | |
2769 | }; | |
2770 | ||
6b6b6042 TR |
2771 | struct platform_driver tegra_sor_driver = { |
2772 | .driver = { | |
2773 | .name = "tegra-sor", | |
2774 | .of_match_table = tegra_sor_of_match, | |
aaff8bd2 | 2775 | .pm = &tegra_sor_pm_ops, |
6b6b6042 TR |
2776 | }, |
2777 | .probe = tegra_sor_probe, | |
2778 | .remove = tegra_sor_remove, | |
2779 | }; |