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d5b1a78a EA |
1 | /* |
2 | * Copyright © 2014 Broadcom | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/io.h> | |
28 | ||
29 | #include "uapi/drm/vc4_drm.h" | |
30 | #include "vc4_drv.h" | |
31 | #include "vc4_regs.h" | |
32 | #include "vc4_trace.h" | |
33 | ||
34 | static void | |
35 | vc4_queue_hangcheck(struct drm_device *dev) | |
36 | { | |
37 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
38 | ||
39 | mod_timer(&vc4->hangcheck.timer, | |
40 | round_jiffies_up(jiffies + msecs_to_jiffies(100))); | |
41 | } | |
42 | ||
21461365 EA |
43 | struct vc4_hang_state { |
44 | struct drm_vc4_get_hang_state user_state; | |
45 | ||
46 | u32 bo_count; | |
47 | struct drm_gem_object **bo; | |
48 | }; | |
49 | ||
50 | static void | |
51 | vc4_free_hang_state(struct drm_device *dev, struct vc4_hang_state *state) | |
52 | { | |
53 | unsigned int i; | |
54 | ||
55 | mutex_lock(&dev->struct_mutex); | |
56 | for (i = 0; i < state->user_state.bo_count; i++) | |
57 | drm_gem_object_unreference(state->bo[i]); | |
58 | mutex_unlock(&dev->struct_mutex); | |
59 | ||
60 | kfree(state); | |
61 | } | |
62 | ||
63 | int | |
64 | vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, | |
65 | struct drm_file *file_priv) | |
66 | { | |
67 | struct drm_vc4_get_hang_state *get_state = data; | |
68 | struct drm_vc4_get_hang_state_bo *bo_state; | |
69 | struct vc4_hang_state *kernel_state; | |
70 | struct drm_vc4_get_hang_state *state; | |
71 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
72 | unsigned long irqflags; | |
73 | u32 i; | |
65c4777d | 74 | int ret = 0; |
21461365 EA |
75 | |
76 | spin_lock_irqsave(&vc4->job_lock, irqflags); | |
77 | kernel_state = vc4->hang_state; | |
78 | if (!kernel_state) { | |
79 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
80 | return -ENOENT; | |
81 | } | |
82 | state = &kernel_state->user_state; | |
83 | ||
84 | /* If the user's array isn't big enough, just return the | |
85 | * required array size. | |
86 | */ | |
87 | if (get_state->bo_count < state->bo_count) { | |
88 | get_state->bo_count = state->bo_count; | |
89 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
90 | return 0; | |
91 | } | |
92 | ||
93 | vc4->hang_state = NULL; | |
94 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
95 | ||
96 | /* Save the user's BO pointer, so we don't stomp it with the memcpy. */ | |
97 | state->bo = get_state->bo; | |
98 | memcpy(get_state, state, sizeof(*state)); | |
99 | ||
100 | bo_state = kcalloc(state->bo_count, sizeof(*bo_state), GFP_KERNEL); | |
101 | if (!bo_state) { | |
102 | ret = -ENOMEM; | |
103 | goto err_free; | |
104 | } | |
105 | ||
106 | for (i = 0; i < state->bo_count; i++) { | |
107 | struct vc4_bo *vc4_bo = to_vc4_bo(kernel_state->bo[i]); | |
108 | u32 handle; | |
109 | ||
110 | ret = drm_gem_handle_create(file_priv, kernel_state->bo[i], | |
111 | &handle); | |
112 | ||
113 | if (ret) { | |
114 | state->bo_count = i - 1; | |
115 | goto err; | |
116 | } | |
117 | bo_state[i].handle = handle; | |
118 | bo_state[i].paddr = vc4_bo->base.paddr; | |
119 | bo_state[i].size = vc4_bo->base.base.size; | |
120 | } | |
121 | ||
65c4777d DC |
122 | if (copy_to_user((void __user *)(uintptr_t)get_state->bo, |
123 | bo_state, | |
124 | state->bo_count * sizeof(*bo_state))) | |
125 | ret = -EFAULT; | |
126 | ||
21461365 EA |
127 | kfree(bo_state); |
128 | ||
129 | err_free: | |
130 | ||
131 | vc4_free_hang_state(dev, kernel_state); | |
132 | ||
133 | err: | |
134 | return ret; | |
135 | } | |
136 | ||
137 | static void | |
138 | vc4_save_hang_state(struct drm_device *dev) | |
139 | { | |
140 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
141 | struct drm_vc4_get_hang_state *state; | |
142 | struct vc4_hang_state *kernel_state; | |
143 | struct vc4_exec_info *exec; | |
144 | struct vc4_bo *bo; | |
145 | unsigned long irqflags; | |
146 | unsigned int i, unref_list_count; | |
147 | ||
7e5082fb | 148 | kernel_state = kcalloc(1, sizeof(*kernel_state), GFP_KERNEL); |
21461365 EA |
149 | if (!kernel_state) |
150 | return; | |
151 | ||
152 | state = &kernel_state->user_state; | |
153 | ||
154 | spin_lock_irqsave(&vc4->job_lock, irqflags); | |
155 | exec = vc4_first_job(vc4); | |
156 | if (!exec) { | |
157 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
158 | return; | |
159 | } | |
160 | ||
161 | unref_list_count = 0; | |
162 | list_for_each_entry(bo, &exec->unref_list, unref_head) | |
163 | unref_list_count++; | |
164 | ||
165 | state->bo_count = exec->bo_count + unref_list_count; | |
166 | kernel_state->bo = kcalloc(state->bo_count, sizeof(*kernel_state->bo), | |
167 | GFP_ATOMIC); | |
168 | if (!kernel_state->bo) { | |
169 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
170 | return; | |
171 | } | |
172 | ||
173 | for (i = 0; i < exec->bo_count; i++) { | |
174 | drm_gem_object_reference(&exec->bo[i]->base); | |
175 | kernel_state->bo[i] = &exec->bo[i]->base; | |
176 | } | |
177 | ||
178 | list_for_each_entry(bo, &exec->unref_list, unref_head) { | |
179 | drm_gem_object_reference(&bo->base.base); | |
180 | kernel_state->bo[i] = &bo->base.base; | |
181 | i++; | |
182 | } | |
183 | ||
184 | state->start_bin = exec->ct0ca; | |
185 | state->start_render = exec->ct1ca; | |
186 | ||
187 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
188 | ||
189 | state->ct0ca = V3D_READ(V3D_CTNCA(0)); | |
190 | state->ct0ea = V3D_READ(V3D_CTNEA(0)); | |
191 | ||
192 | state->ct1ca = V3D_READ(V3D_CTNCA(1)); | |
193 | state->ct1ea = V3D_READ(V3D_CTNEA(1)); | |
194 | ||
195 | state->ct0cs = V3D_READ(V3D_CTNCS(0)); | |
196 | state->ct1cs = V3D_READ(V3D_CTNCS(1)); | |
197 | ||
198 | state->ct0ra0 = V3D_READ(V3D_CT00RA0); | |
199 | state->ct1ra0 = V3D_READ(V3D_CT01RA0); | |
200 | ||
201 | state->bpca = V3D_READ(V3D_BPCA); | |
202 | state->bpcs = V3D_READ(V3D_BPCS); | |
203 | state->bpoa = V3D_READ(V3D_BPOA); | |
204 | state->bpos = V3D_READ(V3D_BPOS); | |
205 | ||
206 | state->vpmbase = V3D_READ(V3D_VPMBASE); | |
207 | ||
208 | state->dbge = V3D_READ(V3D_DBGE); | |
209 | state->fdbgo = V3D_READ(V3D_FDBGO); | |
210 | state->fdbgb = V3D_READ(V3D_FDBGB); | |
211 | state->fdbgr = V3D_READ(V3D_FDBGR); | |
212 | state->fdbgs = V3D_READ(V3D_FDBGS); | |
213 | state->errstat = V3D_READ(V3D_ERRSTAT); | |
214 | ||
215 | spin_lock_irqsave(&vc4->job_lock, irqflags); | |
216 | if (vc4->hang_state) { | |
217 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
218 | vc4_free_hang_state(dev, kernel_state); | |
219 | } else { | |
220 | vc4->hang_state = kernel_state; | |
221 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
222 | } | |
223 | } | |
224 | ||
d5b1a78a EA |
225 | static void |
226 | vc4_reset(struct drm_device *dev) | |
227 | { | |
228 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
229 | ||
230 | DRM_INFO("Resetting GPU.\n"); | |
231 | vc4_v3d_set_power(vc4, false); | |
232 | vc4_v3d_set_power(vc4, true); | |
233 | ||
234 | vc4_irq_reset(dev); | |
235 | ||
236 | /* Rearm the hangcheck -- another job might have been waiting | |
237 | * for our hung one to get kicked off, and vc4_irq_reset() | |
238 | * would have started it. | |
239 | */ | |
240 | vc4_queue_hangcheck(dev); | |
241 | } | |
242 | ||
243 | static void | |
244 | vc4_reset_work(struct work_struct *work) | |
245 | { | |
246 | struct vc4_dev *vc4 = | |
247 | container_of(work, struct vc4_dev, hangcheck.reset_work); | |
248 | ||
21461365 EA |
249 | vc4_save_hang_state(vc4->dev); |
250 | ||
d5b1a78a EA |
251 | vc4_reset(vc4->dev); |
252 | } | |
253 | ||
254 | static void | |
255 | vc4_hangcheck_elapsed(unsigned long data) | |
256 | { | |
257 | struct drm_device *dev = (struct drm_device *)data; | |
258 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
259 | uint32_t ct0ca, ct1ca; | |
c4ce60dc EA |
260 | unsigned long irqflags; |
261 | struct vc4_exec_info *exec; | |
262 | ||
263 | spin_lock_irqsave(&vc4->job_lock, irqflags); | |
264 | exec = vc4_first_job(vc4); | |
d5b1a78a EA |
265 | |
266 | /* If idle, we can stop watching for hangs. */ | |
c4ce60dc EA |
267 | if (!exec) { |
268 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
d5b1a78a | 269 | return; |
c4ce60dc | 270 | } |
d5b1a78a EA |
271 | |
272 | ct0ca = V3D_READ(V3D_CTNCA(0)); | |
273 | ct1ca = V3D_READ(V3D_CTNCA(1)); | |
274 | ||
275 | /* If we've made any progress in execution, rearm the timer | |
276 | * and wait. | |
277 | */ | |
c4ce60dc EA |
278 | if (ct0ca != exec->last_ct0ca || ct1ca != exec->last_ct1ca) { |
279 | exec->last_ct0ca = ct0ca; | |
280 | exec->last_ct1ca = ct1ca; | |
281 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
d5b1a78a EA |
282 | vc4_queue_hangcheck(dev); |
283 | return; | |
284 | } | |
285 | ||
c4ce60dc EA |
286 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); |
287 | ||
d5b1a78a EA |
288 | /* We've gone too long with no progress, reset. This has to |
289 | * be done from a work struct, since resetting can sleep and | |
290 | * this timer hook isn't allowed to. | |
291 | */ | |
292 | schedule_work(&vc4->hangcheck.reset_work); | |
293 | } | |
294 | ||
295 | static void | |
296 | submit_cl(struct drm_device *dev, uint32_t thread, uint32_t start, uint32_t end) | |
297 | { | |
298 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
299 | ||
300 | /* Set the current and end address of the control list. | |
301 | * Writing the end register is what starts the job. | |
302 | */ | |
303 | V3D_WRITE(V3D_CTNCA(thread), start); | |
304 | V3D_WRITE(V3D_CTNEA(thread), end); | |
305 | } | |
306 | ||
307 | int | |
308 | vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, uint64_t timeout_ns, | |
309 | bool interruptible) | |
310 | { | |
311 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
312 | int ret = 0; | |
313 | unsigned long timeout_expire; | |
314 | DEFINE_WAIT(wait); | |
315 | ||
316 | if (vc4->finished_seqno >= seqno) | |
317 | return 0; | |
318 | ||
319 | if (timeout_ns == 0) | |
320 | return -ETIME; | |
321 | ||
322 | timeout_expire = jiffies + nsecs_to_jiffies(timeout_ns); | |
323 | ||
324 | trace_vc4_wait_for_seqno_begin(dev, seqno, timeout_ns); | |
325 | for (;;) { | |
326 | prepare_to_wait(&vc4->job_wait_queue, &wait, | |
327 | interruptible ? TASK_INTERRUPTIBLE : | |
328 | TASK_UNINTERRUPTIBLE); | |
329 | ||
330 | if (interruptible && signal_pending(current)) { | |
331 | ret = -ERESTARTSYS; | |
332 | break; | |
333 | } | |
334 | ||
335 | if (vc4->finished_seqno >= seqno) | |
336 | break; | |
337 | ||
338 | if (timeout_ns != ~0ull) { | |
339 | if (time_after_eq(jiffies, timeout_expire)) { | |
340 | ret = -ETIME; | |
341 | break; | |
342 | } | |
343 | schedule_timeout(timeout_expire - jiffies); | |
344 | } else { | |
345 | schedule(); | |
346 | } | |
347 | } | |
348 | ||
349 | finish_wait(&vc4->job_wait_queue, &wait); | |
350 | trace_vc4_wait_for_seqno_end(dev, seqno); | |
351 | ||
13cf8909 | 352 | return ret; |
d5b1a78a EA |
353 | } |
354 | ||
355 | static void | |
356 | vc4_flush_caches(struct drm_device *dev) | |
357 | { | |
358 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
359 | ||
360 | /* Flush the GPU L2 caches. These caches sit on top of system | |
361 | * L3 (the 128kb or so shared with the CPU), and are | |
362 | * non-allocating in the L3. | |
363 | */ | |
364 | V3D_WRITE(V3D_L2CACTL, | |
365 | V3D_L2CACTL_L2CCLR); | |
366 | ||
367 | V3D_WRITE(V3D_SLCACTL, | |
368 | VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | | |
369 | VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) | | |
370 | VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) | | |
371 | VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC)); | |
372 | } | |
373 | ||
374 | /* Sets the registers for the next job to be actually be executed in | |
375 | * the hardware. | |
376 | * | |
377 | * The job_lock should be held during this. | |
378 | */ | |
379 | void | |
380 | vc4_submit_next_job(struct drm_device *dev) | |
381 | { | |
382 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
383 | struct vc4_exec_info *exec = vc4_first_job(vc4); | |
384 | ||
385 | if (!exec) | |
386 | return; | |
387 | ||
388 | vc4_flush_caches(dev); | |
389 | ||
390 | /* Disable the binner's pre-loaded overflow memory address */ | |
391 | V3D_WRITE(V3D_BPOA, 0); | |
392 | V3D_WRITE(V3D_BPOS, 0); | |
393 | ||
394 | if (exec->ct0ca != exec->ct0ea) | |
395 | submit_cl(dev, 0, exec->ct0ca, exec->ct0ea); | |
396 | submit_cl(dev, 1, exec->ct1ca, exec->ct1ea); | |
397 | } | |
398 | ||
399 | static void | |
400 | vc4_update_bo_seqnos(struct vc4_exec_info *exec, uint64_t seqno) | |
401 | { | |
402 | struct vc4_bo *bo; | |
403 | unsigned i; | |
404 | ||
405 | for (i = 0; i < exec->bo_count; i++) { | |
406 | bo = to_vc4_bo(&exec->bo[i]->base); | |
407 | bo->seqno = seqno; | |
408 | } | |
409 | ||
410 | list_for_each_entry(bo, &exec->unref_list, unref_head) { | |
411 | bo->seqno = seqno; | |
412 | } | |
413 | } | |
414 | ||
415 | /* Queues a struct vc4_exec_info for execution. If no job is | |
416 | * currently executing, then submits it. | |
417 | * | |
418 | * Unlike most GPUs, our hardware only handles one command list at a | |
419 | * time. To queue multiple jobs at once, we'd need to edit the | |
420 | * previous command list to have a jump to the new one at the end, and | |
421 | * then bump the end address. That's a change for a later date, | |
422 | * though. | |
423 | */ | |
424 | static void | |
425 | vc4_queue_submit(struct drm_device *dev, struct vc4_exec_info *exec) | |
426 | { | |
427 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
428 | uint64_t seqno; | |
429 | unsigned long irqflags; | |
430 | ||
431 | spin_lock_irqsave(&vc4->job_lock, irqflags); | |
432 | ||
433 | seqno = ++vc4->emit_seqno; | |
434 | exec->seqno = seqno; | |
435 | vc4_update_bo_seqnos(exec, seqno); | |
436 | ||
437 | list_add_tail(&exec->head, &vc4->job_list); | |
438 | ||
439 | /* If no job was executing, kick ours off. Otherwise, it'll | |
440 | * get started when the previous job's frame done interrupt | |
441 | * occurs. | |
442 | */ | |
443 | if (vc4_first_job(vc4) == exec) { | |
444 | vc4_submit_next_job(dev); | |
445 | vc4_queue_hangcheck(dev); | |
446 | } | |
447 | ||
448 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
449 | } | |
450 | ||
451 | /** | |
452 | * Looks up a bunch of GEM handles for BOs and stores the array for | |
453 | * use in the command validator that actually writes relocated | |
454 | * addresses pointing to them. | |
455 | */ | |
456 | static int | |
457 | vc4_cl_lookup_bos(struct drm_device *dev, | |
458 | struct drm_file *file_priv, | |
459 | struct vc4_exec_info *exec) | |
460 | { | |
461 | struct drm_vc4_submit_cl *args = exec->args; | |
462 | uint32_t *handles; | |
463 | int ret = 0; | |
464 | int i; | |
465 | ||
466 | exec->bo_count = args->bo_handle_count; | |
467 | ||
468 | if (!exec->bo_count) { | |
469 | /* See comment on bo_index for why we have to check | |
470 | * this. | |
471 | */ | |
472 | DRM_ERROR("Rendering requires BOs to validate\n"); | |
473 | return -EINVAL; | |
474 | } | |
475 | ||
476 | exec->bo = kcalloc(exec->bo_count, sizeof(struct drm_gem_cma_object *), | |
477 | GFP_KERNEL); | |
478 | if (!exec->bo) { | |
479 | DRM_ERROR("Failed to allocate validated BO pointers\n"); | |
480 | return -ENOMEM; | |
481 | } | |
482 | ||
483 | handles = drm_malloc_ab(exec->bo_count, sizeof(uint32_t)); | |
484 | if (!handles) { | |
485 | DRM_ERROR("Failed to allocate incoming GEM handles\n"); | |
486 | goto fail; | |
487 | } | |
488 | ||
489 | ret = copy_from_user(handles, | |
490 | (void __user *)(uintptr_t)args->bo_handles, | |
491 | exec->bo_count * sizeof(uint32_t)); | |
492 | if (ret) { | |
493 | DRM_ERROR("Failed to copy in GEM handles\n"); | |
494 | goto fail; | |
495 | } | |
496 | ||
497 | spin_lock(&file_priv->table_lock); | |
498 | for (i = 0; i < exec->bo_count; i++) { | |
499 | struct drm_gem_object *bo = idr_find(&file_priv->object_idr, | |
500 | handles[i]); | |
501 | if (!bo) { | |
502 | DRM_ERROR("Failed to look up GEM BO %d: %d\n", | |
503 | i, handles[i]); | |
504 | ret = -EINVAL; | |
505 | spin_unlock(&file_priv->table_lock); | |
506 | goto fail; | |
507 | } | |
508 | drm_gem_object_reference(bo); | |
509 | exec->bo[i] = (struct drm_gem_cma_object *)bo; | |
510 | } | |
511 | spin_unlock(&file_priv->table_lock); | |
512 | ||
513 | fail: | |
514 | kfree(handles); | |
515 | return 0; | |
516 | } | |
517 | ||
518 | static int | |
519 | vc4_get_bcl(struct drm_device *dev, struct vc4_exec_info *exec) | |
520 | { | |
521 | struct drm_vc4_submit_cl *args = exec->args; | |
522 | void *temp = NULL; | |
523 | void *bin; | |
524 | int ret = 0; | |
525 | uint32_t bin_offset = 0; | |
526 | uint32_t shader_rec_offset = roundup(bin_offset + args->bin_cl_size, | |
527 | 16); | |
528 | uint32_t uniforms_offset = shader_rec_offset + args->shader_rec_size; | |
529 | uint32_t exec_size = uniforms_offset + args->uniforms_size; | |
530 | uint32_t temp_size = exec_size + (sizeof(struct vc4_shader_state) * | |
531 | args->shader_rec_count); | |
532 | struct vc4_bo *bo; | |
533 | ||
534 | if (uniforms_offset < shader_rec_offset || | |
535 | exec_size < uniforms_offset || | |
536 | args->shader_rec_count >= (UINT_MAX / | |
537 | sizeof(struct vc4_shader_state)) || | |
538 | temp_size < exec_size) { | |
539 | DRM_ERROR("overflow in exec arguments\n"); | |
540 | goto fail; | |
541 | } | |
542 | ||
543 | /* Allocate space where we'll store the copied in user command lists | |
544 | * and shader records. | |
545 | * | |
546 | * We don't just copy directly into the BOs because we need to | |
547 | * read the contents back for validation, and I think the | |
548 | * bo->vaddr is uncached access. | |
549 | */ | |
550 | temp = kmalloc(temp_size, GFP_KERNEL); | |
551 | if (!temp) { | |
552 | DRM_ERROR("Failed to allocate storage for copying " | |
553 | "in bin/render CLs.\n"); | |
554 | ret = -ENOMEM; | |
555 | goto fail; | |
556 | } | |
557 | bin = temp + bin_offset; | |
558 | exec->shader_rec_u = temp + shader_rec_offset; | |
559 | exec->uniforms_u = temp + uniforms_offset; | |
560 | exec->shader_state = temp + exec_size; | |
561 | exec->shader_state_size = args->shader_rec_count; | |
562 | ||
65c4777d DC |
563 | if (copy_from_user(bin, |
564 | (void __user *)(uintptr_t)args->bin_cl, | |
565 | args->bin_cl_size)) { | |
566 | ret = -EFAULT; | |
d5b1a78a EA |
567 | goto fail; |
568 | } | |
569 | ||
65c4777d DC |
570 | if (copy_from_user(exec->shader_rec_u, |
571 | (void __user *)(uintptr_t)args->shader_rec, | |
572 | args->shader_rec_size)) { | |
573 | ret = -EFAULT; | |
d5b1a78a EA |
574 | goto fail; |
575 | } | |
576 | ||
65c4777d DC |
577 | if (copy_from_user(exec->uniforms_u, |
578 | (void __user *)(uintptr_t)args->uniforms, | |
579 | args->uniforms_size)) { | |
580 | ret = -EFAULT; | |
d5b1a78a EA |
581 | goto fail; |
582 | } | |
583 | ||
584 | bo = vc4_bo_create(dev, exec_size, true); | |
2c68f1fc | 585 | if (IS_ERR(bo)) { |
d5b1a78a | 586 | DRM_ERROR("Couldn't allocate BO for binning\n"); |
2c68f1fc | 587 | ret = PTR_ERR(bo); |
d5b1a78a EA |
588 | goto fail; |
589 | } | |
590 | exec->exec_bo = &bo->base; | |
591 | ||
592 | list_add_tail(&to_vc4_bo(&exec->exec_bo->base)->unref_head, | |
593 | &exec->unref_list); | |
594 | ||
595 | exec->ct0ca = exec->exec_bo->paddr + bin_offset; | |
596 | ||
597 | exec->bin_u = bin; | |
598 | ||
599 | exec->shader_rec_v = exec->exec_bo->vaddr + shader_rec_offset; | |
600 | exec->shader_rec_p = exec->exec_bo->paddr + shader_rec_offset; | |
601 | exec->shader_rec_size = args->shader_rec_size; | |
602 | ||
603 | exec->uniforms_v = exec->exec_bo->vaddr + uniforms_offset; | |
604 | exec->uniforms_p = exec->exec_bo->paddr + uniforms_offset; | |
605 | exec->uniforms_size = args->uniforms_size; | |
606 | ||
607 | ret = vc4_validate_bin_cl(dev, | |
608 | exec->exec_bo->vaddr + bin_offset, | |
609 | bin, | |
610 | exec); | |
611 | if (ret) | |
612 | goto fail; | |
613 | ||
614 | ret = vc4_validate_shader_recs(dev, exec); | |
615 | ||
616 | fail: | |
617 | kfree(temp); | |
618 | return ret; | |
619 | } | |
620 | ||
621 | static void | |
622 | vc4_complete_exec(struct drm_device *dev, struct vc4_exec_info *exec) | |
623 | { | |
624 | unsigned i; | |
625 | ||
626 | /* Need the struct lock for drm_gem_object_unreference(). */ | |
627 | mutex_lock(&dev->struct_mutex); | |
628 | if (exec->bo) { | |
629 | for (i = 0; i < exec->bo_count; i++) | |
630 | drm_gem_object_unreference(&exec->bo[i]->base); | |
631 | kfree(exec->bo); | |
632 | } | |
633 | ||
634 | while (!list_empty(&exec->unref_list)) { | |
635 | struct vc4_bo *bo = list_first_entry(&exec->unref_list, | |
636 | struct vc4_bo, unref_head); | |
637 | list_del(&bo->unref_head); | |
638 | drm_gem_object_unreference(&bo->base.base); | |
639 | } | |
640 | mutex_unlock(&dev->struct_mutex); | |
641 | ||
642 | kfree(exec); | |
643 | } | |
644 | ||
645 | void | |
646 | vc4_job_handle_completed(struct vc4_dev *vc4) | |
647 | { | |
648 | unsigned long irqflags; | |
b501bacc | 649 | struct vc4_seqno_cb *cb, *cb_temp; |
d5b1a78a EA |
650 | |
651 | spin_lock_irqsave(&vc4->job_lock, irqflags); | |
652 | while (!list_empty(&vc4->job_done_list)) { | |
653 | struct vc4_exec_info *exec = | |
654 | list_first_entry(&vc4->job_done_list, | |
655 | struct vc4_exec_info, head); | |
656 | list_del(&exec->head); | |
657 | ||
658 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
659 | vc4_complete_exec(vc4->dev, exec); | |
660 | spin_lock_irqsave(&vc4->job_lock, irqflags); | |
661 | } | |
b501bacc EA |
662 | |
663 | list_for_each_entry_safe(cb, cb_temp, &vc4->seqno_cb_list, work.entry) { | |
664 | if (cb->seqno <= vc4->finished_seqno) { | |
665 | list_del_init(&cb->work.entry); | |
666 | schedule_work(&cb->work); | |
667 | } | |
668 | } | |
669 | ||
670 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
671 | } | |
672 | ||
673 | static void vc4_seqno_cb_work(struct work_struct *work) | |
674 | { | |
675 | struct vc4_seqno_cb *cb = container_of(work, struct vc4_seqno_cb, work); | |
676 | ||
677 | cb->func(cb); | |
678 | } | |
679 | ||
680 | int vc4_queue_seqno_cb(struct drm_device *dev, | |
681 | struct vc4_seqno_cb *cb, uint64_t seqno, | |
682 | void (*func)(struct vc4_seqno_cb *cb)) | |
683 | { | |
684 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
685 | int ret = 0; | |
686 | unsigned long irqflags; | |
687 | ||
688 | cb->func = func; | |
689 | INIT_WORK(&cb->work, vc4_seqno_cb_work); | |
690 | ||
691 | spin_lock_irqsave(&vc4->job_lock, irqflags); | |
692 | if (seqno > vc4->finished_seqno) { | |
693 | cb->seqno = seqno; | |
694 | list_add_tail(&cb->work.entry, &vc4->seqno_cb_list); | |
695 | } else { | |
696 | schedule_work(&cb->work); | |
697 | } | |
d5b1a78a | 698 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); |
b501bacc EA |
699 | |
700 | return ret; | |
d5b1a78a EA |
701 | } |
702 | ||
703 | /* Scheduled when any job has been completed, this walks the list of | |
704 | * jobs that had completed and unrefs their BOs and frees their exec | |
705 | * structs. | |
706 | */ | |
707 | static void | |
708 | vc4_job_done_work(struct work_struct *work) | |
709 | { | |
710 | struct vc4_dev *vc4 = | |
711 | container_of(work, struct vc4_dev, job_done_work); | |
712 | ||
713 | vc4_job_handle_completed(vc4); | |
714 | } | |
715 | ||
716 | static int | |
717 | vc4_wait_for_seqno_ioctl_helper(struct drm_device *dev, | |
718 | uint64_t seqno, | |
719 | uint64_t *timeout_ns) | |
720 | { | |
721 | unsigned long start = jiffies; | |
722 | int ret = vc4_wait_for_seqno(dev, seqno, *timeout_ns, true); | |
723 | ||
724 | if ((ret == -EINTR || ret == -ERESTARTSYS) && *timeout_ns != ~0ull) { | |
725 | uint64_t delta = jiffies_to_nsecs(jiffies - start); | |
726 | ||
727 | if (*timeout_ns >= delta) | |
728 | *timeout_ns -= delta; | |
729 | } | |
730 | ||
731 | return ret; | |
732 | } | |
733 | ||
734 | int | |
735 | vc4_wait_seqno_ioctl(struct drm_device *dev, void *data, | |
736 | struct drm_file *file_priv) | |
737 | { | |
738 | struct drm_vc4_wait_seqno *args = data; | |
739 | ||
740 | return vc4_wait_for_seqno_ioctl_helper(dev, args->seqno, | |
741 | &args->timeout_ns); | |
742 | } | |
743 | ||
744 | int | |
745 | vc4_wait_bo_ioctl(struct drm_device *dev, void *data, | |
746 | struct drm_file *file_priv) | |
747 | { | |
748 | int ret; | |
749 | struct drm_vc4_wait_bo *args = data; | |
750 | struct drm_gem_object *gem_obj; | |
751 | struct vc4_bo *bo; | |
752 | ||
e0015236 EA |
753 | if (args->pad != 0) |
754 | return -EINVAL; | |
755 | ||
d5b1a78a EA |
756 | gem_obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
757 | if (!gem_obj) { | |
758 | DRM_ERROR("Failed to look up GEM BO %d\n", args->handle); | |
759 | return -EINVAL; | |
760 | } | |
761 | bo = to_vc4_bo(gem_obj); | |
762 | ||
763 | ret = vc4_wait_for_seqno_ioctl_helper(dev, bo->seqno, | |
764 | &args->timeout_ns); | |
765 | ||
766 | drm_gem_object_unreference_unlocked(gem_obj); | |
767 | return ret; | |
768 | } | |
769 | ||
770 | /** | |
771 | * Submits a command list to the VC4. | |
772 | * | |
773 | * This is what is called batchbuffer emitting on other hardware. | |
774 | */ | |
775 | int | |
776 | vc4_submit_cl_ioctl(struct drm_device *dev, void *data, | |
777 | struct drm_file *file_priv) | |
778 | { | |
779 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
780 | struct drm_vc4_submit_cl *args = data; | |
781 | struct vc4_exec_info *exec; | |
782 | int ret; | |
783 | ||
784 | if ((args->flags & ~VC4_SUBMIT_CL_USE_CLEAR_COLOR) != 0) { | |
785 | DRM_ERROR("Unknown flags: 0x%02x\n", args->flags); | |
786 | return -EINVAL; | |
787 | } | |
788 | ||
789 | exec = kcalloc(1, sizeof(*exec), GFP_KERNEL); | |
790 | if (!exec) { | |
791 | DRM_ERROR("malloc failure on exec struct\n"); | |
792 | return -ENOMEM; | |
793 | } | |
794 | ||
795 | exec->args = args; | |
796 | INIT_LIST_HEAD(&exec->unref_list); | |
797 | ||
798 | ret = vc4_cl_lookup_bos(dev, file_priv, exec); | |
799 | if (ret) | |
800 | goto fail; | |
801 | ||
802 | if (exec->args->bin_cl_size != 0) { | |
803 | ret = vc4_get_bcl(dev, exec); | |
804 | if (ret) | |
805 | goto fail; | |
806 | } else { | |
807 | exec->ct0ca = 0; | |
808 | exec->ct0ea = 0; | |
809 | } | |
810 | ||
811 | ret = vc4_get_rcl(dev, exec); | |
812 | if (ret) | |
813 | goto fail; | |
814 | ||
815 | /* Clear this out of the struct we'll be putting in the queue, | |
816 | * since it's part of our stack. | |
817 | */ | |
818 | exec->args = NULL; | |
819 | ||
820 | vc4_queue_submit(dev, exec); | |
821 | ||
822 | /* Return the seqno for our job. */ | |
823 | args->seqno = vc4->emit_seqno; | |
824 | ||
825 | return 0; | |
826 | ||
827 | fail: | |
828 | vc4_complete_exec(vc4->dev, exec); | |
829 | ||
830 | return ret; | |
831 | } | |
832 | ||
833 | void | |
834 | vc4_gem_init(struct drm_device *dev) | |
835 | { | |
836 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
837 | ||
838 | INIT_LIST_HEAD(&vc4->job_list); | |
839 | INIT_LIST_HEAD(&vc4->job_done_list); | |
b501bacc | 840 | INIT_LIST_HEAD(&vc4->seqno_cb_list); |
d5b1a78a EA |
841 | spin_lock_init(&vc4->job_lock); |
842 | ||
843 | INIT_WORK(&vc4->hangcheck.reset_work, vc4_reset_work); | |
844 | setup_timer(&vc4->hangcheck.timer, | |
845 | vc4_hangcheck_elapsed, | |
846 | (unsigned long)dev); | |
847 | ||
848 | INIT_WORK(&vc4->job_done_work, vc4_job_done_work); | |
849 | } | |
850 | ||
851 | void | |
852 | vc4_gem_destroy(struct drm_device *dev) | |
853 | { | |
854 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
855 | ||
856 | /* Waiting for exec to finish would need to be done before | |
857 | * unregistering V3D. | |
858 | */ | |
859 | WARN_ON(vc4->emit_seqno != vc4->finished_seqno); | |
860 | ||
861 | /* V3D should already have disabled its interrupt and cleared | |
862 | * the overflow allocation registers. Now free the object. | |
863 | */ | |
864 | if (vc4->overflow_mem) { | |
865 | drm_gem_object_unreference_unlocked(&vc4->overflow_mem->base.base); | |
866 | vc4->overflow_mem = NULL; | |
867 | } | |
868 | ||
869 | vc4_bo_cache_destroy(dev); | |
21461365 EA |
870 | |
871 | if (vc4->hang_state) | |
872 | vc4_free_hang_state(dev, vc4->hang_state); | |
d5b1a78a | 873 | } |