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fb1d9738 JB |
1 | /************************************************************************** |
2 | * | |
3 | * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | **************************************************************************/ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
fb1d9738 JB |
29 | #include "vmwgfx_drv.h" |
30 | ||
31 | #define VMW_FENCE_WRAP (1 << 24) | |
32 | ||
e9f0d76f | 33 | irqreturn_t vmw_irq_handler(int irq, void *arg) |
fb1d9738 JB |
34 | { |
35 | struct drm_device *dev = (struct drm_device *)arg; | |
36 | struct vmw_private *dev_priv = vmw_priv(dev); | |
57c5ee79 | 37 | uint32_t status, masked_status; |
fb1d9738 JB |
38 | |
39 | spin_lock(&dev_priv->irq_lock); | |
40 | status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); | |
57c5ee79 | 41 | masked_status = status & dev_priv->irq_mask; |
fb1d9738 JB |
42 | spin_unlock(&dev_priv->irq_lock); |
43 | ||
57c5ee79 TH |
44 | if (likely(status)) |
45 | outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); | |
ae2a1040 | 46 | |
57c5ee79 TH |
47 | if (!masked_status) |
48 | return IRQ_NONE; | |
49 | ||
50 | if (masked_status & (SVGA_IRQFLAG_ANY_FENCE | | |
51 | SVGA_IRQFLAG_FENCE_GOAL)) { | |
52 | vmw_fences_update(dev_priv->fman); | |
fb1d9738 | 53 | wake_up_all(&dev_priv->fence_queue); |
ae2a1040 | 54 | } |
57c5ee79 TH |
55 | |
56 | if (masked_status & SVGA_IRQFLAG_FIFO_PROGRESS) | |
fb1d9738 JB |
57 | wake_up_all(&dev_priv->fifo_queue); |
58 | ||
fb1d9738 | 59 | |
57c5ee79 | 60 | return IRQ_HANDLED; |
fb1d9738 JB |
61 | } |
62 | ||
6bcd8d3c | 63 | static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno) |
fb1d9738 | 64 | { |
fb1d9738 | 65 | |
496eb6fd | 66 | return (vmw_read(dev_priv, SVGA_REG_BUSY) == 0); |
fb1d9738 JB |
67 | } |
68 | ||
6bcd8d3c | 69 | void vmw_update_seqno(struct vmw_private *dev_priv, |
1925d456 TH |
70 | struct vmw_fifo_state *fifo_state) |
71 | { | |
72 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; | |
6bcd8d3c | 73 | uint32_t seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE); |
1925d456 | 74 | |
6bcd8d3c TH |
75 | if (dev_priv->last_read_seqno != seqno) { |
76 | dev_priv->last_read_seqno = seqno; | |
77 | vmw_marker_pull(&fifo_state->marker_queue, seqno); | |
57c5ee79 | 78 | vmw_fences_update(dev_priv->fman); |
1925d456 TH |
79 | } |
80 | } | |
fb1d9738 | 81 | |
6bcd8d3c TH |
82 | bool vmw_seqno_passed(struct vmw_private *dev_priv, |
83 | uint32_t seqno) | |
fb1d9738 | 84 | { |
fb1d9738 JB |
85 | struct vmw_fifo_state *fifo_state; |
86 | bool ret; | |
87 | ||
6bcd8d3c | 88 | if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP)) |
fb1d9738 JB |
89 | return true; |
90 | ||
1925d456 | 91 | fifo_state = &dev_priv->fifo; |
6bcd8d3c TH |
92 | vmw_update_seqno(dev_priv, fifo_state); |
93 | if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP)) | |
fb1d9738 JB |
94 | return true; |
95 | ||
fb1d9738 | 96 | if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE) && |
6bcd8d3c | 97 | vmw_fifo_idle(dev_priv, seqno)) |
fb1d9738 JB |
98 | return true; |
99 | ||
fb1d9738 | 100 | /** |
6bcd8d3c | 101 | * Then check if the seqno is higher than what we've actually |
fb1d9738 JB |
102 | * emitted. Then the fence is stale and signaled. |
103 | */ | |
104 | ||
6bcd8d3c | 105 | ret = ((atomic_read(&dev_priv->marker_seq) - seqno) |
85b9e487 | 106 | > VMW_FENCE_WRAP); |
fb1d9738 JB |
107 | |
108 | return ret; | |
109 | } | |
110 | ||
111 | int vmw_fallback_wait(struct vmw_private *dev_priv, | |
112 | bool lazy, | |
113 | bool fifo_idle, | |
6bcd8d3c | 114 | uint32_t seqno, |
fb1d9738 JB |
115 | bool interruptible, |
116 | unsigned long timeout) | |
117 | { | |
118 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; | |
119 | ||
120 | uint32_t count = 0; | |
121 | uint32_t signal_seq; | |
122 | int ret; | |
123 | unsigned long end_jiffies = jiffies + timeout; | |
124 | bool (*wait_condition)(struct vmw_private *, uint32_t); | |
125 | DEFINE_WAIT(__wait); | |
126 | ||
127 | wait_condition = (fifo_idle) ? &vmw_fifo_idle : | |
6bcd8d3c | 128 | &vmw_seqno_passed; |
fb1d9738 JB |
129 | |
130 | /** | |
131 | * Block command submission while waiting for idle. | |
132 | */ | |
133 | ||
134 | if (fifo_idle) | |
135 | down_read(&fifo_state->rwsem); | |
6bcd8d3c | 136 | signal_seq = atomic_read(&dev_priv->marker_seq); |
fb1d9738 JB |
137 | ret = 0; |
138 | ||
139 | for (;;) { | |
140 | prepare_to_wait(&dev_priv->fence_queue, &__wait, | |
141 | (interruptible) ? | |
142 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
6bcd8d3c | 143 | if (wait_condition(dev_priv, seqno)) |
fb1d9738 JB |
144 | break; |
145 | if (time_after_eq(jiffies, end_jiffies)) { | |
146 | DRM_ERROR("SVGA device lockup.\n"); | |
147 | break; | |
148 | } | |
149 | if (lazy) | |
150 | schedule_timeout(1); | |
151 | else if ((++count & 0x0F) == 0) { | |
152 | /** | |
153 | * FIXME: Use schedule_hr_timeout here for | |
154 | * newer kernels and lower CPU utilization. | |
155 | */ | |
156 | ||
157 | __set_current_state(TASK_RUNNING); | |
158 | schedule(); | |
159 | __set_current_state((interruptible) ? | |
160 | TASK_INTERRUPTIBLE : | |
161 | TASK_UNINTERRUPTIBLE); | |
162 | } | |
163 | if (interruptible && signal_pending(current)) { | |
3d3a5b32 | 164 | ret = -ERESTARTSYS; |
fb1d9738 JB |
165 | break; |
166 | } | |
167 | } | |
168 | finish_wait(&dev_priv->fence_queue, &__wait); | |
169 | if (ret == 0 && fifo_idle) { | |
170 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; | |
171 | iowrite32(signal_seq, fifo_mem + SVGA_FIFO_FENCE); | |
172 | } | |
173 | wake_up_all(&dev_priv->fence_queue); | |
174 | if (fifo_idle) | |
175 | up_read(&fifo_state->rwsem); | |
176 | ||
177 | return ret; | |
178 | } | |
179 | ||
ae2a1040 | 180 | void vmw_seqno_waiter_add(struct vmw_private *dev_priv) |
4f73a96b | 181 | { |
496eb6fd | 182 | spin_lock(&dev_priv->waiter_lock); |
4f73a96b TH |
183 | if (dev_priv->fence_queue_waiters++ == 0) { |
184 | unsigned long irq_flags; | |
185 | ||
186 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); | |
187 | outl(SVGA_IRQFLAG_ANY_FENCE, | |
188 | dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); | |
57c5ee79 TH |
189 | dev_priv->irq_mask |= SVGA_IRQFLAG_ANY_FENCE; |
190 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); | |
4f73a96b TH |
191 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
192 | } | |
496eb6fd | 193 | spin_unlock(&dev_priv->waiter_lock); |
4f73a96b TH |
194 | } |
195 | ||
ae2a1040 | 196 | void vmw_seqno_waiter_remove(struct vmw_private *dev_priv) |
4f73a96b | 197 | { |
496eb6fd | 198 | spin_lock(&dev_priv->waiter_lock); |
4f73a96b TH |
199 | if (--dev_priv->fence_queue_waiters == 0) { |
200 | unsigned long irq_flags; | |
201 | ||
202 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); | |
57c5ee79 TH |
203 | dev_priv->irq_mask &= ~SVGA_IRQFLAG_ANY_FENCE; |
204 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); | |
205 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); | |
206 | } | |
496eb6fd | 207 | spin_unlock(&dev_priv->waiter_lock); |
57c5ee79 TH |
208 | } |
209 | ||
210 | ||
211 | void vmw_goal_waiter_add(struct vmw_private *dev_priv) | |
212 | { | |
496eb6fd | 213 | spin_lock(&dev_priv->waiter_lock); |
57c5ee79 TH |
214 | if (dev_priv->goal_queue_waiters++ == 0) { |
215 | unsigned long irq_flags; | |
216 | ||
217 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); | |
218 | outl(SVGA_IRQFLAG_FENCE_GOAL, | |
219 | dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); | |
220 | dev_priv->irq_mask |= SVGA_IRQFLAG_FENCE_GOAL; | |
221 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); | |
222 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); | |
223 | } | |
496eb6fd | 224 | spin_unlock(&dev_priv->waiter_lock); |
57c5ee79 TH |
225 | } |
226 | ||
227 | void vmw_goal_waiter_remove(struct vmw_private *dev_priv) | |
228 | { | |
496eb6fd | 229 | spin_lock(&dev_priv->waiter_lock); |
57c5ee79 TH |
230 | if (--dev_priv->goal_queue_waiters == 0) { |
231 | unsigned long irq_flags; | |
232 | ||
233 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); | |
234 | dev_priv->irq_mask &= ~SVGA_IRQFLAG_FENCE_GOAL; | |
235 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); | |
4f73a96b TH |
236 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
237 | } | |
496eb6fd | 238 | spin_unlock(&dev_priv->waiter_lock); |
4f73a96b TH |
239 | } |
240 | ||
6bcd8d3c TH |
241 | int vmw_wait_seqno(struct vmw_private *dev_priv, |
242 | bool lazy, uint32_t seqno, | |
243 | bool interruptible, unsigned long timeout) | |
fb1d9738 JB |
244 | { |
245 | long ret; | |
fb1d9738 JB |
246 | struct vmw_fifo_state *fifo = &dev_priv->fifo; |
247 | ||
6bcd8d3c | 248 | if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP)) |
fb1d9738 JB |
249 | return 0; |
250 | ||
6bcd8d3c | 251 | if (likely(vmw_seqno_passed(dev_priv, seqno))) |
fb1d9738 JB |
252 | return 0; |
253 | ||
254 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); | |
255 | ||
256 | if (!(fifo->capabilities & SVGA_FIFO_CAP_FENCE)) | |
6bcd8d3c | 257 | return vmw_fallback_wait(dev_priv, lazy, true, seqno, |
fb1d9738 JB |
258 | interruptible, timeout); |
259 | ||
260 | if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) | |
6bcd8d3c | 261 | return vmw_fallback_wait(dev_priv, lazy, false, seqno, |
fb1d9738 JB |
262 | interruptible, timeout); |
263 | ||
4f73a96b | 264 | vmw_seqno_waiter_add(dev_priv); |
fb1d9738 JB |
265 | |
266 | if (interruptible) | |
267 | ret = wait_event_interruptible_timeout | |
268 | (dev_priv->fence_queue, | |
6bcd8d3c | 269 | vmw_seqno_passed(dev_priv, seqno), |
fb1d9738 JB |
270 | timeout); |
271 | else | |
272 | ret = wait_event_timeout | |
273 | (dev_priv->fence_queue, | |
6bcd8d3c | 274 | vmw_seqno_passed(dev_priv, seqno), |
fb1d9738 JB |
275 | timeout); |
276 | ||
4f73a96b TH |
277 | vmw_seqno_waiter_remove(dev_priv); |
278 | ||
3d3a5b32 | 279 | if (unlikely(ret == 0)) |
fb1d9738 JB |
280 | ret = -EBUSY; |
281 | else if (likely(ret > 0)) | |
282 | ret = 0; | |
283 | ||
fb1d9738 JB |
284 | return ret; |
285 | } | |
286 | ||
287 | void vmw_irq_preinstall(struct drm_device *dev) | |
288 | { | |
289 | struct vmw_private *dev_priv = vmw_priv(dev); | |
290 | uint32_t status; | |
291 | ||
292 | if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) | |
293 | return; | |
294 | ||
295 | spin_lock_init(&dev_priv->irq_lock); | |
296 | status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); | |
297 | outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); | |
298 | } | |
299 | ||
300 | int vmw_irq_postinstall(struct drm_device *dev) | |
301 | { | |
302 | return 0; | |
303 | } | |
304 | ||
305 | void vmw_irq_uninstall(struct drm_device *dev) | |
306 | { | |
307 | struct vmw_private *dev_priv = vmw_priv(dev); | |
308 | uint32_t status; | |
309 | ||
310 | if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) | |
311 | return; | |
312 | ||
fb1d9738 | 313 | vmw_write(dev_priv, SVGA_REG_IRQMASK, 0); |
fb1d9738 JB |
314 | |
315 | status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); | |
316 | outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); | |
317 | } |