Commit | Line | Data |
---|---|---|
3e7ee490 | 1 | /* |
3e7ee490 HJ |
2 | * Copyright (c) 2009, Microsoft Corporation. |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
17 | * Authors: | |
18 | * Haiyang Zhang <haiyangz@microsoft.com> | |
19 | * Hank Janssen <hjanssen@microsoft.com> | |
20 | * | |
21 | */ | |
0a46618d HJ |
22 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
23 | ||
a0086dc5 GKH |
24 | #include <linux/kernel.h> |
25 | #include <linux/mm.h> | |
5a0e3ad6 | 26 | #include <linux/slab.h> |
b7c947f0 | 27 | #include <linux/vmalloc.h> |
46a97191 | 28 | #include <linux/hyperv.h> |
83ba0c4f | 29 | #include <linux/version.h> |
db11f12a | 30 | #include <linux/interrupt.h> |
4061ed9e | 31 | #include <linux/clockchips.h> |
407dd164 | 32 | #include <asm/hyperv.h> |
4061ed9e | 33 | #include <asm/mshyperv.h> |
0f2a6619 | 34 | #include "hyperv_vmbus.h" |
3e7ee490 | 35 | |
454f18a9 | 36 | /* The one and only */ |
6a0aaa18 HZ |
37 | struct hv_context hv_context = { |
38 | .synic_initialized = false, | |
39 | .hypercall_page = NULL, | |
3e7ee490 HJ |
40 | }; |
41 | ||
4061ed9e S |
42 | #define HV_TIMER_FREQUENCY (10 * 1000 * 1000) /* 100ns period */ |
43 | #define HV_MAX_MAX_DELTA_TICKS 0xffffffff | |
44 | #define HV_MIN_DELTA_TICKS 1 | |
45 | ||
3e189519 | 46 | /* |
d44890c8 | 47 | * query_hypervisor_info - Get version info of the windows hypervisor |
0831ad04 | 48 | */ |
5fbebb2d S |
49 | unsigned int host_info_eax; |
50 | unsigned int host_info_ebx; | |
51 | unsigned int host_info_ecx; | |
52 | unsigned int host_info_edx; | |
53 | ||
d44890c8 | 54 | static int query_hypervisor_info(void) |
0831ad04 GKH |
55 | { |
56 | unsigned int eax; | |
57 | unsigned int ebx; | |
58 | unsigned int ecx; | |
59 | unsigned int edx; | |
b8dfb264 | 60 | unsigned int max_leaf; |
0831ad04 | 61 | unsigned int op; |
3e7ee490 | 62 | |
0831ad04 GKH |
63 | /* |
64 | * Its assumed that this is called after confirming that Viridian | |
65 | * is present. Query id and revision. | |
66 | */ | |
67 | eax = 0; | |
68 | ebx = 0; | |
69 | ecx = 0; | |
70 | edx = 0; | |
f6feebe0 | 71 | op = HVCPUID_VENDOR_MAXFUNCTION; |
0831ad04 | 72 | cpuid(op, &eax, &ebx, &ecx, &edx); |
3e7ee490 | 73 | |
b8dfb264 | 74 | max_leaf = eax; |
0831ad04 | 75 | |
b8dfb264 | 76 | if (max_leaf >= HVCPUID_VERSION) { |
0831ad04 GKH |
77 | eax = 0; |
78 | ebx = 0; | |
79 | ecx = 0; | |
80 | edx = 0; | |
f6feebe0 | 81 | op = HVCPUID_VERSION; |
0831ad04 | 82 | cpuid(op, &eax, &ebx, &ecx, &edx); |
5fbebb2d S |
83 | host_info_eax = eax; |
84 | host_info_ebx = ebx; | |
85 | host_info_ecx = ecx; | |
86 | host_info_edx = edx; | |
0831ad04 | 87 | } |
b8dfb264 | 88 | return max_leaf; |
0831ad04 | 89 | } |
3e7ee490 | 90 | |
3e189519 | 91 | /* |
d44890c8 | 92 | * do_hypercall- Invoke the specified hypercall |
0831ad04 | 93 | */ |
d44890c8 | 94 | static u64 do_hypercall(u64 control, void *input, void *output) |
3e7ee490 | 95 | { |
b8dfb264 HZ |
96 | u64 input_address = (input) ? virt_to_phys(input) : 0; |
97 | u64 output_address = (output) ? virt_to_phys(output) : 0; | |
dec317fd | 98 | void *hypercall_page = hv_context.hypercall_page; |
d7646eaa VK |
99 | #ifdef CONFIG_X86_64 |
100 | u64 hv_status = 0; | |
101 | ||
102 | if (!hypercall_page) | |
103 | return (u64)ULLONG_MAX; | |
3e7ee490 | 104 | |
b8dfb264 HZ |
105 | __asm__ __volatile__("mov %0, %%r8" : : "r" (output_address) : "r8"); |
106 | __asm__ __volatile__("call *%3" : "=a" (hv_status) : | |
107 | "c" (control), "d" (input_address), | |
108 | "m" (hypercall_page)); | |
3e7ee490 | 109 | |
b8dfb264 | 110 | return hv_status; |
3e7ee490 HJ |
111 | |
112 | #else | |
113 | ||
b8dfb264 HZ |
114 | u32 control_hi = control >> 32; |
115 | u32 control_lo = control & 0xFFFFFFFF; | |
116 | u32 hv_status_hi = 1; | |
117 | u32 hv_status_lo = 1; | |
b8dfb264 HZ |
118 | u32 input_address_hi = input_address >> 32; |
119 | u32 input_address_lo = input_address & 0xFFFFFFFF; | |
b8dfb264 HZ |
120 | u32 output_address_hi = output_address >> 32; |
121 | u32 output_address_lo = output_address & 0xFFFFFFFF; | |
d7646eaa VK |
122 | |
123 | if (!hypercall_page) | |
124 | return (u64)ULLONG_MAX; | |
3e7ee490 | 125 | |
b8dfb264 HZ |
126 | __asm__ __volatile__ ("call *%8" : "=d"(hv_status_hi), |
127 | "=a"(hv_status_lo) : "d" (control_hi), | |
128 | "a" (control_lo), "b" (input_address_hi), | |
129 | "c" (input_address_lo), "D"(output_address_hi), | |
130 | "S"(output_address_lo), "m" (hypercall_page)); | |
3e7ee490 | 131 | |
b8dfb264 | 132 | return hv_status_lo | ((u64)hv_status_hi << 32); |
0831ad04 | 133 | #endif /* !x86_64 */ |
3e7ee490 HJ |
134 | } |
135 | ||
ca9357bd S |
136 | #ifdef CONFIG_X86_64 |
137 | static cycle_t read_hv_clock_tsc(struct clocksource *arg) | |
138 | { | |
139 | cycle_t current_tick; | |
140 | struct ms_hyperv_tsc_page *tsc_pg = hv_context.tsc_page; | |
141 | ||
142 | if (tsc_pg->tsc_sequence != -1) { | |
143 | /* | |
144 | * Use the tsc page to compute the value. | |
145 | */ | |
146 | ||
147 | while (1) { | |
148 | cycle_t tmp; | |
149 | u32 sequence = tsc_pg->tsc_sequence; | |
150 | u64 cur_tsc; | |
151 | u64 scale = tsc_pg->tsc_scale; | |
152 | s64 offset = tsc_pg->tsc_offset; | |
153 | ||
154 | rdtscll(cur_tsc); | |
155 | /* current_tick = ((cur_tsc *scale) >> 64) + offset */ | |
156 | asm("mulq %3" | |
157 | : "=d" (current_tick), "=a" (tmp) | |
158 | : "a" (cur_tsc), "r" (scale)); | |
159 | ||
160 | current_tick += offset; | |
161 | if (tsc_pg->tsc_sequence == sequence) | |
162 | return current_tick; | |
163 | ||
164 | if (tsc_pg->tsc_sequence != -1) | |
165 | continue; | |
166 | /* | |
167 | * Fallback using MSR method. | |
168 | */ | |
169 | break; | |
170 | } | |
171 | } | |
172 | rdmsrl(HV_X64_MSR_TIME_REF_COUNT, current_tick); | |
173 | return current_tick; | |
174 | } | |
175 | ||
176 | static struct clocksource hyperv_cs_tsc = { | |
177 | .name = "hyperv_clocksource_tsc_page", | |
178 | .rating = 425, | |
179 | .read = read_hv_clock_tsc, | |
180 | .mask = CLOCKSOURCE_MASK(64), | |
181 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
182 | }; | |
183 | #endif | |
184 | ||
185 | ||
3e189519 | 186 | /* |
d44890c8 | 187 | * hv_init - Main initialization routine. |
0831ad04 GKH |
188 | * |
189 | * This routine must be called before any other routines in here are called | |
190 | */ | |
d44890c8 | 191 | int hv_init(void) |
3e7ee490 | 192 | { |
b8dfb264 HZ |
193 | int max_leaf; |
194 | union hv_x64_msr_hypercall_contents hypercall_msr; | |
ca9357bd | 195 | union hv_x64_msr_hypercall_contents tsc_msr; |
b8dfb264 | 196 | void *virtaddr = NULL; |
ca9357bd | 197 | void *va_tsc = NULL; |
3e7ee490 | 198 | |
14c1bf8a | 199 | memset(hv_context.synic_event_page, 0, sizeof(void *) * NR_CPUS); |
6a0aaa18 | 200 | memset(hv_context.synic_message_page, 0, |
14c1bf8a | 201 | sizeof(void *) * NR_CPUS); |
b29ef354 S |
202 | memset(hv_context.post_msg_page, 0, |
203 | sizeof(void *) * NR_CPUS); | |
917ea427 S |
204 | memset(hv_context.vp_index, 0, |
205 | sizeof(int) * NR_CPUS); | |
db11f12a S |
206 | memset(hv_context.event_dpc, 0, |
207 | sizeof(void *) * NR_CPUS); | |
4061ed9e S |
208 | memset(hv_context.clk_evt, 0, |
209 | sizeof(void *) * NR_CPUS); | |
3e7ee490 | 210 | |
d44890c8 | 211 | max_leaf = query_hypervisor_info(); |
3e7ee490 | 212 | |
83ba0c4f S |
213 | /* |
214 | * Write our OS ID. | |
215 | */ | |
216 | hv_context.guestid = generate_guest_id(0, LINUX_VERSION_CODE, 0); | |
217 | wrmsrl(HV_X64_MSR_GUEST_OS_ID, hv_context.guestid); | |
a73e6b7c | 218 | |
454f18a9 | 219 | /* See if the hypercall page is already set */ |
b8dfb264 | 220 | rdmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); |
3e7ee490 | 221 | |
df3493e0 | 222 | virtaddr = __vmalloc(PAGE_SIZE, GFP_KERNEL, PAGE_KERNEL_EXEC); |
3e7ee490 | 223 | |
98e08702 | 224 | if (!virtaddr) |
44939d37 | 225 | goto cleanup; |
3e7ee490 | 226 | |
b8dfb264 | 227 | hypercall_msr.enable = 1; |
a73e6b7c | 228 | |
b8dfb264 HZ |
229 | hypercall_msr.guest_physical_address = vmalloc_to_pfn(virtaddr); |
230 | wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); | |
a73e6b7c HJ |
231 | |
232 | /* Confirm that hypercall page did get setup. */ | |
b8dfb264 HZ |
233 | hypercall_msr.as_uint64 = 0; |
234 | rdmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); | |
a73e6b7c | 235 | |
98e08702 | 236 | if (!hypercall_msr.enable) |
44939d37 | 237 | goto cleanup; |
3e7ee490 | 238 | |
b8dfb264 | 239 | hv_context.hypercall_page = virtaddr; |
a73e6b7c | 240 | |
ca9357bd S |
241 | #ifdef CONFIG_X86_64 |
242 | if (ms_hyperv.features & HV_X64_MSR_REFERENCE_TSC_AVAILABLE) { | |
243 | va_tsc = __vmalloc(PAGE_SIZE, GFP_KERNEL, PAGE_KERNEL); | |
244 | if (!va_tsc) | |
245 | goto cleanup; | |
246 | hv_context.tsc_page = va_tsc; | |
247 | ||
248 | rdmsrl(HV_X64_MSR_REFERENCE_TSC, tsc_msr.as_uint64); | |
249 | ||
250 | tsc_msr.enable = 1; | |
251 | tsc_msr.guest_physical_address = vmalloc_to_pfn(va_tsc); | |
252 | ||
253 | wrmsrl(HV_X64_MSR_REFERENCE_TSC, tsc_msr.as_uint64); | |
254 | clocksource_register_hz(&hyperv_cs_tsc, NSEC_PER_SEC/100); | |
255 | } | |
256 | #endif | |
5433e003 | 257 | return 0; |
3e7ee490 | 258 | |
44939d37 | 259 | cleanup: |
b8dfb264 HZ |
260 | if (virtaddr) { |
261 | if (hypercall_msr.enable) { | |
262 | hypercall_msr.as_uint64 = 0; | |
263 | wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); | |
3e7ee490 HJ |
264 | } |
265 | ||
b8dfb264 | 266 | vfree(virtaddr); |
3e7ee490 | 267 | } |
5433e003 S |
268 | |
269 | return -ENOTSUPP; | |
3e7ee490 HJ |
270 | } |
271 | ||
3e189519 | 272 | /* |
d44890c8 | 273 | * hv_cleanup - Cleanup routine. |
0831ad04 GKH |
274 | * |
275 | * This routine is called normally during driver unloading or exiting. | |
276 | */ | |
d44890c8 | 277 | void hv_cleanup(void) |
3e7ee490 | 278 | { |
b8dfb264 | 279 | union hv_x64_msr_hypercall_contents hypercall_msr; |
3e7ee490 | 280 | |
93e5bd06 S |
281 | /* Reset our OS id */ |
282 | wrmsrl(HV_X64_MSR_GUEST_OS_ID, 0); | |
283 | ||
6a0aaa18 | 284 | if (hv_context.hypercall_page) { |
b8dfb264 HZ |
285 | hypercall_msr.as_uint64 = 0; |
286 | wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); | |
6a0aaa18 HZ |
287 | vfree(hv_context.hypercall_page); |
288 | hv_context.hypercall_page = NULL; | |
3e7ee490 | 289 | } |
ca9357bd S |
290 | |
291 | #ifdef CONFIG_X86_64 | |
292 | /* | |
293 | * Cleanup the TSC page based CS. | |
294 | */ | |
295 | if (ms_hyperv.features & HV_X64_MSR_REFERENCE_TSC_AVAILABLE) { | |
296 | clocksource_change_rating(&hyperv_cs_tsc, 10); | |
297 | clocksource_unregister(&hyperv_cs_tsc); | |
298 | ||
299 | hypercall_msr.as_uint64 = 0; | |
300 | wrmsrl(HV_X64_MSR_REFERENCE_TSC, hypercall_msr.as_uint64); | |
301 | vfree(hv_context.tsc_page); | |
302 | hv_context.tsc_page = NULL; | |
303 | } | |
304 | #endif | |
3e7ee490 HJ |
305 | } |
306 | ||
3e189519 | 307 | /* |
d44890c8 | 308 | * hv_post_message - Post a message using the hypervisor message IPC. |
0831ad04 GKH |
309 | * |
310 | * This involves a hypercall. | |
311 | */ | |
415f0a02 | 312 | int hv_post_message(union hv_connection_id connection_id, |
b8dfb264 HZ |
313 | enum hv_message_type message_type, |
314 | void *payload, size_t payload_size) | |
3e7ee490 | 315 | { |
3e7ee490 | 316 | |
b8dfb264 | 317 | struct hv_input_post_message *aligned_msg; |
034469e6 | 318 | u16 status; |
3e7ee490 | 319 | |
b8dfb264 | 320 | if (payload_size > HV_MESSAGE_PAYLOAD_BYTE_COUNT) |
39594abc | 321 | return -EMSGSIZE; |
3e7ee490 | 322 | |
b8dfb264 | 323 | aligned_msg = (struct hv_input_post_message *) |
b29ef354 | 324 | hv_context.post_msg_page[get_cpu()]; |
3e7ee490 | 325 | |
b8dfb264 | 326 | aligned_msg->connectionid = connection_id; |
b29ef354 | 327 | aligned_msg->reserved = 0; |
b8dfb264 HZ |
328 | aligned_msg->message_type = message_type; |
329 | aligned_msg->payload_size = payload_size; | |
330 | memcpy((void *)aligned_msg->payload, payload, payload_size); | |
3e7ee490 | 331 | |
d44890c8 HZ |
332 | status = do_hypercall(HVCALL_POST_MESSAGE, aligned_msg, NULL) |
333 | & 0xFFFF; | |
3e7ee490 | 334 | |
b29ef354 | 335 | put_cpu(); |
3e7ee490 HJ |
336 | return status; |
337 | } | |
338 | ||
339 | ||
3e189519 | 340 | /* |
d44890c8 HZ |
341 | * hv_signal_event - |
342 | * Signal an event on the specified connection using the hypervisor event IPC. | |
0831ad04 GKH |
343 | * |
344 | * This involves a hypercall. | |
345 | */ | |
1f42248d | 346 | u16 hv_signal_event(void *con_id) |
3e7ee490 | 347 | { |
034469e6 | 348 | u16 status; |
3e7ee490 | 349 | |
1f42248d S |
350 | status = (do_hypercall(HVCALL_SIGNAL_EVENT, con_id, NULL) & 0xFFFF); |
351 | ||
3e7ee490 HJ |
352 | return status; |
353 | } | |
354 | ||
4061ed9e S |
355 | static int hv_ce_set_next_event(unsigned long delta, |
356 | struct clock_event_device *evt) | |
357 | { | |
358 | cycle_t current_tick; | |
359 | ||
bc609cb4 | 360 | WARN_ON(!clockevent_state_oneshot(evt)); |
4061ed9e S |
361 | |
362 | rdmsrl(HV_X64_MSR_TIME_REF_COUNT, current_tick); | |
363 | current_tick += delta; | |
364 | wrmsrl(HV_X64_MSR_STIMER0_COUNT, current_tick); | |
365 | return 0; | |
366 | } | |
367 | ||
bc609cb4 VK |
368 | static int hv_ce_shutdown(struct clock_event_device *evt) |
369 | { | |
370 | wrmsrl(HV_X64_MSR_STIMER0_COUNT, 0); | |
371 | wrmsrl(HV_X64_MSR_STIMER0_CONFIG, 0); | |
372 | ||
373 | return 0; | |
374 | } | |
375 | ||
376 | static int hv_ce_set_oneshot(struct clock_event_device *evt) | |
4061ed9e S |
377 | { |
378 | union hv_timer_config timer_cfg; | |
379 | ||
bc609cb4 VK |
380 | timer_cfg.enable = 1; |
381 | timer_cfg.auto_enable = 1; | |
382 | timer_cfg.sintx = VMBUS_MESSAGE_SINT; | |
383 | wrmsrl(HV_X64_MSR_STIMER0_CONFIG, timer_cfg.as_uint64); | |
384 | ||
385 | return 0; | |
4061ed9e S |
386 | } |
387 | ||
388 | static void hv_init_clockevent_device(struct clock_event_device *dev, int cpu) | |
389 | { | |
390 | dev->name = "Hyper-V clockevent"; | |
391 | dev->features = CLOCK_EVT_FEAT_ONESHOT; | |
392 | dev->cpumask = cpumask_of(cpu); | |
393 | dev->rating = 1000; | |
e086748c VK |
394 | /* |
395 | * Avoid settint dev->owner = THIS_MODULE deliberately as doing so will | |
396 | * result in clockevents_config_and_register() taking additional | |
397 | * references to the hv_vmbus module making it impossible to unload. | |
398 | */ | |
4061ed9e | 399 | |
bc609cb4 VK |
400 | dev->set_state_shutdown = hv_ce_shutdown; |
401 | dev->set_state_oneshot = hv_ce_set_oneshot; | |
4061ed9e S |
402 | dev->set_next_event = hv_ce_set_next_event; |
403 | } | |
404 | ||
2608fb65 JW |
405 | |
406 | int hv_synic_alloc(void) | |
407 | { | |
408 | size_t size = sizeof(struct tasklet_struct); | |
4061ed9e | 409 | size_t ced_size = sizeof(struct clock_event_device); |
2608fb65 JW |
410 | int cpu; |
411 | ||
9f01ec53 S |
412 | hv_context.hv_numa_map = kzalloc(sizeof(struct cpumask) * nr_node_ids, |
413 | GFP_ATOMIC); | |
414 | if (hv_context.hv_numa_map == NULL) { | |
415 | pr_err("Unable to allocate NUMA map\n"); | |
416 | goto err; | |
417 | } | |
418 | ||
2608fb65 JW |
419 | for_each_online_cpu(cpu) { |
420 | hv_context.event_dpc[cpu] = kmalloc(size, GFP_ATOMIC); | |
421 | if (hv_context.event_dpc[cpu] == NULL) { | |
422 | pr_err("Unable to allocate event dpc\n"); | |
423 | goto err; | |
424 | } | |
425 | tasklet_init(hv_context.event_dpc[cpu], vmbus_on_event, cpu); | |
426 | ||
4061ed9e S |
427 | hv_context.clk_evt[cpu] = kzalloc(ced_size, GFP_ATOMIC); |
428 | if (hv_context.clk_evt[cpu] == NULL) { | |
429 | pr_err("Unable to allocate clock event device\n"); | |
430 | goto err; | |
431 | } | |
9f01ec53 | 432 | |
4061ed9e S |
433 | hv_init_clockevent_device(hv_context.clk_evt[cpu], cpu); |
434 | ||
2608fb65 JW |
435 | hv_context.synic_message_page[cpu] = |
436 | (void *)get_zeroed_page(GFP_ATOMIC); | |
437 | ||
438 | if (hv_context.synic_message_page[cpu] == NULL) { | |
439 | pr_err("Unable to allocate SYNIC message page\n"); | |
440 | goto err; | |
441 | } | |
442 | ||
443 | hv_context.synic_event_page[cpu] = | |
444 | (void *)get_zeroed_page(GFP_ATOMIC); | |
445 | ||
446 | if (hv_context.synic_event_page[cpu] == NULL) { | |
447 | pr_err("Unable to allocate SYNIC event page\n"); | |
448 | goto err; | |
449 | } | |
b29ef354 S |
450 | |
451 | hv_context.post_msg_page[cpu] = | |
452 | (void *)get_zeroed_page(GFP_ATOMIC); | |
453 | ||
454 | if (hv_context.post_msg_page[cpu] == NULL) { | |
455 | pr_err("Unable to allocate post msg page\n"); | |
456 | goto err; | |
457 | } | |
2608fb65 JW |
458 | } |
459 | ||
460 | return 0; | |
461 | err: | |
462 | return -ENOMEM; | |
463 | } | |
464 | ||
8712954d | 465 | static void hv_synic_free_cpu(int cpu) |
2608fb65 JW |
466 | { |
467 | kfree(hv_context.event_dpc[cpu]); | |
4061ed9e | 468 | kfree(hv_context.clk_evt[cpu]); |
fdf91dae | 469 | if (hv_context.synic_event_page[cpu]) |
2608fb65 JW |
470 | free_page((unsigned long)hv_context.synic_event_page[cpu]); |
471 | if (hv_context.synic_message_page[cpu]) | |
472 | free_page((unsigned long)hv_context.synic_message_page[cpu]); | |
b29ef354 S |
473 | if (hv_context.post_msg_page[cpu]) |
474 | free_page((unsigned long)hv_context.post_msg_page[cpu]); | |
2608fb65 JW |
475 | } |
476 | ||
477 | void hv_synic_free(void) | |
478 | { | |
479 | int cpu; | |
480 | ||
9f01ec53 | 481 | kfree(hv_context.hv_numa_map); |
2608fb65 JW |
482 | for_each_online_cpu(cpu) |
483 | hv_synic_free_cpu(cpu); | |
484 | } | |
485 | ||
3e189519 | 486 | /* |
d44890c8 | 487 | * hv_synic_init - Initialize the Synthethic Interrupt Controller. |
0831ad04 GKH |
488 | * |
489 | * If it is already initialized by another entity (ie x2v shim), we need to | |
490 | * retrieve the initialized message and event pages. Otherwise, we create and | |
491 | * initialize the message and event pages. | |
492 | */ | |
302a3c0f | 493 | void hv_synic_init(void *arg) |
3e7ee490 | 494 | { |
0831ad04 | 495 | u64 version; |
eacb1b4d GKH |
496 | union hv_synic_simp simp; |
497 | union hv_synic_siefp siefp; | |
b8dfb264 | 498 | union hv_synic_sint shared_sint; |
eacb1b4d | 499 | union hv_synic_scontrol sctrl; |
917ea427 | 500 | u64 vp_index; |
a73e6b7c | 501 | |
7692fd4d | 502 | int cpu = smp_processor_id(); |
3e7ee490 | 503 | |
6a0aaa18 | 504 | if (!hv_context.hypercall_page) |
7692fd4d | 505 | return; |
3e7ee490 | 506 | |
454f18a9 | 507 | /* Check the version */ |
a51ed7d6 | 508 | rdmsrl(HV_X64_MSR_SVERSION, version); |
3e7ee490 | 509 | |
a73e6b7c | 510 | /* Setup the Synic's message page */ |
f6feebe0 HZ |
511 | rdmsrl(HV_X64_MSR_SIMP, simp.as_uint64); |
512 | simp.simp_enabled = 1; | |
6a0aaa18 | 513 | simp.base_simp_gpa = virt_to_phys(hv_context.synic_message_page[cpu]) |
a73e6b7c | 514 | >> PAGE_SHIFT; |
3e7ee490 | 515 | |
f6feebe0 | 516 | wrmsrl(HV_X64_MSR_SIMP, simp.as_uint64); |
3e7ee490 | 517 | |
a73e6b7c | 518 | /* Setup the Synic's event page */ |
f6feebe0 HZ |
519 | rdmsrl(HV_X64_MSR_SIEFP, siefp.as_uint64); |
520 | siefp.siefp_enabled = 1; | |
6a0aaa18 | 521 | siefp.base_siefp_gpa = virt_to_phys(hv_context.synic_event_page[cpu]) |
a73e6b7c HJ |
522 | >> PAGE_SHIFT; |
523 | ||
f6feebe0 | 524 | wrmsrl(HV_X64_MSR_SIEFP, siefp.as_uint64); |
0831ad04 | 525 | |
0831ad04 | 526 | /* Setup the shared SINT. */ |
b8dfb264 | 527 | rdmsrl(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64); |
3e7ee490 | 528 | |
b8dfb264 | 529 | shared_sint.as_uint64 = 0; |
302a3c0f | 530 | shared_sint.vector = HYPERVISOR_CALLBACK_VECTOR; |
b8dfb264 | 531 | shared_sint.masked = false; |
b0209501 | 532 | shared_sint.auto_eoi = true; |
3e7ee490 | 533 | |
b8dfb264 | 534 | wrmsrl(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64); |
3e7ee490 | 535 | |
454f18a9 | 536 | /* Enable the global synic bit */ |
f6feebe0 HZ |
537 | rdmsrl(HV_X64_MSR_SCONTROL, sctrl.as_uint64); |
538 | sctrl.enable = 1; | |
3e7ee490 | 539 | |
f6feebe0 | 540 | wrmsrl(HV_X64_MSR_SCONTROL, sctrl.as_uint64); |
3e7ee490 | 541 | |
6a0aaa18 | 542 | hv_context.synic_initialized = true; |
917ea427 S |
543 | |
544 | /* | |
545 | * Setup the mapping between Hyper-V's notion | |
546 | * of cpuid and Linux' notion of cpuid. | |
547 | * This array will be indexed using Linux cpuid. | |
548 | */ | |
549 | rdmsrl(HV_X64_MSR_VP_INDEX, vp_index); | |
550 | hv_context.vp_index[cpu] = (u32)vp_index; | |
3a28fa35 S |
551 | |
552 | INIT_LIST_HEAD(&hv_context.percpu_list[cpu]); | |
4061ed9e S |
553 | |
554 | /* | |
555 | * Register the per-cpu clockevent source. | |
556 | */ | |
557 | if (ms_hyperv.features & HV_X64_MSR_SYNTIMER_AVAILABLE) | |
558 | clockevents_config_and_register(hv_context.clk_evt[cpu], | |
559 | HV_TIMER_FREQUENCY, | |
560 | HV_MIN_DELTA_TICKS, | |
561 | HV_MAX_MAX_DELTA_TICKS); | |
7692fd4d | 562 | return; |
3e7ee490 HJ |
563 | } |
564 | ||
e086748c VK |
565 | /* |
566 | * hv_synic_clockevents_cleanup - Cleanup clockevent devices | |
567 | */ | |
568 | void hv_synic_clockevents_cleanup(void) | |
569 | { | |
570 | int cpu; | |
571 | ||
572 | if (!(ms_hyperv.features & HV_X64_MSR_SYNTIMER_AVAILABLE)) | |
573 | return; | |
574 | ||
575 | for_each_online_cpu(cpu) | |
576 | clockevents_unbind_device(hv_context.clk_evt[cpu], cpu); | |
577 | } | |
578 | ||
3e189519 | 579 | /* |
d44890c8 | 580 | * hv_synic_cleanup - Cleanup routine for hv_synic_init(). |
0831ad04 | 581 | */ |
d44890c8 | 582 | void hv_synic_cleanup(void *arg) |
3e7ee490 | 583 | { |
b8dfb264 | 584 | union hv_synic_sint shared_sint; |
eacb1b4d GKH |
585 | union hv_synic_simp simp; |
586 | union hv_synic_siefp siefp; | |
e72e7ac5 | 587 | union hv_synic_scontrol sctrl; |
7692fd4d | 588 | int cpu = smp_processor_id(); |
3e7ee490 | 589 | |
6a0aaa18 | 590 | if (!hv_context.synic_initialized) |
3e7ee490 | 591 | return; |
3e7ee490 | 592 | |
e086748c VK |
593 | /* Turn off clockevent device */ |
594 | if (ms_hyperv.features & HV_X64_MSR_SYNTIMER_AVAILABLE) | |
bc609cb4 | 595 | hv_ce_shutdown(hv_context.clk_evt[cpu]); |
e086748c | 596 | |
b8dfb264 | 597 | rdmsrl(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64); |
3e7ee490 | 598 | |
b8dfb264 | 599 | shared_sint.masked = 1; |
3e7ee490 | 600 | |
7692fd4d | 601 | /* Need to correctly cleanup in the case of SMP!!! */ |
454f18a9 | 602 | /* Disable the interrupt */ |
b8dfb264 | 603 | wrmsrl(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64); |
3e7ee490 | 604 | |
f6feebe0 HZ |
605 | rdmsrl(HV_X64_MSR_SIMP, simp.as_uint64); |
606 | simp.simp_enabled = 0; | |
607 | simp.base_simp_gpa = 0; | |
3e7ee490 | 608 | |
f6feebe0 | 609 | wrmsrl(HV_X64_MSR_SIMP, simp.as_uint64); |
3e7ee490 | 610 | |
f6feebe0 HZ |
611 | rdmsrl(HV_X64_MSR_SIEFP, siefp.as_uint64); |
612 | siefp.siefp_enabled = 0; | |
613 | siefp.base_siefp_gpa = 0; | |
3e7ee490 | 614 | |
f6feebe0 | 615 | wrmsrl(HV_X64_MSR_SIEFP, siefp.as_uint64); |
3e7ee490 | 616 | |
e72e7ac5 VK |
617 | /* Disable the global synic bit */ |
618 | rdmsrl(HV_X64_MSR_SCONTROL, sctrl.as_uint64); | |
619 | sctrl.enable = 0; | |
620 | wrmsrl(HV_X64_MSR_SCONTROL, sctrl.as_uint64); | |
3e7ee490 | 621 | } |