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4453d736 GR |
1 | /* |
2 | * jc42.c - driver for Jedec JC42.4 compliant temperature sensors | |
3 | * | |
4 | * Copyright (c) 2010 Ericsson AB. | |
5 | * | |
6 | * Derived from lm77.c by Andras BALI <drewie@freemail.hu>. | |
7 | * | |
8 | * JC42.4 compliant temperature sensors are typically used on memory modules. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | */ | |
24 | ||
25 | #include <linux/module.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/jiffies.h> | |
29 | #include <linux/i2c.h> | |
30 | #include <linux/hwmon.h> | |
31 | #include <linux/hwmon-sysfs.h> | |
32 | #include <linux/err.h> | |
33 | #include <linux/mutex.h> | |
34 | ||
35 | /* Addresses to scan */ | |
36 | static const unsigned short normal_i2c[] = { | |
37 | 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END }; | |
38 | ||
39 | /* JC42 registers. All registers are 16 bit. */ | |
40 | #define JC42_REG_CAP 0x00 | |
41 | #define JC42_REG_CONFIG 0x01 | |
42 | #define JC42_REG_TEMP_UPPER 0x02 | |
43 | #define JC42_REG_TEMP_LOWER 0x03 | |
44 | #define JC42_REG_TEMP_CRITICAL 0x04 | |
45 | #define JC42_REG_TEMP 0x05 | |
46 | #define JC42_REG_MANID 0x06 | |
47 | #define JC42_REG_DEVICEID 0x07 | |
48 | ||
49 | /* Status bits in temperature register */ | |
50 | #define JC42_ALARM_CRIT_BIT 15 | |
51 | #define JC42_ALARM_MAX_BIT 14 | |
52 | #define JC42_ALARM_MIN_BIT 13 | |
53 | ||
54 | /* Configuration register defines */ | |
55 | #define JC42_CFG_CRIT_ONLY (1 << 2) | |
2c6315da CL |
56 | #define JC42_CFG_TCRIT_LOCK (1 << 6) |
57 | #define JC42_CFG_EVENT_LOCK (1 << 7) | |
4453d736 GR |
58 | #define JC42_CFG_SHUTDOWN (1 << 8) |
59 | #define JC42_CFG_HYST_SHIFT 9 | |
2ccc8731 | 60 | #define JC42_CFG_HYST_MASK (0x03 << 9) |
4453d736 GR |
61 | |
62 | /* Capabilities */ | |
63 | #define JC42_CAP_RANGE (1 << 2) | |
64 | ||
65 | /* Manufacturer IDs */ | |
66 | #define ADT_MANID 0x11d4 /* Analog Devices */ | |
1bd612a2 | 67 | #define ATMEL_MANID 0x001f /* Atmel */ |
4453d736 GR |
68 | #define MAX_MANID 0x004d /* Maxim */ |
69 | #define IDT_MANID 0x00b3 /* IDT */ | |
70 | #define MCP_MANID 0x0054 /* Microchip */ | |
71 | #define NXP_MANID 0x1131 /* NXP Semiconductors */ | |
72 | #define ONS_MANID 0x1b09 /* ON Semiconductor */ | |
73 | #define STM_MANID 0x104a /* ST Microelectronics */ | |
74 | ||
75 | /* Supported chips */ | |
76 | ||
77 | /* Analog Devices */ | |
78 | #define ADT7408_DEVID 0x0801 | |
79 | #define ADT7408_DEVID_MASK 0xffff | |
80 | ||
1bd612a2 GR |
81 | /* Atmel */ |
82 | #define AT30TS00_DEVID 0x8201 | |
83 | #define AT30TS00_DEVID_MASK 0xffff | |
84 | ||
4453d736 GR |
85 | /* IDT */ |
86 | #define TS3000B3_DEVID 0x2903 /* Also matches TSE2002B3 */ | |
87 | #define TS3000B3_DEVID_MASK 0xffff | |
88 | ||
1bd612a2 GR |
89 | #define TS3000GB2_DEVID 0x2912 /* Also matches TSE2002GB2 */ |
90 | #define TS3000GB2_DEVID_MASK 0xffff | |
91 | ||
4453d736 GR |
92 | /* Maxim */ |
93 | #define MAX6604_DEVID 0x3e00 | |
94 | #define MAX6604_DEVID_MASK 0xffff | |
95 | ||
96 | /* Microchip */ | |
1bd612a2 GR |
97 | #define MCP9804_DEVID 0x0200 |
98 | #define MCP9804_DEVID_MASK 0xfffc | |
99 | ||
4453d736 GR |
100 | #define MCP98242_DEVID 0x2000 |
101 | #define MCP98242_DEVID_MASK 0xfffc | |
102 | ||
103 | #define MCP98243_DEVID 0x2100 | |
104 | #define MCP98243_DEVID_MASK 0xfffc | |
105 | ||
d4768280 GR |
106 | #define MCP98244_DEVID 0x2200 |
107 | #define MCP98244_DEVID_MASK 0xfffc | |
108 | ||
4453d736 GR |
109 | #define MCP9843_DEVID 0x0000 /* Also matches mcp9805 */ |
110 | #define MCP9843_DEVID_MASK 0xfffe | |
111 | ||
112 | /* NXP */ | |
113 | #define SE97_DEVID 0xa200 | |
114 | #define SE97_DEVID_MASK 0xfffc | |
115 | ||
116 | #define SE98_DEVID 0xa100 | |
117 | #define SE98_DEVID_MASK 0xfffc | |
118 | ||
119 | /* ON Semiconductor */ | |
120 | #define CAT6095_DEVID 0x0800 /* Also matches CAT34TS02 */ | |
121 | #define CAT6095_DEVID_MASK 0xffe0 | |
122 | ||
123 | /* ST Microelectronics */ | |
124 | #define STTS424_DEVID 0x0101 | |
125 | #define STTS424_DEVID_MASK 0xffff | |
126 | ||
127 | #define STTS424E_DEVID 0x0000 | |
128 | #define STTS424E_DEVID_MASK 0xfffe | |
129 | ||
4de86126 JD |
130 | #define STTS2002_DEVID 0x0300 |
131 | #define STTS2002_DEVID_MASK 0xffff | |
132 | ||
133 | #define STTS3000_DEVID 0x0200 | |
134 | #define STTS3000_DEVID_MASK 0xffff | |
135 | ||
4453d736 GR |
136 | static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 }; |
137 | ||
138 | struct jc42_chips { | |
139 | u16 manid; | |
140 | u16 devid; | |
141 | u16 devid_mask; | |
142 | }; | |
143 | ||
144 | static struct jc42_chips jc42_chips[] = { | |
145 | { ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK }, | |
1bd612a2 | 146 | { ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK }, |
4453d736 | 147 | { IDT_MANID, TS3000B3_DEVID, TS3000B3_DEVID_MASK }, |
1bd612a2 | 148 | { IDT_MANID, TS3000GB2_DEVID, TS3000GB2_DEVID_MASK }, |
4453d736 | 149 | { MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK }, |
1bd612a2 | 150 | { MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK }, |
4453d736 GR |
151 | { MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK }, |
152 | { MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK }, | |
d4768280 | 153 | { MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK }, |
4453d736 GR |
154 | { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK }, |
155 | { NXP_MANID, SE97_DEVID, SE97_DEVID_MASK }, | |
156 | { ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK }, | |
157 | { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK }, | |
158 | { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK }, | |
159 | { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK }, | |
4de86126 JD |
160 | { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK }, |
161 | { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK }, | |
4453d736 GR |
162 | }; |
163 | ||
164 | /* Each client has this additional data */ | |
165 | struct jc42_data { | |
62f9a57c | 166 | struct i2c_client *client; |
4453d736 GR |
167 | struct mutex update_lock; /* protect register access */ |
168 | bool extended; /* true if extended range supported */ | |
169 | bool valid; | |
170 | unsigned long last_updated; /* In jiffies */ | |
171 | u16 orig_config; /* original configuration */ | |
172 | u16 config; /* current configuration */ | |
173 | u16 temp_input; /* Temperatures */ | |
174 | u16 temp_crit; | |
175 | u16 temp_min; | |
176 | u16 temp_max; | |
177 | }; | |
178 | ||
179 | static int jc42_probe(struct i2c_client *client, | |
180 | const struct i2c_device_id *id); | |
181 | static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info); | |
182 | static int jc42_remove(struct i2c_client *client); | |
4453d736 GR |
183 | |
184 | static struct jc42_data *jc42_update_device(struct device *dev); | |
185 | ||
186 | static const struct i2c_device_id jc42_id[] = { | |
4453d736 | 187 | { "jc42", 0 }, |
4453d736 GR |
188 | { } |
189 | }; | |
190 | MODULE_DEVICE_TABLE(i2c, jc42_id); | |
191 | ||
192 | #ifdef CONFIG_PM | |
193 | ||
194 | static int jc42_suspend(struct device *dev) | |
195 | { | |
62f9a57c | 196 | struct jc42_data *data = dev_get_drvdata(dev); |
4453d736 GR |
197 | |
198 | data->config |= JC42_CFG_SHUTDOWN; | |
62f9a57c GR |
199 | i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG, |
200 | data->config); | |
4453d736 GR |
201 | return 0; |
202 | } | |
203 | ||
204 | static int jc42_resume(struct device *dev) | |
205 | { | |
62f9a57c | 206 | struct jc42_data *data = dev_get_drvdata(dev); |
4453d736 GR |
207 | |
208 | data->config &= ~JC42_CFG_SHUTDOWN; | |
62f9a57c GR |
209 | i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG, |
210 | data->config); | |
4453d736 GR |
211 | return 0; |
212 | } | |
213 | ||
214 | static const struct dev_pm_ops jc42_dev_pm_ops = { | |
215 | .suspend = jc42_suspend, | |
216 | .resume = jc42_resume, | |
217 | }; | |
218 | ||
219 | #define JC42_DEV_PM_OPS (&jc42_dev_pm_ops) | |
220 | #else | |
221 | #define JC42_DEV_PM_OPS NULL | |
222 | #endif /* CONFIG_PM */ | |
223 | ||
224 | /* This is the driver that will be inserted */ | |
225 | static struct i2c_driver jc42_driver = { | |
774466ad | 226 | .class = I2C_CLASS_SPD, |
4453d736 GR |
227 | .driver = { |
228 | .name = "jc42", | |
229 | .pm = JC42_DEV_PM_OPS, | |
230 | }, | |
231 | .probe = jc42_probe, | |
232 | .remove = jc42_remove, | |
233 | .id_table = jc42_id, | |
234 | .detect = jc42_detect, | |
235 | .address_list = normal_i2c, | |
236 | }; | |
237 | ||
238 | #define JC42_TEMP_MIN_EXTENDED (-40000) | |
239 | #define JC42_TEMP_MIN 0 | |
240 | #define JC42_TEMP_MAX 125000 | |
241 | ||
242 | static u16 jc42_temp_to_reg(int temp, bool extended) | |
243 | { | |
2a844c14 GR |
244 | int ntemp = clamp_val(temp, |
245 | extended ? JC42_TEMP_MIN_EXTENDED : | |
246 | JC42_TEMP_MIN, JC42_TEMP_MAX); | |
4453d736 GR |
247 | |
248 | /* convert from 0.001 to 0.0625 resolution */ | |
249 | return (ntemp * 2 / 125) & 0x1fff; | |
250 | } | |
251 | ||
252 | static int jc42_temp_from_reg(s16 reg) | |
253 | { | |
254 | reg &= 0x1fff; | |
255 | ||
256 | /* sign extend register */ | |
257 | if (reg & 0x1000) | |
258 | reg |= 0xf000; | |
259 | ||
260 | /* convert from 0.0625 to 0.001 resolution */ | |
261 | return reg * 125 / 2; | |
262 | } | |
263 | ||
264 | /* sysfs stuff */ | |
265 | ||
266 | /* read routines for temperature limits */ | |
267 | #define show(value) \ | |
268 | static ssize_t show_##value(struct device *dev, \ | |
269 | struct device_attribute *attr, \ | |
270 | char *buf) \ | |
271 | { \ | |
272 | struct jc42_data *data = jc42_update_device(dev); \ | |
273 | if (IS_ERR(data)) \ | |
274 | return PTR_ERR(data); \ | |
275 | return sprintf(buf, "%d\n", jc42_temp_from_reg(data->value)); \ | |
276 | } | |
277 | ||
278 | show(temp_input); | |
279 | show(temp_crit); | |
280 | show(temp_min); | |
281 | show(temp_max); | |
282 | ||
283 | /* read routines for hysteresis values */ | |
284 | static ssize_t show_temp_crit_hyst(struct device *dev, | |
285 | struct device_attribute *attr, char *buf) | |
286 | { | |
287 | struct jc42_data *data = jc42_update_device(dev); | |
288 | int temp, hyst; | |
289 | ||
290 | if (IS_ERR(data)) | |
291 | return PTR_ERR(data); | |
292 | ||
293 | temp = jc42_temp_from_reg(data->temp_crit); | |
2ccc8731 JD |
294 | hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK) |
295 | >> JC42_CFG_HYST_SHIFT]; | |
4453d736 GR |
296 | return sprintf(buf, "%d\n", temp - hyst); |
297 | } | |
298 | ||
299 | static ssize_t show_temp_max_hyst(struct device *dev, | |
300 | struct device_attribute *attr, char *buf) | |
301 | { | |
302 | struct jc42_data *data = jc42_update_device(dev); | |
303 | int temp, hyst; | |
304 | ||
305 | if (IS_ERR(data)) | |
306 | return PTR_ERR(data); | |
307 | ||
308 | temp = jc42_temp_from_reg(data->temp_max); | |
2ccc8731 JD |
309 | hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK) |
310 | >> JC42_CFG_HYST_SHIFT]; | |
4453d736 GR |
311 | return sprintf(buf, "%d\n", temp - hyst); |
312 | } | |
313 | ||
314 | /* write routines */ | |
315 | #define set(value, reg) \ | |
316 | static ssize_t set_##value(struct device *dev, \ | |
317 | struct device_attribute *attr, \ | |
318 | const char *buf, size_t count) \ | |
319 | { \ | |
62f9a57c | 320 | struct jc42_data *data = dev_get_drvdata(dev); \ |
4453d736 GR |
321 | int err, ret = count; \ |
322 | long val; \ | |
62f9a57c | 323 | if (kstrtol(buf, 10, &val) < 0) \ |
4453d736 GR |
324 | return -EINVAL; \ |
325 | mutex_lock(&data->update_lock); \ | |
326 | data->value = jc42_temp_to_reg(val, data->extended); \ | |
62f9a57c | 327 | err = i2c_smbus_write_word_swapped(data->client, reg, data->value); \ |
4453d736 GR |
328 | if (err < 0) \ |
329 | ret = err; \ | |
330 | mutex_unlock(&data->update_lock); \ | |
331 | return ret; \ | |
332 | } | |
333 | ||
334 | set(temp_min, JC42_REG_TEMP_LOWER); | |
335 | set(temp_max, JC42_REG_TEMP_UPPER); | |
336 | set(temp_crit, JC42_REG_TEMP_CRITICAL); | |
337 | ||
5d577dba GR |
338 | /* |
339 | * JC42.4 compliant chips only support four hysteresis values. | |
340 | * Pick best choice and go from there. | |
341 | */ | |
4453d736 GR |
342 | static ssize_t set_temp_crit_hyst(struct device *dev, |
343 | struct device_attribute *attr, | |
344 | const char *buf, size_t count) | |
345 | { | |
62f9a57c | 346 | struct jc42_data *data = dev_get_drvdata(dev); |
e8667296 | 347 | unsigned long val; |
4453d736 GR |
348 | int diff, hyst; |
349 | int err; | |
350 | int ret = count; | |
351 | ||
179c4fdb | 352 | if (kstrtoul(buf, 10, &val) < 0) |
4453d736 GR |
353 | return -EINVAL; |
354 | ||
355 | diff = jc42_temp_from_reg(data->temp_crit) - val; | |
356 | hyst = 0; | |
357 | if (diff > 0) { | |
358 | if (diff < 2250) | |
359 | hyst = 1; /* 1.5 degrees C */ | |
360 | else if (diff < 4500) | |
361 | hyst = 2; /* 3.0 degrees C */ | |
362 | else | |
363 | hyst = 3; /* 6.0 degrees C */ | |
364 | } | |
365 | ||
366 | mutex_lock(&data->update_lock); | |
2ccc8731 | 367 | data->config = (data->config & ~JC42_CFG_HYST_MASK) |
4453d736 | 368 | | (hyst << JC42_CFG_HYST_SHIFT); |
62f9a57c | 369 | err = i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG, |
90f4102c | 370 | data->config); |
4453d736 GR |
371 | if (err < 0) |
372 | ret = err; | |
373 | mutex_unlock(&data->update_lock); | |
374 | return ret; | |
375 | } | |
376 | ||
377 | static ssize_t show_alarm(struct device *dev, | |
378 | struct device_attribute *attr, char *buf) | |
379 | { | |
380 | u16 bit = to_sensor_dev_attr(attr)->index; | |
381 | struct jc42_data *data = jc42_update_device(dev); | |
382 | u16 val; | |
383 | ||
384 | if (IS_ERR(data)) | |
385 | return PTR_ERR(data); | |
386 | ||
387 | val = data->temp_input; | |
388 | if (bit != JC42_ALARM_CRIT_BIT && (data->config & JC42_CFG_CRIT_ONLY)) | |
389 | val = 0; | |
390 | return sprintf(buf, "%u\n", (val >> bit) & 1); | |
391 | } | |
392 | ||
393 | static DEVICE_ATTR(temp1_input, S_IRUGO, | |
394 | show_temp_input, NULL); | |
2c6315da | 395 | static DEVICE_ATTR(temp1_crit, S_IRUGO, |
4453d736 | 396 | show_temp_crit, set_temp_crit); |
2c6315da | 397 | static DEVICE_ATTR(temp1_min, S_IRUGO, |
4453d736 | 398 | show_temp_min, set_temp_min); |
2c6315da | 399 | static DEVICE_ATTR(temp1_max, S_IRUGO, |
4453d736 GR |
400 | show_temp_max, set_temp_max); |
401 | ||
2c6315da | 402 | static DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, |
4453d736 GR |
403 | show_temp_crit_hyst, set_temp_crit_hyst); |
404 | static DEVICE_ATTR(temp1_max_hyst, S_IRUGO, | |
405 | show_temp_max_hyst, NULL); | |
406 | ||
407 | static SENSOR_DEVICE_ATTR(temp1_crit_alarm, S_IRUGO, show_alarm, NULL, | |
408 | JC42_ALARM_CRIT_BIT); | |
409 | static SENSOR_DEVICE_ATTR(temp1_min_alarm, S_IRUGO, show_alarm, NULL, | |
410 | JC42_ALARM_MIN_BIT); | |
411 | static SENSOR_DEVICE_ATTR(temp1_max_alarm, S_IRUGO, show_alarm, NULL, | |
412 | JC42_ALARM_MAX_BIT); | |
413 | ||
414 | static struct attribute *jc42_attributes[] = { | |
415 | &dev_attr_temp1_input.attr, | |
416 | &dev_attr_temp1_crit.attr, | |
417 | &dev_attr_temp1_min.attr, | |
418 | &dev_attr_temp1_max.attr, | |
419 | &dev_attr_temp1_crit_hyst.attr, | |
420 | &dev_attr_temp1_max_hyst.attr, | |
421 | &sensor_dev_attr_temp1_crit_alarm.dev_attr.attr, | |
422 | &sensor_dev_attr_temp1_min_alarm.dev_attr.attr, | |
423 | &sensor_dev_attr_temp1_max_alarm.dev_attr.attr, | |
424 | NULL | |
425 | }; | |
426 | ||
587a1f16 | 427 | static umode_t jc42_attribute_mode(struct kobject *kobj, |
2c6315da CL |
428 | struct attribute *attr, int index) |
429 | { | |
430 | struct device *dev = container_of(kobj, struct device, kobj); | |
62f9a57c | 431 | struct jc42_data *data = dev_get_drvdata(dev); |
2c6315da CL |
432 | unsigned int config = data->config; |
433 | bool readonly; | |
434 | ||
435 | if (attr == &dev_attr_temp1_crit.attr) | |
436 | readonly = config & JC42_CFG_TCRIT_LOCK; | |
437 | else if (attr == &dev_attr_temp1_min.attr || | |
438 | attr == &dev_attr_temp1_max.attr) | |
439 | readonly = config & JC42_CFG_EVENT_LOCK; | |
440 | else if (attr == &dev_attr_temp1_crit_hyst.attr) | |
441 | readonly = config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK); | |
442 | else | |
443 | readonly = true; | |
444 | ||
445 | return S_IRUGO | (readonly ? 0 : S_IWUSR); | |
446 | } | |
447 | ||
4453d736 GR |
448 | static const struct attribute_group jc42_group = { |
449 | .attrs = jc42_attributes, | |
2c6315da | 450 | .is_visible = jc42_attribute_mode, |
4453d736 | 451 | }; |
62f9a57c | 452 | __ATTRIBUTE_GROUPS(jc42); |
4453d736 GR |
453 | |
454 | /* Return 0 if detection is successful, -ENODEV otherwise */ | |
f15df57d | 455 | static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info) |
4453d736 | 456 | { |
f15df57d | 457 | struct i2c_adapter *adapter = client->adapter; |
4453d736 GR |
458 | int i, config, cap, manid, devid; |
459 | ||
460 | if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | | |
461 | I2C_FUNC_SMBUS_WORD_DATA)) | |
462 | return -ENODEV; | |
463 | ||
f15df57d GR |
464 | cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP); |
465 | config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG); | |
466 | manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID); | |
467 | devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID); | |
4453d736 GR |
468 | |
469 | if (cap < 0 || config < 0 || manid < 0 || devid < 0) | |
470 | return -ENODEV; | |
471 | ||
472 | if ((cap & 0xff00) || (config & 0xf800)) | |
473 | return -ENODEV; | |
474 | ||
475 | for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) { | |
476 | struct jc42_chips *chip = &jc42_chips[i]; | |
477 | if (manid == chip->manid && | |
478 | (devid & chip->devid_mask) == chip->devid) { | |
479 | strlcpy(info->type, "jc42", I2C_NAME_SIZE); | |
480 | return 0; | |
481 | } | |
482 | } | |
483 | return -ENODEV; | |
484 | } | |
485 | ||
f15df57d | 486 | static int jc42_probe(struct i2c_client *client, const struct i2c_device_id *id) |
4453d736 | 487 | { |
f15df57d | 488 | struct device *dev = &client->dev; |
62f9a57c GR |
489 | struct device *hwmon_dev; |
490 | struct jc42_data *data; | |
491 | int config, cap; | |
4453d736 | 492 | |
f15df57d GR |
493 | data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL); |
494 | if (!data) | |
495 | return -ENOMEM; | |
4453d736 | 496 | |
62f9a57c | 497 | data->client = client; |
f15df57d | 498 | i2c_set_clientdata(client, data); |
4453d736 GR |
499 | mutex_init(&data->update_lock); |
500 | ||
f15df57d GR |
501 | cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP); |
502 | if (cap < 0) | |
503 | return cap; | |
504 | ||
4453d736 GR |
505 | data->extended = !!(cap & JC42_CAP_RANGE); |
506 | ||
f15df57d GR |
507 | config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG); |
508 | if (config < 0) | |
509 | return config; | |
510 | ||
4453d736 GR |
511 | data->orig_config = config; |
512 | if (config & JC42_CFG_SHUTDOWN) { | |
513 | config &= ~JC42_CFG_SHUTDOWN; | |
f15df57d | 514 | i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config); |
4453d736 GR |
515 | } |
516 | data->config = config; | |
517 | ||
62f9a57c GR |
518 | hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name, |
519 | data, | |
520 | jc42_groups); | |
650a2c02 | 521 | return PTR_ERR_OR_ZERO(hwmon_dev); |
4453d736 GR |
522 | } |
523 | ||
524 | static int jc42_remove(struct i2c_client *client) | |
525 | { | |
526 | struct jc42_data *data = i2c_get_clientdata(client); | |
5953e276 JD |
527 | |
528 | /* Restore original configuration except hysteresis */ | |
529 | if ((data->config & ~JC42_CFG_HYST_MASK) != | |
530 | (data->orig_config & ~JC42_CFG_HYST_MASK)) { | |
531 | int config; | |
532 | ||
533 | config = (data->orig_config & ~JC42_CFG_HYST_MASK) | |
534 | | (data->config & JC42_CFG_HYST_MASK); | |
535 | i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config); | |
536 | } | |
4453d736 GR |
537 | return 0; |
538 | } | |
539 | ||
4453d736 GR |
540 | static struct jc42_data *jc42_update_device(struct device *dev) |
541 | { | |
62f9a57c GR |
542 | struct jc42_data *data = dev_get_drvdata(dev); |
543 | struct i2c_client *client = data->client; | |
4453d736 GR |
544 | struct jc42_data *ret = data; |
545 | int val; | |
546 | ||
547 | mutex_lock(&data->update_lock); | |
548 | ||
549 | if (time_after(jiffies, data->last_updated + HZ) || !data->valid) { | |
90f4102c | 550 | val = i2c_smbus_read_word_swapped(client, JC42_REG_TEMP); |
4453d736 GR |
551 | if (val < 0) { |
552 | ret = ERR_PTR(val); | |
553 | goto abort; | |
554 | } | |
555 | data->temp_input = val; | |
556 | ||
90f4102c JD |
557 | val = i2c_smbus_read_word_swapped(client, |
558 | JC42_REG_TEMP_CRITICAL); | |
4453d736 GR |
559 | if (val < 0) { |
560 | ret = ERR_PTR(val); | |
561 | goto abort; | |
562 | } | |
563 | data->temp_crit = val; | |
564 | ||
90f4102c | 565 | val = i2c_smbus_read_word_swapped(client, JC42_REG_TEMP_LOWER); |
4453d736 GR |
566 | if (val < 0) { |
567 | ret = ERR_PTR(val); | |
568 | goto abort; | |
569 | } | |
570 | data->temp_min = val; | |
571 | ||
90f4102c | 572 | val = i2c_smbus_read_word_swapped(client, JC42_REG_TEMP_UPPER); |
4453d736 GR |
573 | if (val < 0) { |
574 | ret = ERR_PTR(val); | |
575 | goto abort; | |
576 | } | |
577 | data->temp_max = val; | |
578 | ||
579 | data->last_updated = jiffies; | |
580 | data->valid = true; | |
581 | } | |
582 | abort: | |
583 | mutex_unlock(&data->update_lock); | |
584 | return ret; | |
585 | } | |
586 | ||
f0967eea | 587 | module_i2c_driver(jc42_driver); |
4453d736 | 588 | |
bb9a80e5 | 589 | MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>"); |
4453d736 GR |
590 | MODULE_DESCRIPTION("JC42 driver"); |
591 | MODULE_LICENSE("GPL"); |