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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/kaber/nf-2.6
[deliverable/linux.git] / drivers / hwmon / w83627ehf.c
CommitLineData
08e7e278
JD		 1/*
2 w83627ehf - Driver for the hardware monitoring functionality of
3 the Winbond W83627EHF Super-I/O chip
4 Copyright (C) 2005 Jean Delvare <khali@linux-fr.org>
3379ceee 5 Copyright (C) 2006 Yuan Mu (Winbond),
7188cc66 6 Rudolf Marek <r.marek@assembler.cz>
c18beb5b 7 David Hubbard <david.c.hubbard@gmail.com>
41e9a062 8 Daniel J Blueman <daniel.blueman@gmail.com>
08e7e278
JD		 9
10 Shamelessly ripped from the w83627hf driver
11 Copyright (C) 2003 Mark Studebaker
12
13 Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
14 in testing and debugging this driver.
15
8dd2d2ca
JD		 16 This driver also supports the W83627EHG, which is the lead-free
17 version of the W83627EHF.
18
08e7e278
JD		 19 This program is free software; you can redistribute it and/or modify
20 it under the terms of the GNU General Public License as published by
21 the Free Software Foundation; either version 2 of the License, or
22 (at your option) any later version.
23
24 This program is distributed in the hope that it will be useful,
25 but WITHOUT ANY WARRANTY; without even the implied warranty of
26 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 GNU General Public License for more details.
28
29 You should have received a copy of the GNU General Public License
30 along with this program; if not, write to the Free Software
31 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32
33
34 Supports the following chips:
35
657c93b1
DH		 36 Chip #vin #fan #pwm #temp chip IDs man ID
37 w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
38 0x8860 0xa1
39 w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
c1e48dce 40 w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
237c8d2f 41 w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
c39aedaf 42 w83667hg-b 9 5 3 3 0xb350 0xc1 0x5ca3
08e7e278
JD		 43*/
44
abdc6fd1
JP		 45#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
46
08e7e278
JD		 47#include <linux/module.h>
48#include <linux/init.h>
49#include <linux/slab.h>
1ea6dd38
DH		 50#include <linux/jiffies.h>
51#include <linux/platform_device.h>
943b0830 52#include <linux/hwmon.h>
412fec82 53#include <linux/hwmon-sysfs.h>
fc18d6c0 54#include <linux/hwmon-vid.h>
943b0830 55#include <linux/err.h>
9a61bf63 56#include <linux/mutex.h>
b9acb64a 57#include <linux/acpi.h>
6055fae8 58#include <linux/io.h>
08e7e278
JD		 59#include "lm75.h"
60
c39aedaf 61enum kinds { w83627ehf, w83627dhg, w83627dhg_p, w83667hg, w83667hg_b };
08e7e278 62
1ea6dd38
DH		 63/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
64static const char * w83627ehf_device_names[] = {
65 "w83627ehf",
66 "w83627dhg",
c1e48dce 67 "w83627dhg",
237c8d2f 68 "w83667hg",
c39aedaf 69 "w83667hg",
1ea6dd38
DH		 70};
71
67b671bc
JD		 72static unsigned short force_id;
73module_param(force_id, ushort, 0);
74MODULE_PARM_DESC(force_id, "Override the detected device ID");
75
1ea6dd38 76#define DRVNAME "w83627ehf"
08e7e278 77
657c93b1 78/*
1ea6dd38 79 * Super-I/O constants and functions
657c93b1 80 */
08e7e278
JD		 81
82#define W83627EHF_LD_HWM 0x0b
237c8d2f 83#define W83667HG_LD_VID 0x0d
08e7e278
JD		 84
85#define SIO_REG_LDSEL 0x07 /* Logical device select */
86#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
fc18d6c0 87#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
08e7e278
JD		 88#define SIO_REG_ENABLE 0x30 /* Logical device enable */
89#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
fc18d6c0
JD		 90#define SIO_REG_VID_CTRL 0xF0 /* VID control */
91#define SIO_REG_VID_DATA 0xF1 /* VID data */
08e7e278 92
657c93b1
DH		 93#define SIO_W83627EHF_ID 0x8850
94#define SIO_W83627EHG_ID 0x8860
95#define SIO_W83627DHG_ID 0xa020
c1e48dce 96#define SIO_W83627DHG_P_ID 0xb070
237c8d2f 97#define SIO_W83667HG_ID 0xa510
c39aedaf 98#define SIO_W83667HG_B_ID 0xb350
657c93b1 99#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 100
101static inline void
1ea6dd38 102superio_outb(int ioreg, int reg, int val)
08e7e278 103{
1ea6dd38
DH		 104 outb(reg, ioreg);
105 outb(val, ioreg + 1);
08e7e278
JD		 106}
107
108static inline int
1ea6dd38 109superio_inb(int ioreg, int reg)
08e7e278 110{
1ea6dd38
DH		 111 outb(reg, ioreg);
112 return inb(ioreg + 1);
08e7e278
JD		 113}
114
115static inline void
1ea6dd38 116superio_select(int ioreg, int ld)
08e7e278 117{
1ea6dd38
DH		 118 outb(SIO_REG_LDSEL, ioreg);
119 outb(ld, ioreg + 1);
08e7e278
JD		 120}
121
122static inline void
1ea6dd38 123superio_enter(int ioreg)
08e7e278 124{
1ea6dd38
DH		 125 outb(0x87, ioreg);
126 outb(0x87, ioreg);
08e7e278
JD		 127}
128
129static inline void
1ea6dd38 130superio_exit(int ioreg)
08e7e278 131{
022b75a3 132 outb(0xaa, ioreg);
1ea6dd38
DH		 133 outb(0x02, ioreg);
134 outb(0x02, ioreg + 1);
08e7e278
JD		 135}
136
137/*
138 * ISA constants
139 */
140
1a641fce
JD		 141#define IOREGION_ALIGNMENT ~7
142#define IOREGION_OFFSET 5
143#define IOREGION_LENGTH 2
1ea6dd38
DH		 144#define ADDR_REG_OFFSET 0
145#define DATA_REG_OFFSET 1
08e7e278
JD		 146
147#define W83627EHF_REG_BANK 0x4E
148#define W83627EHF_REG_CONFIG 0x40
657c93b1
DH		 149
150/* Not currently used:
151 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
152 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
153 * REG_MAN_ID is at port 0x4f
154 * REG_CHIP_ID is at port 0x58 */
08e7e278
JD		 155
156static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
157static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
158
cf0676fe
RM		 159/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
160#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
161 (0x554 + (((nr) - 7) * 2)))
162#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
163 (0x555 + (((nr) - 7) * 2)))
164#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
165 (0x550 + (nr) - 7))
166
08e7e278
JD		 167#define W83627EHF_REG_TEMP1 0x27
168#define W83627EHF_REG_TEMP1_HYST 0x3a
169#define W83627EHF_REG_TEMP1_OVER 0x39
170static const u16 W83627EHF_REG_TEMP[] = { 0x150, 0x250 };
171static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x153, 0x253 };
172static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x155, 0x255 };
173static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0x152, 0x252 };
174
175/* Fan clock dividers are spread over the following five registers */
176#define W83627EHF_REG_FANDIV1 0x47
177#define W83627EHF_REG_FANDIV2 0x4B
178#define W83627EHF_REG_VBAT 0x5D
179#define W83627EHF_REG_DIODE 0x59
180#define W83627EHF_REG_SMI_OVT 0x4C
181
a4589dbb
JD		 182#define W83627EHF_REG_ALARM1 0x459
183#define W83627EHF_REG_ALARM2 0x45A
184#define W83627EHF_REG_ALARM3 0x45B
185
08c79950 186/* SmartFan registers */
41e9a062
DB		 187#define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
188#define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
189
08c79950
RM		 190/* DC or PWM output fan configuration */
191static const u8 W83627EHF_REG_PWM_ENABLE[] = {
192 0x04, /* SYS FAN0 output mode and PWM mode */
193 0x04, /* CPU FAN0 output mode and PWM mode */
194 0x12, /* AUX FAN mode */
41e9a062 195 0x62, /* CPU FAN1 mode */
08c79950
RM		 196};
197
198static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
199static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
200
201/* FAN Duty Cycle, be used to control */
202static const u8 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
203static const u8 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
204static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
205
08c79950 206/* Advanced Fan control, some values are common for all fans */
41e9a062
DB		 207static const u8 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
208static const u8 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
209static const u8 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
c39aedaf
GR		 210
211static const u8 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
212 = { 0xff, 0x67, 0xff, 0x69 };
213static const u8 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
214 = { 0xff, 0x68, 0xff, 0x6a };
215
216static const u8 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
217static const u8 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[] = { 0x68, 0x6a, 0x6c };
08c79950 218
08e7e278
JD		 219/*
220 * Conversions
221 */
222
08c79950
RM		 223/* 1 is PWM mode, output in ms */
224static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
225{
226 return mode ? 100 * reg : 400 * reg;
227}
228
229static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
230{
231 return SENSORS_LIMIT((mode ? (msec + 50) / 100 :
232 (msec + 200) / 400), 1, 255);
233}
234
08e7e278
JD		 235static inline unsigned int
236fan_from_reg(u8 reg, unsigned int div)
237{
238 if (reg == 0 || reg == 255)
239 return 0;
240 return 1350000U / (reg * div);
241}
242
243static inline unsigned int
244div_from_reg(u8 reg)
245{
246 return 1 << reg;
247}
248
249static inline int
250temp1_from_reg(s8 reg)
251{
252 return reg * 1000;
253}
254
255static inline s8
5bfedac0 256temp1_to_reg(long temp, int min, int max)
08e7e278 257{
08c79950
RM		 258 if (temp <= min)
259 return min / 1000;
260 if (temp >= max)
261 return max / 1000;
08e7e278
JD		 262 if (temp < 0)
263 return (temp - 500) / 1000;
264 return (temp + 500) / 1000;
265}
266
cf0676fe
RM		 267/* Some of analog inputs have internal scaling (2x), 8mV is ADC LSB */
268
269static u8 scale_in[10] = { 8, 8, 16, 16, 8, 8, 8, 16, 16, 8 };
270
271static inline long in_from_reg(u8 reg, u8 nr)
272{
273 return reg * scale_in[nr];
274}
275
276static inline u8 in_to_reg(u32 val, u8 nr)
277{
278 return SENSORS_LIMIT(((val + (scale_in[nr] / 2)) / scale_in[nr]), 0, 255);
279}
280
08e7e278
JD		 281/*
282 * Data structures and manipulation thereof
283 */
284
285struct w83627ehf_data {
1ea6dd38
DH		 286 int addr; /* IO base of hw monitor block */
287 const char *name;
288
1beeffe4 289 struct device *hwmon_dev;
9a61bf63 290 struct mutex lock;
08e7e278 291
da2e0255
GR		 292 const u8 *REG_FAN_START_OUTPUT;
293 const u8 *REG_FAN_STOP_OUTPUT;
294 const u8 *REG_FAN_MAX_OUTPUT;
295 const u8 *REG_FAN_STEP_OUTPUT;
296
9a61bf63 297 struct mutex update_lock;
08e7e278
JD		 298 char valid; /* !=0 if following fields are valid */
299 unsigned long last_updated; /* In jiffies */
300
301 /* Register values */
1ea6dd38 302 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 303 u8 in[10]; /* Register value */
304 u8 in_max[10]; /* Register value */
305 u8 in_min[10]; /* Register value */
08e7e278
JD		 306 u8 fan[5];
307 u8 fan_min[5];
308 u8 fan_div[5];
309 u8 has_fan; /* some fan inputs can be disabled */
da667365 310 u8 temp_type[3];
08e7e278
JD		 311 s8 temp1;
312 s8 temp1_max;
313 s8 temp1_max_hyst;
314 s16 temp[2];
315 s16 temp_max[2];
316 s16 temp_max_hyst[2];
a4589dbb 317 u32 alarms;
08c79950
RM		 318
319 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
320 u8 pwm_enable[4]; /* 1->manual
41e9a062
DB		 321 2->thermal cruise mode (also called SmartFan I)
322 3->fan speed cruise mode
323 4->variable thermal cruise (also called SmartFan III) */
237c8d2f 324 u8 pwm_num; /* number of pwm */
08c79950
RM		 325 u8 pwm[4];
326 u8 target_temp[4];
327 u8 tolerance[4];
328
41e9a062
DB		 329 u8 fan_start_output[4]; /* minimum fan speed when spinning up */
330 u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
331 u8 fan_stop_time[4]; /* time at minimum before disabling fan */
332 u8 fan_max_output[4]; /* maximum fan speed */
333 u8 fan_step_output[4]; /* rate of change output value */
fc18d6c0
JD		 334
335 u8 vid;
336 u8 vrm;
a157d06d
GJ		 337
338 u8 temp3_disable;
339 u8 in6_skip;
08e7e278
JD		 340};
341
1ea6dd38
DH		 342struct w83627ehf_sio_data {
343 int sioreg;
344 enum kinds kind;
345};
346
08e7e278
JD		 347static inline int is_word_sized(u16 reg)
348{
349 return (((reg & 0xff00) == 0x100
350 || (reg & 0xff00) == 0x200)
351 && ((reg & 0x00ff) == 0x50
352 || (reg & 0x00ff) == 0x53
353 || (reg & 0x00ff) == 0x55));
354}
355
0956895a 356/* Registers 0x50-0x5f are banked */
1ea6dd38 357static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278 358{
0956895a 359 if ((reg & 0x00f0) == 0x50) {
1ea6dd38
DH		 360 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
361 outb_p(reg >> 8, data->addr + DATA_REG_OFFSET);
08e7e278
JD		 362 }
363}
364
0956895a 365/* Not strictly necessary, but play it safe for now */
1ea6dd38 366static inline void w83627ehf_reset_bank(struct w83627ehf_data *data, u16 reg)
08e7e278
JD		 367{
368 if (reg & 0xff00) {
1ea6dd38
DH		 369 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
370 outb_p(0, data->addr + DATA_REG_OFFSET);
08e7e278
JD		 371 }
372}
373
1ea6dd38 374static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 375{
08e7e278
JD		 376 int res, word_sized = is_word_sized(reg);
377
9a61bf63 378 mutex_lock(&data->lock);
08e7e278 379
1ea6dd38
DH		 380 w83627ehf_set_bank(data, reg);
381 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
382 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 383 if (word_sized) {
384 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 385 data->addr + ADDR_REG_OFFSET);
386 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 387 }
1ea6dd38 388 w83627ehf_reset_bank(data, reg);
08e7e278 389
9a61bf63 390 mutex_unlock(&data->lock);
08e7e278
JD		 391
392 return res;
393}
394
1ea6dd38 395static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg, u16 value)
08e7e278 396{
08e7e278
JD		 397 int word_sized = is_word_sized(reg);
398
9a61bf63 399 mutex_lock(&data->lock);
08e7e278 400
1ea6dd38
DH		 401 w83627ehf_set_bank(data, reg);
402 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 403 if (word_sized) {
1ea6dd38 404 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 405 outb_p((reg & 0xff) + 1,
1ea6dd38 406 data->addr + ADDR_REG_OFFSET);
08e7e278 407 }
1ea6dd38
DH		 408 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
409 w83627ehf_reset_bank(data, reg);
08e7e278 410
9a61bf63 411 mutex_unlock(&data->lock);
08e7e278
JD		 412 return 0;
413}
414
415/* This function assumes that the caller holds data->update_lock */
1ea6dd38 416static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 417{
08e7e278
JD		 418 u8 reg;
419
420 switch (nr) {
421 case 0:
1ea6dd38 422 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 423 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 424 /* fan5 input control bit is write only, compute the value */
425 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 426 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
427 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 428 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 429 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 430 break;
431 case 1:
1ea6dd38 432 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 433 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 434 /* fan5 input control bit is write only, compute the value */
435 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 436 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
437 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 438 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 439 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 440 break;
441 case 2:
1ea6dd38 442 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 443 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 444 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
445 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 446 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 447 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 448 break;
449 case 3:
1ea6dd38 450 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 451 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 452 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
453 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 454 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 455 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 456 break;
457 case 4:
1ea6dd38 458 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 459 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 460 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 461 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 462 break;
463 }
464}
465
ea7be66c
MH		 466static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
467{
468 int i;
469
470 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
471 data->fan_div[0] = (i >> 4) & 0x03;
472 data->fan_div[1] = (i >> 6) & 0x03;
473 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
474 data->fan_div[2] = (i >> 6) & 0x03;
475 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
476 data->fan_div[0] |= (i >> 3) & 0x04;
477 data->fan_div[1] |= (i >> 4) & 0x04;
478 data->fan_div[2] |= (i >> 5) & 0x04;
479 if (data->has_fan & ((1 << 3) | (1 << 4))) {
480 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
481 data->fan_div[3] = i & 0x03;
482 data->fan_div[4] = ((i >> 2) & 0x03)
483 | ((i >> 5) & 0x04);
484 }
485 if (data->has_fan & (1 << 3)) {
486 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
487 data->fan_div[3] |= (i >> 5) & 0x04;
488 }
489}
490
08e7e278
JD		 491static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
492{
1ea6dd38 493 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950 494 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
08e7e278
JD		 495 int i;
496
9a61bf63 497 mutex_lock(&data->update_lock);
08e7e278 498
6b3e4645 499 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
08e7e278
JD		 500 || !data->valid) {
501 /* Fan clock dividers */
ea7be66c 502 w83627ehf_update_fan_div(data);
08e7e278 503
cf0676fe 504 /* Measured voltages and limits */
1ea6dd38
DH		 505 for (i = 0; i < data->in_num; i++) {
506 data->in[i] = w83627ehf_read_value(data,
cf0676fe 507 W83627EHF_REG_IN(i));
1ea6dd38 508 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 509 W83627EHF_REG_IN_MIN(i));
1ea6dd38 510 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 511 W83627EHF_REG_IN_MAX(i));
512 }
513
08e7e278
JD		 514 /* Measured fan speeds and limits */
515 for (i = 0; i < 5; i++) {
516 if (!(data->has_fan & (1 << i)))
517 continue;
518
1ea6dd38 519 data->fan[i] = w83627ehf_read_value(data,
08e7e278 520 W83627EHF_REG_FAN[i]);
1ea6dd38 521 data->fan_min[i] = w83627ehf_read_value(data,
08e7e278
JD		 522 W83627EHF_REG_FAN_MIN[i]);
523
524 /* If we failed to measure the fan speed and clock
525 divider can be increased, let's try that for next
526 time */
527 if (data->fan[i] == 0xff
528 && data->fan_div[i] < 0x07) {
1ea6dd38 529 dev_dbg(dev, "Increasing fan%d "
08e7e278 530 "clock divider from %u to %u\n",
33725ad3 531 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 532 div_from_reg(data->fan_div[i] + 1));
533 data->fan_div[i]++;
1ea6dd38 534 w83627ehf_write_fan_div(data, i);
08e7e278
JD		 535 /* Preserve min limit if possible */
536 if (data->fan_min[i] >= 2
537 && data->fan_min[i] != 255)
1ea6dd38 538 w83627ehf_write_value(data,
08e7e278
JD		 539 W83627EHF_REG_FAN_MIN[i],
540 (data->fan_min[i] /= 2));
541 }
542 }
543
da2e0255
GR		 544 for (i = 0; i < data->pwm_num; i++) {
545 if (!(data->has_fan & (1 << i)))
546 continue;
547
77fa49d9 548 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
08c79950 549 if (i != 1) {
1ea6dd38 550 pwmcfg = w83627ehf_read_value(data,
08c79950 551 W83627EHF_REG_PWM_ENABLE[i]);
1ea6dd38 552 tolerance = w83627ehf_read_value(data,
08c79950
RM		 553 W83627EHF_REG_TOLERANCE[i]);
554 }
555 data->pwm_mode[i] =
556 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1)
557 ? 0 : 1;
558 data->pwm_enable[i] =
559 ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
560 & 3) + 1;
1ea6dd38 561 data->pwm[i] = w83627ehf_read_value(data,
08c79950 562 W83627EHF_REG_PWM[i]);
41e9a062
DB		 563 data->fan_start_output[i] = w83627ehf_read_value(data,
564 W83627EHF_REG_FAN_START_OUTPUT[i]);
565 data->fan_stop_output[i] = w83627ehf_read_value(data,
566 W83627EHF_REG_FAN_STOP_OUTPUT[i]);
1ea6dd38 567 data->fan_stop_time[i] = w83627ehf_read_value(data,
08c79950 568 W83627EHF_REG_FAN_STOP_TIME[i]);
da2e0255
GR		 569
570 if (data->REG_FAN_MAX_OUTPUT[i] != 0xff)
571 data->fan_max_output[i] =
572 w83627ehf_read_value(data,
573 data->REG_FAN_MAX_OUTPUT[i]);
574
575 if (data->REG_FAN_STEP_OUTPUT[i] != 0xff)
576 data->fan_step_output[i] =
577 w83627ehf_read_value(data,
578 data->REG_FAN_STEP_OUTPUT[i]);
579
08c79950 580 data->target_temp[i] =
1ea6dd38 581 w83627ehf_read_value(data,
08c79950
RM		 582 W83627EHF_REG_TARGET[i]) &
583 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
584 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0))
585 & 0x0f;
586 }
587
08e7e278 588 /* Measured temperatures and limits */
1ea6dd38 589 data->temp1 = w83627ehf_read_value(data,
08e7e278 590 W83627EHF_REG_TEMP1);
1ea6dd38 591 data->temp1_max = w83627ehf_read_value(data,
08e7e278 592 W83627EHF_REG_TEMP1_OVER);
1ea6dd38 593 data->temp1_max_hyst = w83627ehf_read_value(data,
08e7e278
JD		 594 W83627EHF_REG_TEMP1_HYST);
595 for (i = 0; i < 2; i++) {
1ea6dd38 596 data->temp[i] = w83627ehf_read_value(data,
08e7e278 597 W83627EHF_REG_TEMP[i]);
1ea6dd38 598 data->temp_max[i] = w83627ehf_read_value(data,
08e7e278 599 W83627EHF_REG_TEMP_OVER[i]);
1ea6dd38 600 data->temp_max_hyst[i] = w83627ehf_read_value(data,
08e7e278
JD		 601 W83627EHF_REG_TEMP_HYST[i]);
602 }
603
1ea6dd38 604 data->alarms = w83627ehf_read_value(data,
a4589dbb 605 W83627EHF_REG_ALARM1) |
1ea6dd38 606 (w83627ehf_read_value(data,
a4589dbb 607 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 608 (w83627ehf_read_value(data,
a4589dbb
JD		 609 W83627EHF_REG_ALARM3) << 16);
610
08e7e278
JD		 611 data->last_updated = jiffies;
612 data->valid = 1;
613 }
614
9a61bf63 615 mutex_unlock(&data->update_lock);
08e7e278
JD		 616 return data;
617}
618
619/*
620 * Sysfs callback functions
621 */
cf0676fe
RM		 622#define show_in_reg(reg) \
623static ssize_t \
624show_##reg(struct device *dev, struct device_attribute *attr, \
625 char *buf) \
626{ \
627 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
628 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
629 int nr = sensor_attr->index; \
630 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr)); \
631}
632show_in_reg(in)
633show_in_reg(in_min)
634show_in_reg(in_max)
635
636#define store_in_reg(REG, reg) \
637static ssize_t \
638store_in_##reg (struct device *dev, struct device_attribute *attr, \
639 const char *buf, size_t count) \
640{ \
1ea6dd38 641 struct w83627ehf_data *data = dev_get_drvdata(dev); \
cf0676fe
RM		 642 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
643 int nr = sensor_attr->index; \
644 u32 val = simple_strtoul(buf, NULL, 10); \
645 \
646 mutex_lock(&data->update_lock); \
647 data->in_##reg[nr] = in_to_reg(val, nr); \
1ea6dd38 648 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
cf0676fe
RM		 649 data->in_##reg[nr]); \
650 mutex_unlock(&data->update_lock); \
651 return count; \
652}
653
654store_in_reg(MIN, min)
655store_in_reg(MAX, max)
656
a4589dbb
JD		 657static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
658{
659 struct w83627ehf_data *data = w83627ehf_update_device(dev);
660 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
661 int nr = sensor_attr->index;
662 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
663}
664
cf0676fe
RM		 665static struct sensor_device_attribute sda_in_input[] = {
666 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
667 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
668 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
669 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
670 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
671 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
672 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
673 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
674 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
675 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
676};
677
a4589dbb
JD		 678static struct sensor_device_attribute sda_in_alarm[] = {
679 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
680 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
681 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
682 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
683 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
684 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
685 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
686 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
687 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
688 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
689};
690
cf0676fe
RM		 691static struct sensor_device_attribute sda_in_min[] = {
692 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
693 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
694 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
695 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
696 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
697 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
698 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
699 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
700 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
701 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
702};
703
704static struct sensor_device_attribute sda_in_max[] = {
705 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
706 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
707 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
708 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
709 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
710 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
711 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
712 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
713 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
714 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
715};
716
08e7e278
JD		 717#define show_fan_reg(reg) \
718static ssize_t \
412fec82
YM		 719show_##reg(struct device *dev, struct device_attribute *attr, \
720 char *buf) \
08e7e278
JD		 721{ \
722 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
412fec82
YM		 723 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
724 int nr = sensor_attr->index; \
08e7e278
JD		 725 return sprintf(buf, "%d\n", \
726 fan_from_reg(data->reg[nr], \
727 div_from_reg(data->fan_div[nr]))); \
728}
729show_fan_reg(fan);
730show_fan_reg(fan_min);
731
732static ssize_t
412fec82
YM		 733show_fan_div(struct device *dev, struct device_attribute *attr,
734 char *buf)
08e7e278
JD		 735{
736 struct w83627ehf_data *data = w83627ehf_update_device(dev);
412fec82
YM		 737 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
738 int nr = sensor_attr->index;
739 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
08e7e278
JD		 740}
741
742static ssize_t
412fec82
YM		 743store_fan_min(struct device *dev, struct device_attribute *attr,
744 const char *buf, size_t count)
08e7e278 745{
1ea6dd38 746 struct w83627ehf_data *data = dev_get_drvdata(dev);
412fec82
YM		 747 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
748 int nr = sensor_attr->index;
08e7e278
JD		 749 unsigned int val = simple_strtoul(buf, NULL, 10);
750 unsigned int reg;
751 u8 new_div;
752
9a61bf63 753 mutex_lock(&data->update_lock);
08e7e278
JD		 754 if (!val) {
755 /* No min limit, alarm disabled */
756 data->fan_min[nr] = 255;
757 new_div = data->fan_div[nr]; /* No change */
758 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
759 } else if ((reg = 1350000U / val) >= 128 * 255) {
760 /* Speed below this value cannot possibly be represented,
761 even with the highest divider (128) */
762 data->fan_min[nr] = 254;
763 new_div = 7; /* 128 == (1 << 7) */
764 dev_warn(dev, "fan%u low limit %u below minimum %u, set to "
765 "minimum\n", nr + 1, val, fan_from_reg(254, 128));
766 } else if (!reg) {
767 /* Speed above this value cannot possibly be represented,
768 even with the lowest divider (1) */
769 data->fan_min[nr] = 1;
770 new_div = 0; /* 1 == (1 << 0) */
771 dev_warn(dev, "fan%u low limit %u above maximum %u, set to "
b9110b1c 772 "maximum\n", nr + 1, val, fan_from_reg(1, 1));
08e7e278
JD		 773 } else {
774 /* Automatically pick the best divider, i.e. the one such
775 that the min limit will correspond to a register value
776 in the 96..192 range */
777 new_div = 0;
778 while (reg > 192 && new_div < 7) {
779 reg >>= 1;
780 new_div++;
781 }
782 data->fan_min[nr] = reg;
783 }
784
785 /* Write both the fan clock divider (if it changed) and the new
786 fan min (unconditionally) */
787 if (new_div != data->fan_div[nr]) {
158ce075
JD		 788 /* Preserve the fan speed reading */
789 if (data->fan[nr] != 0xff) {
790 if (new_div > data->fan_div[nr])
791 data->fan[nr] >>= new_div - data->fan_div[nr];
792 else if (data->fan[nr] & 0x80)
793 data->fan[nr] = 0xff;
794 else
795 data->fan[nr] <<= data->fan_div[nr] - new_div;
796 }
08e7e278
JD		 797
798 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
799 nr + 1, div_from_reg(data->fan_div[nr]),
800 div_from_reg(new_div));
801 data->fan_div[nr] = new_div;
1ea6dd38 802 w83627ehf_write_fan_div(data, nr);
6b3e4645
JD		 803 /* Give the chip time to sample a new speed value */
804 data->last_updated = jiffies;
08e7e278 805 }
1ea6dd38 806 w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[nr],
08e7e278 807 data->fan_min[nr]);
9a61bf63 808 mutex_unlock(&data->update_lock);
08e7e278
JD		 809
810 return count;
811}
812
412fec82
YM		 813static struct sensor_device_attribute sda_fan_input[] = {
814 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
815 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
816 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
817 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
818 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
819};
08e7e278 820
a4589dbb
JD		 821static struct sensor_device_attribute sda_fan_alarm[] = {
822 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
823 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
824 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
825 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
826 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
827};
828
412fec82
YM		 829static struct sensor_device_attribute sda_fan_min[] = {
830 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
831 store_fan_min, 0),
832 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
833 store_fan_min, 1),
834 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
835 store_fan_min, 2),
836 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
837 store_fan_min, 3),
838 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
839 store_fan_min, 4),
840};
08e7e278 841
412fec82
YM		 842static struct sensor_device_attribute sda_fan_div[] = {
843 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
844 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
845 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
846 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
847 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
848};
849
08e7e278
JD		 850#define show_temp1_reg(reg) \
851static ssize_t \
6f637a64
GKH		 852show_##reg(struct device *dev, struct device_attribute *attr, \
853 char *buf) \
08e7e278
JD		 854{ \
855 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
856 return sprintf(buf, "%d\n", temp1_from_reg(data->reg)); \
857}
858show_temp1_reg(temp1);
859show_temp1_reg(temp1_max);
860show_temp1_reg(temp1_max_hyst);
861
862#define store_temp1_reg(REG, reg) \
863static ssize_t \
6f637a64
GKH		 864store_temp1_##reg(struct device *dev, struct device_attribute *attr, \
865 const char *buf, size_t count) \
08e7e278 866{ \
1ea6dd38 867 struct w83627ehf_data *data = dev_get_drvdata(dev); \
5bfedac0 868 long val = simple_strtol(buf, NULL, 10); \
08e7e278 869 \
9a61bf63 870 mutex_lock(&data->update_lock); \
08c79950 871 data->temp1_##reg = temp1_to_reg(val, -128000, 127000); \
1ea6dd38 872 w83627ehf_write_value(data, W83627EHF_REG_TEMP1_##REG, \
08e7e278 873 data->temp1_##reg); \
9a61bf63 874 mutex_unlock(&data->update_lock); \
08e7e278
JD		 875 return count; \
876}
877store_temp1_reg(OVER, max);
878store_temp1_reg(HYST, max_hyst);
879
08e7e278
JD		 880#define show_temp_reg(reg) \
881static ssize_t \
412fec82
YM		 882show_##reg(struct device *dev, struct device_attribute *attr, \
883 char *buf) \
08e7e278
JD		 884{ \
885 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
412fec82
YM		 886 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
887 int nr = sensor_attr->index; \
08e7e278
JD		 888 return sprintf(buf, "%d\n", \
889 LM75_TEMP_FROM_REG(data->reg[nr])); \
890}
891show_temp_reg(temp);
892show_temp_reg(temp_max);
893show_temp_reg(temp_max_hyst);
894
895#define store_temp_reg(REG, reg) \
896static ssize_t \
412fec82
YM		 897store_##reg(struct device *dev, struct device_attribute *attr, \
898 const char *buf, size_t count) \
08e7e278 899{ \
1ea6dd38 900 struct w83627ehf_data *data = dev_get_drvdata(dev); \
412fec82
YM		 901 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
902 int nr = sensor_attr->index; \
5bfedac0 903 long val = simple_strtol(buf, NULL, 10); \
08e7e278 904 \
9a61bf63 905 mutex_lock(&data->update_lock); \
08e7e278 906 data->reg[nr] = LM75_TEMP_TO_REG(val); \
1ea6dd38 907 w83627ehf_write_value(data, W83627EHF_REG_TEMP_##REG[nr], \
08e7e278 908 data->reg[nr]); \
9a61bf63 909 mutex_unlock(&data->update_lock); \
08e7e278
JD		 910 return count; \
911}
912store_temp_reg(OVER, temp_max);
913store_temp_reg(HYST, temp_max_hyst);
914
da667365
JD		 915static ssize_t
916show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
917{
918 struct w83627ehf_data *data = w83627ehf_update_device(dev);
919 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
920 int nr = sensor_attr->index;
921 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
922}
923
a157d06d 924static struct sensor_device_attribute sda_temp_input[] = {
412fec82
YM		 925 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp1, NULL, 0),
926 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 0),
927 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 1),
a157d06d
GJ		 928};
929
930static struct sensor_device_attribute sda_temp_max[] = {
412fec82
YM		 931 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp1_max,
932 store_temp1_max, 0),
933 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
934 store_temp_max, 0),
935 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
936 store_temp_max, 1),
a157d06d
GJ		 937};
938
939static struct sensor_device_attribute sda_temp_max_hyst[] = {
412fec82
YM		 940 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp1_max_hyst,
941 store_temp1_max_hyst, 0),
942 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
943 store_temp_max_hyst, 0),
944 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
945 store_temp_max_hyst, 1),
a157d06d
GJ		 946};
947
948static struct sensor_device_attribute sda_temp_alarm[] = {
a4589dbb
JD		 949 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
950 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
951 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
a157d06d
GJ		 952};
953
954static struct sensor_device_attribute sda_temp_type[] = {
da667365
JD		 955 SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
956 SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
957 SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
412fec82 958};
08e7e278 959
08c79950
RM		 960#define show_pwm_reg(reg) \
961static ssize_t show_##reg (struct device *dev, struct device_attribute *attr, \
962 char *buf) \
963{ \
964 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
965 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
966 int nr = sensor_attr->index; \
967 return sprintf(buf, "%d\n", data->reg[nr]); \
968}
969
970show_pwm_reg(pwm_mode)
971show_pwm_reg(pwm_enable)
972show_pwm_reg(pwm)
973
974static ssize_t
975store_pwm_mode(struct device *dev, struct device_attribute *attr,
976 const char *buf, size_t count)
977{
1ea6dd38 978 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 979 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
980 int nr = sensor_attr->index;
981 u32 val = simple_strtoul(buf, NULL, 10);
982 u16 reg;
983
984 if (val > 1)
985 return -EINVAL;
986 mutex_lock(&data->update_lock);
1ea6dd38 987 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 988 data->pwm_mode[nr] = val;
989 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
990 if (!val)
991 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1ea6dd38 992 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 993 mutex_unlock(&data->update_lock);
994 return count;
995}
996
997static ssize_t
998store_pwm(struct device *dev, struct device_attribute *attr,
999 const char *buf, size_t count)
1000{
1ea6dd38 1001 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1002 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1003 int nr = sensor_attr->index;
1004 u32 val = SENSORS_LIMIT(simple_strtoul(buf, NULL, 10), 0, 255);
1005
1006 mutex_lock(&data->update_lock);
1007 data->pwm[nr] = val;
1ea6dd38 1008 w83627ehf_write_value(data, W83627EHF_REG_PWM[nr], val);
08c79950
RM		 1009 mutex_unlock(&data->update_lock);
1010 return count;
1011}
1012
1013static ssize_t
1014store_pwm_enable(struct device *dev, struct device_attribute *attr,
1015 const char *buf, size_t count)
1016{
1ea6dd38 1017 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1018 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1019 int nr = sensor_attr->index;
1020 u32 val = simple_strtoul(buf, NULL, 10);
1021 u16 reg;
1022
41e9a062 1023 if (!val || (val > 4))
08c79950
RM		 1024 return -EINVAL;
1025 mutex_lock(&data->update_lock);
1ea6dd38 1026 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 1027 data->pwm_enable[nr] = val;
1028 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
1029 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1ea6dd38 1030 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 1031 mutex_unlock(&data->update_lock);
1032 return count;
1033}
1034
1035
1036#define show_tol_temp(reg) \
1037static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1038 char *buf) \
1039{ \
1040 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1041 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1042 int nr = sensor_attr->index; \
1043 return sprintf(buf, "%d\n", temp1_from_reg(data->reg[nr])); \
1044}
1045
1046show_tol_temp(tolerance)
1047show_tol_temp(target_temp)
1048
1049static ssize_t
1050store_target_temp(struct device *dev, struct device_attribute *attr,
1051 const char *buf, size_t count)
1052{
1ea6dd38 1053 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1054 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1055 int nr = sensor_attr->index;
1056 u8 val = temp1_to_reg(simple_strtoul(buf, NULL, 10), 0, 127000);
1057
1058 mutex_lock(&data->update_lock);
1059 data->target_temp[nr] = val;
1ea6dd38 1060 w83627ehf_write_value(data, W83627EHF_REG_TARGET[nr], val);
08c79950
RM		 1061 mutex_unlock(&data->update_lock);
1062 return count;
1063}
1064
1065static ssize_t
1066store_tolerance(struct device *dev, struct device_attribute *attr,
1067 const char *buf, size_t count)
1068{
1ea6dd38 1069 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1070 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1071 int nr = sensor_attr->index;
1072 u16 reg;
1073 /* Limit the temp to 0C - 15C */
1074 u8 val = temp1_to_reg(simple_strtoul(buf, NULL, 10), 0, 15000);
1075
1076 mutex_lock(&data->update_lock);
1ea6dd38 1077 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
08c79950
RM		 1078 data->tolerance[nr] = val;
1079 if (nr == 1)
1080 reg = (reg & 0x0f) | (val << 4);
1081 else
1082 reg = (reg & 0xf0) | val;
1ea6dd38 1083 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
08c79950
RM		 1084 mutex_unlock(&data->update_lock);
1085 return count;
1086}
1087
1088static struct sensor_device_attribute sda_pwm[] = {
1089 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1090 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1091 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1092 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1093};
1094
1095static struct sensor_device_attribute sda_pwm_mode[] = {
1096 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1097 store_pwm_mode, 0),
1098 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1099 store_pwm_mode, 1),
1100 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1101 store_pwm_mode, 2),
1102 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1103 store_pwm_mode, 3),
1104};
1105
1106static struct sensor_device_attribute sda_pwm_enable[] = {
1107 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1108 store_pwm_enable, 0),
1109 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1110 store_pwm_enable, 1),
1111 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1112 store_pwm_enable, 2),
1113 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1114 store_pwm_enable, 3),
1115};
1116
1117static struct sensor_device_attribute sda_target_temp[] = {
1118 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1119 store_target_temp, 0),
1120 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1121 store_target_temp, 1),
1122 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1123 store_target_temp, 2),
1124 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1125 store_target_temp, 3),
1126};
1127
1128static struct sensor_device_attribute sda_tolerance[] = {
1129 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1130 store_tolerance, 0),
1131 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1132 store_tolerance, 1),
1133 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1134 store_tolerance, 2),
1135 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1136 store_tolerance, 3),
1137};
1138
08c79950
RM		 1139/* Smart Fan registers */
1140
1141#define fan_functions(reg, REG) \
1142static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1143 char *buf) \
1144{ \
1145 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1146 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1147 int nr = sensor_attr->index; \
1148 return sprintf(buf, "%d\n", data->reg[nr]); \
1149}\
1150static ssize_t \
1151store_##reg(struct device *dev, struct device_attribute *attr, \
1152 const char *buf, size_t count) \
1153{\
1ea6dd38 1154 struct w83627ehf_data *data = dev_get_drvdata(dev); \
08c79950
RM		 1155 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1156 int nr = sensor_attr->index; \
1157 u32 val = SENSORS_LIMIT(simple_strtoul(buf, NULL, 10), 1, 255); \
1158 mutex_lock(&data->update_lock); \
1159 data->reg[nr] = val; \
da2e0255 1160 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
08c79950
RM		 1161 mutex_unlock(&data->update_lock); \
1162 return count; \
1163}
1164
41e9a062
DB		 1165fan_functions(fan_start_output, FAN_START_OUTPUT)
1166fan_functions(fan_stop_output, FAN_STOP_OUTPUT)
1167fan_functions(fan_max_output, FAN_MAX_OUTPUT)
1168fan_functions(fan_step_output, FAN_STEP_OUTPUT)
08c79950
RM		 1169
1170#define fan_time_functions(reg, REG) \
1171static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1172 char *buf) \
1173{ \
1174 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1175 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1176 int nr = sensor_attr->index; \
1177 return sprintf(buf, "%d\n", \
1178 step_time_from_reg(data->reg[nr], data->pwm_mode[nr])); \
1179} \
1180\
1181static ssize_t \
1182store_##reg(struct device *dev, struct device_attribute *attr, \
1183 const char *buf, size_t count) \
1184{ \
1ea6dd38 1185 struct w83627ehf_data *data = dev_get_drvdata(dev); \
08c79950
RM		 1186 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1187 int nr = sensor_attr->index; \
1188 u8 val = step_time_to_reg(simple_strtoul(buf, NULL, 10), \
1189 data->pwm_mode[nr]); \
1190 mutex_lock(&data->update_lock); \
1191 data->reg[nr] = val; \
1ea6dd38 1192 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
08c79950
RM		 1193 mutex_unlock(&data->update_lock); \
1194 return count; \
1195} \
1196
1197fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1198
1ea6dd38
DH		 1199static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1200 char *buf)
1201{
1202 struct w83627ehf_data *data = dev_get_drvdata(dev);
1203
1204 return sprintf(buf, "%s\n", data->name);
1205}
1206static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
08c79950
RM		 1207
1208static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1209 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1210 store_fan_stop_time, 3),
41e9a062
DB		 1211 SENSOR_ATTR(pwm4_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1212 store_fan_start_output, 3),
1213 SENSOR_ATTR(pwm4_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1214 store_fan_stop_output, 3),
1215 SENSOR_ATTR(pwm4_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1216 store_fan_max_output, 3),
1217 SENSOR_ATTR(pwm4_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1218 store_fan_step_output, 3),
08c79950
RM		 1219};
1220
1221static struct sensor_device_attribute sda_sf3_arrays[] = {
1222 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1223 store_fan_stop_time, 0),
1224 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1225 store_fan_stop_time, 1),
1226 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1227 store_fan_stop_time, 2),
41e9a062
DB		 1228 SENSOR_ATTR(pwm1_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1229 store_fan_start_output, 0),
1230 SENSOR_ATTR(pwm2_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1231 store_fan_start_output, 1),
1232 SENSOR_ATTR(pwm3_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1233 store_fan_start_output, 2),
1234 SENSOR_ATTR(pwm1_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1235 store_fan_stop_output, 0),
1236 SENSOR_ATTR(pwm2_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1237 store_fan_stop_output, 1),
1238 SENSOR_ATTR(pwm3_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1239 store_fan_stop_output, 2),
da2e0255 1240};
41e9a062 1241
da2e0255
GR		 1242
1243/*
1244 * pwm1 and pwm3 don't support max and step settings on all chips.
1245 * Need to check support while generating/removing attribute files.
1246 */
1247static struct sensor_device_attribute sda_sf3_max_step_arrays[] = {
1248 SENSOR_ATTR(pwm1_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1249 store_fan_max_output, 0),
1250 SENSOR_ATTR(pwm1_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1251 store_fan_step_output, 0),
41e9a062
DB		 1252 SENSOR_ATTR(pwm2_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1253 store_fan_max_output, 1),
1254 SENSOR_ATTR(pwm2_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1255 store_fan_step_output, 1),
da2e0255
GR		 1256 SENSOR_ATTR(pwm3_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1257 store_fan_max_output, 2),
1258 SENSOR_ATTR(pwm3_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1259 store_fan_step_output, 2),
08c79950
RM		 1260};
1261
fc18d6c0
JD		 1262static ssize_t
1263show_vid(struct device *dev, struct device_attribute *attr, char *buf)
1264{
1265 struct w83627ehf_data *data = dev_get_drvdata(dev);
1266 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1267}
1268static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1269
08e7e278 1270/*
1ea6dd38 1271 * Driver and device management
08e7e278
JD		 1272 */
1273
c18beb5b
DH		 1274static void w83627ehf_device_remove_files(struct device *dev)
1275{
1276 /* some entries in the following arrays may not have been used in
1277 * device_create_file(), but device_remove_file() will ignore them */
1278 int i;
1ea6dd38 1279 struct w83627ehf_data *data = dev_get_drvdata(dev);
c18beb5b
DH		 1280
1281 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1282 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
da2e0255
GR		 1283 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
1284 struct sensor_device_attribute *attr =
1285 &sda_sf3_max_step_arrays[i];
1286 if (data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff)
1287 device_remove_file(dev, &attr->dev_attr);
1288 }
c18beb5b
DH		 1289 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1290 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1ea6dd38 1291 for (i = 0; i < data->in_num; i++) {
a157d06d
GJ		 1292 if ((i == 6) && data->in6_skip)
1293 continue;
c18beb5b
DH		 1294 device_remove_file(dev, &sda_in_input[i].dev_attr);
1295 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1296 device_remove_file(dev, &sda_in_min[i].dev_attr);
1297 device_remove_file(dev, &sda_in_max[i].dev_attr);
1298 }
1299 for (i = 0; i < 5; i++) {
1300 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1301 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1302 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1303 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1304 }
237c8d2f 1305 for (i = 0; i < data->pwm_num; i++) {
c18beb5b
DH		 1306 device_remove_file(dev, &sda_pwm[i].dev_attr);
1307 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1308 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1309 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1310 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1311 }
a157d06d
GJ		 1312 for (i = 0; i < 3; i++) {
1313 if ((i == 2) && data->temp3_disable)
1314 continue;
1315 device_remove_file(dev, &sda_temp_input[i].dev_attr);
1316 device_remove_file(dev, &sda_temp_max[i].dev_attr);
1317 device_remove_file(dev, &sda_temp_max_hyst[i].dev_attr);
1318 device_remove_file(dev, &sda_temp_alarm[i].dev_attr);
1319 device_remove_file(dev, &sda_temp_type[i].dev_attr);
1320 }
c18beb5b 1321
1ea6dd38 1322 device_remove_file(dev, &dev_attr_name);
cbe311f2 1323 device_remove_file(dev, &dev_attr_cpu0_vid);
1ea6dd38 1324}
08e7e278 1325
1ea6dd38
DH		 1326/* Get the monitoring functions started */
1327static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data)
08e7e278
JD		 1328{
1329 int i;
da667365 1330 u8 tmp, diode;
08e7e278
JD		 1331
1332 /* Start monitoring is needed */
1ea6dd38 1333 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1334 if (!(tmp & 0x01))
1ea6dd38 1335 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1336 tmp | 0x01);
1337
1338 /* Enable temp2 and temp3 if needed */
1339 for (i = 0; i < 2; i++) {
1ea6dd38 1340 tmp = w83627ehf_read_value(data,
08e7e278 1341 W83627EHF_REG_TEMP_CONFIG[i]);
a157d06d
GJ		 1342 if ((i == 1) && data->temp3_disable)
1343 continue;
08e7e278 1344 if (tmp & 0x01)
1ea6dd38 1345 w83627ehf_write_value(data,
08e7e278
JD		 1346 W83627EHF_REG_TEMP_CONFIG[i],
1347 tmp & 0xfe);
1348 }
d3130f0e
JD		 1349
1350 /* Enable VBAT monitoring if needed */
1351 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1352 if (!(tmp & 0x01))
1353 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
da667365
JD		 1354
1355 /* Get thermal sensor types */
1356 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1357 for (i = 0; i < 3; i++) {
1358 if ((tmp & (0x02 << i)))
1359 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 2;
1360 else
1361 data->temp_type[i] = 4; /* thermistor */
1362 }
08e7e278
JD		 1363}
1364
1ea6dd38 1365static int __devinit w83627ehf_probe(struct platform_device *pdev)
08e7e278 1366{
1ea6dd38
DH		 1367 struct device *dev = &pdev->dev;
1368 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08e7e278 1369 struct w83627ehf_data *data;
1ea6dd38 1370 struct resource *res;
fc18d6c0 1371 u8 fan4pin, fan5pin, en_vrm10;
08e7e278
JD		 1372 int i, err = 0;
1373
1ea6dd38
DH		 1374 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1375 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 1376 err = -EBUSY;
1ea6dd38
DH		 1377 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1378 (unsigned long)res->start,
1379 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 1380 goto exit;
1381 }
1382
ba9c2e8d 1383 if (!(data = kzalloc(sizeof(struct w83627ehf_data), GFP_KERNEL))) {
08e7e278
JD		 1384 err = -ENOMEM;
1385 goto exit_release;
1386 }
08e7e278 1387
1ea6dd38 1388 data->addr = res->start;
9a61bf63 1389 mutex_init(&data->lock);
9a61bf63 1390 mutex_init(&data->update_lock);
1ea6dd38
DH		 1391 data->name = w83627ehf_device_names[sio_data->kind];
1392 platform_set_drvdata(pdev, data);
08e7e278 1393
237c8d2f
GJ		 1394 /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
1395 data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
1396 /* 667HG has 3 pwms */
c39aedaf
GR		 1397 data->pwm_num = (sio_data->kind == w83667hg
1398 || sio_data->kind == w83667hg_b) ? 3 : 4;
08e7e278 1399
a157d06d 1400 /* Check temp3 configuration bit for 667HG */
c39aedaf 1401 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
a157d06d
GJ		 1402 data->temp3_disable = w83627ehf_read_value(data,
1403 W83627EHF_REG_TEMP_CONFIG[1]) & 0x01;
1404 data->in6_skip = !data->temp3_disable;
1405 }
1406
da2e0255
GR		 1407 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
1408 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
c39aedaf
GR		 1409 if (sio_data->kind == w83667hg_b) {
1410 data->REG_FAN_MAX_OUTPUT =
1411 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
1412 data->REG_FAN_STEP_OUTPUT =
1413 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
1414 } else {
1415 data->REG_FAN_MAX_OUTPUT =
1416 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
1417 data->REG_FAN_STEP_OUTPUT =
1418 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
1419 }
da2e0255 1420
08e7e278 1421 /* Initialize the chip */
1ea6dd38 1422 w83627ehf_init_device(data);
08e7e278 1423
fc18d6c0
JD		 1424 data->vrm = vid_which_vrm();
1425 superio_enter(sio_data->sioreg);
fc18d6c0 1426 /* Read VID value */
c39aedaf 1427 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
237c8d2f
GJ		 1428 /* W83667HG has different pins for VID input and output, so
1429 we can get the VID input values directly at logical device D
1430 0xe3. */
1431 superio_select(sio_data->sioreg, W83667HG_LD_VID);
1432 data->vid = superio_inb(sio_data->sioreg, 0xe3);
cbe311f2
JD		 1433 err = device_create_file(dev, &dev_attr_cpu0_vid);
1434 if (err)
1435 goto exit_release;
58e6e781 1436 } else {
237c8d2f
GJ		 1437 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
1438 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
1439 /* Set VID input sensibility if needed. In theory the
1440 BIOS should have set it, but in practice it's not
1441 always the case. We only do it for the W83627EHF/EHG
1442 because the W83627DHG is more complex in this
1443 respect. */
1444 if (sio_data->kind == w83627ehf) {
1445 en_vrm10 = superio_inb(sio_data->sioreg,
1446 SIO_REG_EN_VRM10);
1447 if ((en_vrm10 & 0x08) && data->vrm == 90) {
1448 dev_warn(dev, "Setting VID input "
1449 "voltage to TTL\n");
1450 superio_outb(sio_data->sioreg,
1451 SIO_REG_EN_VRM10,
1452 en_vrm10 & ~0x08);
1453 } else if (!(en_vrm10 & 0x08)
1454 && data->vrm == 100) {
1455 dev_warn(dev, "Setting VID input "
1456 "voltage to VRM10\n");
1457 superio_outb(sio_data->sioreg,
1458 SIO_REG_EN_VRM10,
1459 en_vrm10 | 0x08);
1460 }
1461 }
1462
1463 data->vid = superio_inb(sio_data->sioreg,
1464 SIO_REG_VID_DATA);
1465 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
1466 data->vid &= 0x3f;
1467
1468 err = device_create_file(dev, &dev_attr_cpu0_vid);
1469 if (err)
1470 goto exit_release;
1471 } else {
1472 dev_info(dev, "VID pins in output mode, CPU VID not "
1473 "available\n");
1474 }
fc18d6c0
JD		 1475 }
1476
08c79950 1477 /* fan4 and fan5 share some pins with the GPIO and serial flash */
c39aedaf 1478 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
237c8d2f
GJ		 1479 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
1480 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
1481 } else {
1482 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
1483 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
1484 }
1ea6dd38 1485 superio_exit(sio_data->sioreg);
08c79950 1486
08e7e278 1487 /* It looks like fan4 and fan5 pins can be alternatively used
14992c7e
RM		 1488 as fan on/off switches, but fan5 control is write only :/
1489 We assume that if the serial interface is disabled, designers
1490 connected fan5 as input unless they are emitting log 1, which
1491 is not the default. */
08c79950 1492
08e7e278 1493 data->has_fan = 0x07; /* fan1, fan2 and fan3 */
1ea6dd38 1494 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
1704b26e 1495 if ((i & (1 << 2)) && fan4pin)
08e7e278 1496 data->has_fan |= (1 << 3);
1704b26e 1497 if (!(i & (1 << 1)) && fan5pin)
08e7e278
JD		 1498 data->has_fan |= (1 << 4);
1499
ea7be66c
MH		 1500 /* Read fan clock dividers immediately */
1501 w83627ehf_update_fan_div(data);
1502
08e7e278 1503 /* Register sysfs hooks */
08c79950 1504 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
c18beb5b
DH		 1505 if ((err = device_create_file(dev,
1506 &sda_sf3_arrays[i].dev_attr)))
1507 goto exit_remove;
08c79950 1508
da2e0255
GR		 1509 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
1510 struct sensor_device_attribute *attr =
1511 &sda_sf3_max_step_arrays[i];
1512 if (data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) {
1513 err = device_create_file(dev, &attr->dev_attr);
1514 if (err)
1515 goto exit_remove;
1516 }
1517 }
08c79950 1518 /* if fan4 is enabled create the sf3 files for it */
237c8d2f 1519 if ((data->has_fan & (1 << 3)) && data->pwm_num >= 4)
c18beb5b
DH		 1520 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
1521 if ((err = device_create_file(dev,
1522 &sda_sf3_arrays_fan4[i].dev_attr)))
1523 goto exit_remove;
1524 }
08c79950 1525
a157d06d
GJ		 1526 for (i = 0; i < data->in_num; i++) {
1527 if ((i == 6) && data->in6_skip)
1528 continue;
c18beb5b
DH		 1529 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
1530 || (err = device_create_file(dev,
1531 &sda_in_alarm[i].dev_attr))
1532 || (err = device_create_file(dev,
1533 &sda_in_min[i].dev_attr))
1534 || (err = device_create_file(dev,
1535 &sda_in_max[i].dev_attr)))
1536 goto exit_remove;
a157d06d 1537 }
cf0676fe 1538
412fec82 1539 for (i = 0; i < 5; i++) {
08c79950 1540 if (data->has_fan & (1 << i)) {
c18beb5b
DH		 1541 if ((err = device_create_file(dev,
1542 &sda_fan_input[i].dev_attr))
1543 || (err = device_create_file(dev,
1544 &sda_fan_alarm[i].dev_attr))
1545 || (err = device_create_file(dev,
1546 &sda_fan_div[i].dev_attr))
1547 || (err = device_create_file(dev,
1548 &sda_fan_min[i].dev_attr)))
1549 goto exit_remove;
237c8d2f 1550 if (i < data->pwm_num &&
c18beb5b
DH		 1551 ((err = device_create_file(dev,
1552 &sda_pwm[i].dev_attr))
1553 || (err = device_create_file(dev,
1554 &sda_pwm_mode[i].dev_attr))
1555 || (err = device_create_file(dev,
1556 &sda_pwm_enable[i].dev_attr))
1557 || (err = device_create_file(dev,
1558 &sda_target_temp[i].dev_attr))
1559 || (err = device_create_file(dev,
1560 &sda_tolerance[i].dev_attr))))
1561 goto exit_remove;
08c79950 1562 }
08e7e278 1563 }
08c79950 1564
a157d06d
GJ		 1565 for (i = 0; i < 3; i++) {
1566 if ((i == 2) && data->temp3_disable)
1567 continue;
1568 if ((err = device_create_file(dev,
1569 &sda_temp_input[i].dev_attr))
1570 || (err = device_create_file(dev,
1571 &sda_temp_max[i].dev_attr))
1572 || (err = device_create_file(dev,
1573 &sda_temp_max_hyst[i].dev_attr))
1574 || (err = device_create_file(dev,
1575 &sda_temp_alarm[i].dev_attr))
1576 || (err = device_create_file(dev,
1577 &sda_temp_type[i].dev_attr)))
c18beb5b 1578 goto exit_remove;
a157d06d 1579 }
c18beb5b 1580
1ea6dd38
DH		 1581 err = device_create_file(dev, &dev_attr_name);
1582 if (err)
1583 goto exit_remove;
1584
1beeffe4
TJ		 1585 data->hwmon_dev = hwmon_device_register(dev);
1586 if (IS_ERR(data->hwmon_dev)) {
1587 err = PTR_ERR(data->hwmon_dev);
c18beb5b
DH		 1588 goto exit_remove;
1589 }
08e7e278
JD		 1590
1591 return 0;
1592
c18beb5b
DH		 1593exit_remove:
1594 w83627ehf_device_remove_files(dev);
08e7e278 1595 kfree(data);
1ea6dd38 1596 platform_set_drvdata(pdev, NULL);
08e7e278 1597exit_release:
1ea6dd38 1598 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 1599exit:
1600 return err;
1601}
1602
1ea6dd38 1603static int __devexit w83627ehf_remove(struct platform_device *pdev)
08e7e278 1604{
1ea6dd38 1605 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 1606
1beeffe4 1607 hwmon_device_unregister(data->hwmon_dev);
1ea6dd38
DH		 1608 w83627ehf_device_remove_files(&pdev->dev);
1609 release_region(data->addr, IOREGION_LENGTH);
1610 platform_set_drvdata(pdev, NULL);
943b0830 1611 kfree(data);
08e7e278
JD		 1612
1613 return 0;
1614}
1615
1ea6dd38 1616static struct platform_driver w83627ehf_driver = {
cdaf7934 1617 .driver = {
87218842 1618 .owner = THIS_MODULE,
1ea6dd38 1619 .name = DRVNAME,
cdaf7934 1620 },
1ea6dd38
DH		 1621 .probe = w83627ehf_probe,
1622 .remove = __devexit_p(w83627ehf_remove),
08e7e278
JD		 1623};
1624
1ea6dd38
DH		 1625/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
1626static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
1627 struct w83627ehf_sio_data *sio_data)
08e7e278 1628{
1ea6dd38
DH		 1629 static const char __initdata sio_name_W83627EHF[] = "W83627EHF";
1630 static const char __initdata sio_name_W83627EHG[] = "W83627EHG";
1631 static const char __initdata sio_name_W83627DHG[] = "W83627DHG";
c1e48dce 1632 static const char __initdata sio_name_W83627DHG_P[] = "W83627DHG-P";
237c8d2f 1633 static const char __initdata sio_name_W83667HG[] = "W83667HG";
c39aedaf 1634 static const char __initdata sio_name_W83667HG_B[] = "W83667HG-B";
1ea6dd38 1635
08e7e278 1636 u16 val;
1ea6dd38 1637 const char *sio_name;
08e7e278 1638
1ea6dd38 1639 superio_enter(sioaddr);
08e7e278 1640
67b671bc
JD		 1641 if (force_id)
1642 val = force_id;
1643 else
1644 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
1645 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 1646 switch (val & SIO_ID_MASK) {
657c93b1 1647 case SIO_W83627EHF_ID:
1ea6dd38
DH		 1648 sio_data->kind = w83627ehf;
1649 sio_name = sio_name_W83627EHF;
1650 break;
657c93b1 1651 case SIO_W83627EHG_ID:
1ea6dd38
DH		 1652 sio_data->kind = w83627ehf;
1653 sio_name = sio_name_W83627EHG;
1654 break;
1655 case SIO_W83627DHG_ID:
1656 sio_data->kind = w83627dhg;
1657 sio_name = sio_name_W83627DHG;
657c93b1 1658 break;
c1e48dce
JD		 1659 case SIO_W83627DHG_P_ID:
1660 sio_data->kind = w83627dhg_p;
1661 sio_name = sio_name_W83627DHG_P;
1662 break;
237c8d2f
GJ		 1663 case SIO_W83667HG_ID:
1664 sio_data->kind = w83667hg;
1665 sio_name = sio_name_W83667HG;
1666 break;
c39aedaf
GR		 1667 case SIO_W83667HG_B_ID:
1668 sio_data->kind = w83667hg_b;
1669 sio_name = sio_name_W83667HG_B;
1670 break;
657c93b1 1671 default:
9f66036b 1672 if (val != 0xffff)
abdc6fd1 1673 pr_debug("unsupported chip ID: 0x%04x\n", val);
1ea6dd38 1674 superio_exit(sioaddr);
08e7e278
JD		 1675 return -ENODEV;
1676 }
1677
1ea6dd38
DH		 1678 /* We have a known chip, find the HWM I/O address */
1679 superio_select(sioaddr, W83627EHF_LD_HWM);
1680 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
1681 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 1682 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 1683 if (*addr == 0) {
abdc6fd1 1684 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
1ea6dd38 1685 superio_exit(sioaddr);
08e7e278
JD		 1686 return -ENODEV;
1687 }
1688
1689 /* Activate logical device if needed */
1ea6dd38 1690 val = superio_inb(sioaddr, SIO_REG_ENABLE);
475ef855 1691 if (!(val & 0x01)) {
abdc6fd1 1692 pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
1ea6dd38 1693 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
475ef855 1694 }
1ea6dd38
DH		 1695
1696 superio_exit(sioaddr);
abdc6fd1 1697 pr_info("Found %s chip at %#x\n", sio_name, *addr);
1ea6dd38 1698 sio_data->sioreg = sioaddr;
08e7e278 1699
08e7e278
JD		 1700 return 0;
1701}
1702
1ea6dd38
DH		 1703/* when Super-I/O functions move to a separate file, the Super-I/O
1704 * bus will manage the lifetime of the device and this module will only keep
1705 * track of the w83627ehf driver. But since we platform_device_alloc(), we
1706 * must keep track of the device */
1707static struct platform_device *pdev;
1708
08e7e278
JD		 1709static int __init sensors_w83627ehf_init(void)
1710{
1ea6dd38
DH		 1711 int err;
1712 unsigned short address;
1713 struct resource res;
1714 struct w83627ehf_sio_data sio_data;
1715
1716 /* initialize sio_data->kind and sio_data->sioreg.
1717 *
1718 * when Super-I/O functions move to a separate file, the Super-I/O
1719 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
1720 * w83627ehf hardware monitor, and call probe() */
1721 if (w83627ehf_find(0x2e, &address, &sio_data) &&
1722 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 1723 return -ENODEV;
1724
1ea6dd38
DH		 1725 err = platform_driver_register(&w83627ehf_driver);
1726 if (err)
1727 goto exit;
1728
1729 if (!(pdev = platform_device_alloc(DRVNAME, address))) {
1730 err = -ENOMEM;
abdc6fd1 1731 pr_err("Device allocation failed\n");
1ea6dd38
DH		 1732 goto exit_unregister;
1733 }
1734
1735 err = platform_device_add_data(pdev, &sio_data,
1736 sizeof(struct w83627ehf_sio_data));
1737 if (err) {
abdc6fd1 1738 pr_err("Platform data allocation failed\n");
1ea6dd38
DH		 1739 goto exit_device_put;
1740 }
1741
1742 memset(&res, 0, sizeof(res));
1743 res.name = DRVNAME;
1744 res.start = address + IOREGION_OFFSET;
1745 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
1746 res.flags = IORESOURCE_IO;
b9acb64a
JD		 1747
1748 err = acpi_check_resource_conflict(&res);
1749 if (err)
18632f84 1750 goto exit_device_put;
b9acb64a 1751
1ea6dd38
DH		 1752 err = platform_device_add_resources(pdev, &res, 1);
1753 if (err) {
abdc6fd1 1754 pr_err("Device resource addition failed (%d)\n", err);
1ea6dd38
DH		 1755 goto exit_device_put;
1756 }
1757
1758 /* platform_device_add calls probe() */
1759 err = platform_device_add(pdev);
1760 if (err) {
abdc6fd1 1761 pr_err("Device addition failed (%d)\n", err);
1ea6dd38
DH		 1762 goto exit_device_put;
1763 }
1764
1765 return 0;
1766
1767exit_device_put:
1768 platform_device_put(pdev);
1769exit_unregister:
1770 platform_driver_unregister(&w83627ehf_driver);
1771exit:
1772 return err;
08e7e278
JD		 1773}
1774
1775static void __exit sensors_w83627ehf_exit(void)
1776{
1ea6dd38
DH		 1777 platform_device_unregister(pdev);
1778 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 1779}
1780
1781MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
1782MODULE_DESCRIPTION("W83627EHF driver");
1783MODULE_LICENSE("GPL");
1784
1785module_init(sensors_w83627ehf_init);
1786module_exit(sensors_w83627ehf_exit);
Linux kernel - Deliverables
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