Merge remote-tracking branch 'char-misc/char-misc-next'
[deliverable/linux.git] / drivers / hwtracing / coresight / coresight-tmc.h
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1/*
2 * Copyright(C) 2015 Linaro Limited. All rights reserved.
3 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef _CORESIGHT_TMC_H
19#define _CORESIGHT_TMC_H
20
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21#include <linux/miscdevice.h>
22
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23#define TMC_RSZ 0x004
24#define TMC_STS 0x00c
25#define TMC_RRD 0x010
26#define TMC_RRP 0x014
27#define TMC_RWP 0x018
28#define TMC_TRG 0x01c
29#define TMC_CTL 0x020
30#define TMC_RWD 0x024
31#define TMC_MODE 0x028
32#define TMC_LBUFLEVEL 0x02c
33#define TMC_CBUFLEVEL 0x030
34#define TMC_BUFWM 0x034
35#define TMC_RRPHI 0x038
36#define TMC_RWPHI 0x03c
37#define TMC_AXICTL 0x110
38#define TMC_DBALO 0x118
39#define TMC_DBAHI 0x11c
40#define TMC_FFSR 0x300
41#define TMC_FFCR 0x304
42#define TMC_PSCR 0x308
43#define TMC_ITMISCOP0 0xee0
44#define TMC_ITTRFLIN 0xee8
45#define TMC_ITATBDATA0 0xeec
46#define TMC_ITATBCTR2 0xef0
47#define TMC_ITATBCTR1 0xef4
48#define TMC_ITATBCTR0 0xef8
49
50/* register description */
51/* TMC_CTL - 0x020 */
52#define TMC_CTL_CAPT_EN BIT(0)
53/* TMC_STS - 0x00C */
a8ab4268 54#define TMC_STS_TMCREADY_BIT 2
2e499bbc 55#define TMC_STS_FULL BIT(0)
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56#define TMC_STS_TRIGGERED BIT(1)
57/* TMC_AXICTL - 0x110 */
58#define TMC_AXICTL_PROT_CTL_B0 BIT(0)
59#define TMC_AXICTL_PROT_CTL_B1 BIT(1)
60#define TMC_AXICTL_SCT_GAT_MODE BIT(7)
61#define TMC_AXICTL_WR_BURST_16 0xF00
62/* TMC_FFCR - 0x304 */
a8ab4268 63#define TMC_FFCR_FLUSHMAN_BIT 6
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64#define TMC_FFCR_EN_FMT BIT(0)
65#define TMC_FFCR_EN_TI BIT(1)
66#define TMC_FFCR_FON_FLIN BIT(4)
67#define TMC_FFCR_FON_TRIG_EVT BIT(5)
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68#define TMC_FFCR_TRIGON_TRIGIN BIT(8)
69#define TMC_FFCR_STOP_ON_FLUSH BIT(12)
70
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71
72enum tmc_config_type {
73 TMC_CONFIG_TYPE_ETB,
74 TMC_CONFIG_TYPE_ETR,
75 TMC_CONFIG_TYPE_ETF,
76};
77
78enum tmc_mode {
79 TMC_MODE_CIRCULAR_BUFFER,
80 TMC_MODE_SOFTWARE_FIFO,
81 TMC_MODE_HARDWARE_FIFO,
82};
83
84enum tmc_mem_intf_width {
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85 TMC_MEM_INTF_WIDTH_32BITS = 1,
86 TMC_MEM_INTF_WIDTH_64BITS = 2,
87 TMC_MEM_INTF_WIDTH_128BITS = 4,
88 TMC_MEM_INTF_WIDTH_256BITS = 8,
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89};
90
91/**
92 * struct tmc_drvdata - specifics associated to an TMC component
93 * @base: memory mapped base address for this component.
94 * @dev: the device entity associated to this component.
95 * @csdev: component vitals needed by the framework.
96 * @miscdev: specifics to handle "/dev/xyz.tmc" entry.
97 * @spinlock: only one at a time pls.
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98 * @buf: area of memory where trace data get sent.
99 * @paddr: DMA start location in RAM.
100 * @vaddr: virtual representation of @paddr.
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101 * @size: trace buffer size.
102 * @len: size of the available trace.
f2facc33 103 * @mode: how this TMC is being used.
4c324b5f 104 * @config_type: TMC variant, must be of type @tmc_config_type.
4f1ff3de 105 * @memwidth: width of the memory interface databus, in bytes.
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106 * @trigger_cntr: amount of words to store after a trigger.
107 */
108struct tmc_drvdata {
109 void __iomem *base;
110 struct device *dev;
111 struct coresight_device *csdev;
112 struct miscdevice miscdev;
113 spinlock_t spinlock;
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114 bool reading;
115 char *buf;
116 dma_addr_t paddr;
117 void __iomem *vaddr;
118 u32 size;
8505feae 119 u32 len;
f2facc33 120 local_t mode;
4c324b5f 121 enum tmc_config_type config_type;
4f1ff3de 122 enum tmc_mem_intf_width memwidth;
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123 u32 trigger_cntr;
124};
125
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126/* Generic functions */
127void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata);
128void tmc_flush_and_stop(struct tmc_drvdata *drvdata);
129void tmc_enable_hw(struct tmc_drvdata *drvdata);
130void tmc_disable_hw(struct tmc_drvdata *drvdata);
131
132/* ETB/ETF functions */
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133int tmc_read_prepare_etb(struct tmc_drvdata *drvdata);
134int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata);
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135extern const struct coresight_ops tmc_etb_cs_ops;
136extern const struct coresight_ops tmc_etf_cs_ops;
137
138/* ETR functions */
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139int tmc_read_prepare_etr(struct tmc_drvdata *drvdata);
140int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata);
6c6ed1e2 141extern const struct coresight_ops tmc_etr_cs_ops;
4c324b5f 142#endif
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