[deliverable/linux.git] / drivers / i2c / busses / i2c-amd8111.c

/*
 * SMBus 2.0 driver for AMD-8111 IO-Hub.
 *
 * Copyright (c) 2002 Vojtech Pavlik
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation version 2.
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/stddef.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/acpi.h>
#include <asm/io.h>

MODULE_LICENSE("GPL");
MODULE_AUTHOR ("Vojtech Pavlik <vojtech@suse.cz>");
MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver");

struct amd_smbus {
	struct pci_dev *dev;
	struct i2c_adapter adapter;
	int base;
	int size;
};

static struct pci_driver amd8111_driver;

/*
 * AMD PCI control registers definitions.
 */

#define AMD_PCI_MISC	0x48

#define AMD_PCI_MISC_SCI	0x04	/* deliver SCI */
#define AMD_PCI_MISC_INT	0x02	/* deliver PCI IRQ */
#define AMD_PCI_MISC_SPEEDUP	0x01	/* 16x clock speedup */

/*
 * ACPI 2.0 chapter 13 PCI interface definitions.
 */

#define AMD_EC_DATA	0x00	/* data register */
#define AMD_EC_SC	0x04	/* status of controller */
#define AMD_EC_CMD	0x04	/* command register */
#define AMD_EC_ICR	0x08	/* interrupt control register */

#define AMD_EC_SC_SMI	0x04	/* smi event pending */
#define AMD_EC_SC_SCI	0x02	/* sci event pending */
#define AMD_EC_SC_BURST	0x01	/* burst mode enabled */
#define AMD_EC_SC_CMD	0x08	/* byte in data reg is command */
#define AMD_EC_SC_IBF	0x02	/* data ready for embedded controller */
#define AMD_EC_SC_OBF	0x01	/* data ready for host */

#define AMD_EC_CMD_RD	0x80	/* read EC */
#define AMD_EC_CMD_WR	0x81	/* write EC */
#define AMD_EC_CMD_BE	0x82	/* enable burst mode */
#define AMD_EC_CMD_BD	0x83	/* disable burst mode */
#define AMD_EC_CMD_QR	0x84	/* query EC */

/*
 * ACPI 2.0 chapter 13 access of registers of the EC
 */

static unsigned int amd_ec_wait_write(struct amd_smbus *smbus)
{
	int timeout = 500;

	while ((inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF) && --timeout)
		udelay(1);

	if (!timeout) {
		dev_warn(&smbus->dev->dev,
			 "Timeout while waiting for IBF to clear\n");
		return -ETIMEDOUT;
	}

	return 0;
}

static unsigned int amd_ec_wait_read(struct amd_smbus *smbus)
{
	int timeout = 500;

	while ((~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF) && --timeout)
		udelay(1);

	if (!timeout) {
		dev_warn(&smbus->dev->dev,
			 "Timeout while waiting for OBF to set\n");
		return -ETIMEDOUT;
	}

	return 0;
}

static unsigned int amd_ec_read(struct amd_smbus *smbus, unsigned char address,
		unsigned char *data)
{
	int status;

	status = amd_ec_wait_write(smbus);
	if (status)
		return status;
	outb(AMD_EC_CMD_RD, smbus->base + AMD_EC_CMD);

	status = amd_ec_wait_write(smbus);
	if (status)
		return status;
	outb(address, smbus->base + AMD_EC_DATA);

	status = amd_ec_wait_read(smbus);
	if (status)
		return status;
	*data = inb(smbus->base + AMD_EC_DATA);

	return 0;
}

static unsigned int amd_ec_write(struct amd_smbus *smbus, unsigned char address,
		unsigned char data)
{
	int status;

	status = amd_ec_wait_write(smbus);
	if (status)
		return status;
	outb(AMD_EC_CMD_WR, smbus->base + AMD_EC_CMD);

	status = amd_ec_wait_write(smbus);
	if (status)
		return status;
	outb(address, smbus->base + AMD_EC_DATA);

	status = amd_ec_wait_write(smbus);
	if (status)
		return status;
	outb(data, smbus->base + AMD_EC_DATA);

	return 0;
}

/*
 * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
 */

#define AMD_SMB_PRTCL	0x00	/* protocol, PEC */
#define AMD_SMB_STS	0x01	/* status */
#define AMD_SMB_ADDR	0x02	/* address */
#define AMD_SMB_CMD	0x03	/* command */
#define AMD_SMB_DATA	0x04	/* 32 data registers */
#define AMD_SMB_BCNT	0x24	/* number of data bytes */
#define AMD_SMB_ALRM_A	0x25	/* alarm address */
#define AMD_SMB_ALRM_D	0x26	/* 2 bytes alarm data */

#define AMD_SMB_STS_DONE	0x80
#define AMD_SMB_STS_ALRM	0x40
#define AMD_SMB_STS_RES		0x20
#define AMD_SMB_STS_STATUS	0x1f

#define AMD_SMB_STATUS_OK	0x00
#define AMD_SMB_STATUS_FAIL	0x07
#define AMD_SMB_STATUS_DNAK	0x10
#define AMD_SMB_STATUS_DERR	0x11
#define AMD_SMB_STATUS_CMD_DENY	0x12
#define AMD_SMB_STATUS_UNKNOWN	0x13
#define AMD_SMB_STATUS_ACC_DENY	0x17
#define AMD_SMB_STATUS_TIMEOUT	0x18
#define AMD_SMB_STATUS_NOTSUP	0x19
#define AMD_SMB_STATUS_BUSY	0x1A
#define AMD_SMB_STATUS_PEC	0x1F

#define AMD_SMB_PRTCL_WRITE		0x00
#define AMD_SMB_PRTCL_READ		0x01
#define AMD_SMB_PRTCL_QUICK		0x02
#define AMD_SMB_PRTCL_BYTE		0x04
#define AMD_SMB_PRTCL_BYTE_DATA		0x06
#define AMD_SMB_PRTCL_WORD_DATA		0x08
#define AMD_SMB_PRTCL_BLOCK_DATA	0x0a
#define AMD_SMB_PRTCL_PROC_CALL		0x0c
#define AMD_SMB_PRTCL_BLOCK_PROC_CALL	0x0d
#define AMD_SMB_PRTCL_I2C_BLOCK_DATA	0x4a
#define AMD_SMB_PRTCL_PEC		0x80


static s32 amd8111_access(struct i2c_adapter * adap, u16 addr,
		unsigned short flags, char read_write, u8 command, int size,
		union i2c_smbus_data * data)
{
	struct amd_smbus *smbus = adap->algo_data;
	unsigned char protocol, len, pec, temp[2];
	int i;

	protocol = (read_write == I2C_SMBUS_READ) ? AMD_SMB_PRTCL_READ
						  : AMD_SMB_PRTCL_WRITE;
	pec = (flags & I2C_CLIENT_PEC) ? AMD_SMB_PRTCL_PEC : 0;

	switch (size) {
		case I2C_SMBUS_QUICK:
			protocol |= AMD_SMB_PRTCL_QUICK;
			read_write = I2C_SMBUS_WRITE;
			break;

		case I2C_SMBUS_BYTE:
			if (read_write == I2C_SMBUS_WRITE)
				amd_ec_write(smbus, AMD_SMB_CMD, command);
			protocol |= AMD_SMB_PRTCL_BYTE;
			break;

		case I2C_SMBUS_BYTE_DATA:
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			if (read_write == I2C_SMBUS_WRITE)
				amd_ec_write(smbus, AMD_SMB_DATA, data->byte);
			protocol |= AMD_SMB_PRTCL_BYTE_DATA;
			break;

		case I2C_SMBUS_WORD_DATA:
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			if (read_write == I2C_SMBUS_WRITE) {
				amd_ec_write(smbus, AMD_SMB_DATA,
					     data->word & 0xff);
				amd_ec_write(smbus, AMD_SMB_DATA + 1,
					     data->word >> 8);
			}
			protocol |= AMD_SMB_PRTCL_WORD_DATA | pec;
			break;

		case I2C_SMBUS_BLOCK_DATA:
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			if (read_write == I2C_SMBUS_WRITE) {
				len = min_t(u8, data->block[0],
					    I2C_SMBUS_BLOCK_MAX);
				amd_ec_write(smbus, AMD_SMB_BCNT, len);
				for (i = 0; i < len; i++)
					amd_ec_write(smbus, AMD_SMB_DATA + i,
						     data->block[i + 1]);
			}
			protocol |= AMD_SMB_PRTCL_BLOCK_DATA | pec;
			break;

		case I2C_SMBUS_I2C_BLOCK_DATA:
			len = min_t(u8, data->block[0],
				    I2C_SMBUS_BLOCK_MAX);
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			amd_ec_write(smbus, AMD_SMB_BCNT, len);
			if (read_write == I2C_SMBUS_WRITE)
				for (i = 0; i < len; i++)
					amd_ec_write(smbus, AMD_SMB_DATA + i,
						     data->block[i + 1]);
			protocol |= AMD_SMB_PRTCL_I2C_BLOCK_DATA;
			break;

		case I2C_SMBUS_PROC_CALL:
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			amd_ec_write(smbus, AMD_SMB_DATA, data->word & 0xff);
			amd_ec_write(smbus, AMD_SMB_DATA + 1, data->word >> 8);
			protocol = AMD_SMB_PRTCL_PROC_CALL | pec;
			read_write = I2C_SMBUS_READ;
			break;

		case I2C_SMBUS_BLOCK_PROC_CALL:
			len = min_t(u8, data->block[0],
				    I2C_SMBUS_BLOCK_MAX - 1);
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			amd_ec_write(smbus, AMD_SMB_BCNT, len);
			for (i = 0; i < len; i++)
				amd_ec_write(smbus, AMD_SMB_DATA + i,
					     data->block[i + 1]);
			protocol = AMD_SMB_PRTCL_BLOCK_PROC_CALL | pec;
			read_write = I2C_SMBUS_READ;
			break;

		default:
			dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
			return -EOPNOTSUPP;
	}

	amd_ec_write(smbus, AMD_SMB_ADDR, addr << 1);
	amd_ec_write(smbus, AMD_SMB_PRTCL, protocol);

	/* FIXME this discards status from ec_read(); so temp[0] will
	 * hold stack garbage ... the rest of this routine will act
	 * nonsensically.  Ignored ec_write() status might explain
	 * some such failures...
	 */
	amd_ec_read(smbus, AMD_SMB_STS, temp + 0);

	if (~temp[0] & AMD_SMB_STS_DONE) {
		udelay(500);
		amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
	}

	if (~temp[0] & AMD_SMB_STS_DONE) {
		msleep(1);
		amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
	}

	if ((~temp[0] & AMD_SMB_STS_DONE) || (temp[0] & AMD_SMB_STS_STATUS))
		return -EIO;

	if (read_write == I2C_SMBUS_WRITE)
		return 0;

	switch (size) {
		case I2C_SMBUS_BYTE:
		case I2C_SMBUS_BYTE_DATA:
			amd_ec_read(smbus, AMD_SMB_DATA, &data->byte);
			break;

		case I2C_SMBUS_WORD_DATA:
		case I2C_SMBUS_PROC_CALL:
			amd_ec_read(smbus, AMD_SMB_DATA, temp + 0);
			amd_ec_read(smbus, AMD_SMB_DATA + 1, temp + 1);
			data->word = (temp[1] << 8) | temp[0];
			break;

		case I2C_SMBUS_BLOCK_DATA:
		case I2C_SMBUS_BLOCK_PROC_CALL:
			amd_ec_read(smbus, AMD_SMB_BCNT, &len);
			len = min_t(u8, len, I2C_SMBUS_BLOCK_MAX);
		case I2C_SMBUS_I2C_BLOCK_DATA:
			for (i = 0; i < len; i++)
				amd_ec_read(smbus, AMD_SMB_DATA + i,
					    data->block + i + 1);
			data->block[0] = len;
			break;
	}

	return 0;
}


static u32 amd8111_func(struct i2c_adapter *adapter)
{
	return	I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
		I2C_FUNC_SMBUS_BYTE_DATA |
		I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA |
		I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
		I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_PEC;
}

static const struct i2c_algorithm smbus_algorithm = {
	.smbus_xfer = amd8111_access,
	.functionality = amd8111_func,
};


static struct pci_device_id amd8111_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS2) },
	{ 0, }
};

MODULE_DEVICE_TABLE (pci, amd8111_ids);

static int __devinit amd8111_probe(struct pci_dev *dev,
		const struct pci_device_id *id)
{
	struct amd_smbus *smbus;
	int error;

	if (!(pci_resource_flags(dev, 0) & IORESOURCE_IO))
		return -ENODEV;

	smbus = kzalloc(sizeof(struct amd_smbus), GFP_KERNEL);
	if (!smbus)
		return -ENOMEM;

	smbus->dev = dev;
	smbus->base = pci_resource_start(dev, 0);
	smbus->size = pci_resource_len(dev, 0);

	error = acpi_check_resource_conflict(&dev->resource[0]);
	if (error) {
		error = -ENODEV;
		goto out_kfree;
	}

	if (!request_region(smbus->base, smbus->size, amd8111_driver.name)) {
		error = -EBUSY;
		goto out_kfree;
	}

	smbus->adapter.owner = THIS_MODULE;
	snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
		"SMBus2 AMD8111 adapter at %04x", smbus->base);
	smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
	smbus->adapter.algo = &smbus_algorithm;
	smbus->adapter.algo_data = smbus;

	/* set up the sysfs linkage to our parent device */
	smbus->adapter.dev.parent = &dev->dev;

	pci_write_config_dword(smbus->dev, AMD_PCI_MISC, 0);
	error = i2c_add_adapter(&smbus->adapter);
	if (error)
		goto out_release_region;

	pci_set_drvdata(dev, smbus);
	return 0;

 out_release_region:
	release_region(smbus->base, smbus->size);
 out_kfree:
	kfree(smbus);
	return error;
}

static void __devexit amd8111_remove(struct pci_dev *dev)
{
	struct amd_smbus *smbus = pci_get_drvdata(dev);

	i2c_del_adapter(&smbus->adapter);
	release_region(smbus->base, smbus->size);
	kfree(smbus);
}

static struct pci_driver amd8111_driver = {
	.name		= "amd8111_smbus2",
	.id_table	= amd8111_ids,
	.probe		= amd8111_probe,
	.remove		= __devexit_p(amd8111_remove),
};

static int __init i2c_amd8111_init(void)
{
	return pci_register_driver(&amd8111_driver);
}

static void __exit i2c_amd8111_exit(void)
{
	pci_unregister_driver(&amd8111_driver);
}

module_init(i2c_amd8111_init);
module_exit(i2c_amd8111_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* SMBus 2.0 driver for AMD-8111 IO-Hub.
	3	*
	4	* Copyright (c) 2002 Vojtech Pavlik
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation version 2.
	9	*/
	10
1da177e4 LT	11	#include <linux/module.h>
	12	#include <linux/pci.h>
	13	#include <linux/kernel.h>
	14	#include <linux/stddef.h>
1da177e4 LT	15	#include <linux/ioport.h>
	16	#include <linux/init.h>
	17	#include <linux/i2c.h>
	18	#include <linux/delay.h>
54fb4a05	19	#include <linux/acpi.h>
1da177e4 LT	20	#include <asm/io.h>
	21
	22	MODULE_LICENSE("GPL");
	23	MODULE_AUTHOR ("Vojtech Pavlik <vojtech@suse.cz>");
	24	MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver");
	25
	26	struct amd_smbus {
	27	struct pci_dev *dev;
	28	struct i2c_adapter adapter;
	29	int base;
	30	int size;
	31	};
	32
d6072f84 JD	33	static struct pci_driver amd8111_driver;
d6072f84 JD	34
1da177e4 LT	35	/*
	36	* AMD PCI control registers definitions.
	37	*/
	38
	39	#define AMD_PCI_MISC 0x48
	40
	41	#define AMD_PCI_MISC_SCI 0x04 /* deliver SCI */
	42	#define AMD_PCI_MISC_INT 0x02 /* deliver PCI IRQ */
	43	#define AMD_PCI_MISC_SPEEDUP 0x01 /* 16x clock speedup */
	44
	45	/*
	46	* ACPI 2.0 chapter 13 PCI interface definitions.
	47	*/
	48
	49	#define AMD_EC_DATA 0x00 /* data register */
	50	#define AMD_EC_SC 0x04 /* status of controller */
	51	#define AMD_EC_CMD 0x04 /* command register */
	52	#define AMD_EC_ICR 0x08 /* interrupt control register */
	53
	54	#define AMD_EC_SC_SMI 0x04 /* smi event pending */
	55	#define AMD_EC_SC_SCI 0x02 /* sci event pending */
	56	#define AMD_EC_SC_BURST 0x01 /* burst mode enabled */
	57	#define AMD_EC_SC_CMD 0x08 /* byte in data reg is command */
	58	#define AMD_EC_SC_IBF 0x02 /* data ready for embedded controller */
	59	#define AMD_EC_SC_OBF 0x01 /* data ready for host */
	60
	61	#define AMD_EC_CMD_RD 0x80 /* read EC */
	62	#define AMD_EC_CMD_WR 0x81 /* write EC */
	63	#define AMD_EC_CMD_BE 0x82 /* enable burst mode */
	64	#define AMD_EC_CMD_BD 0x83 /* disable burst mode */
	65	#define AMD_EC_CMD_QR 0x84 /* query EC */
	66
	67	/*
	68	* ACPI 2.0 chapter 13 access of registers of the EC
	69	*/
	70
	71	static unsigned int amd_ec_wait_write(struct amd_smbus *smbus)
	72	{
	73	int timeout = 500;
	74
a746b578	75	while ((inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF) && --timeout)
1da177e4 LT	76	udelay(1);
	77
	78	if (!timeout) {
88b9e750 JD	79	dev_warn(&smbus->dev->dev,
88b9e750 JD	80	"Timeout while waiting for IBF to clear\n");
97140342	81	return -ETIMEDOUT;
1da177e4 LT	82	}
	83
	84	return 0;
	85	}
	86
	87	static unsigned int amd_ec_wait_read(struct amd_smbus *smbus)
	88	{
	89	int timeout = 500;
	90
a746b578	91	while ((~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF) && --timeout)
1da177e4 LT	92	udelay(1);
	93
	94	if (!timeout) {
88b9e750 JD	95	dev_warn(&smbus->dev->dev,
88b9e750 JD	96	"Timeout while waiting for OBF to set\n");
97140342	97	return -ETIMEDOUT;
1da177e4 LT	98	}
	99
	100	return 0;
	101	}
	102
88b9e750 JD	103	static unsigned int amd_ec_read(struct amd_smbus *smbus, unsigned char address,
88b9e750 JD	104	unsigned char *data)
1da177e4	105	{
97140342 DB	106	int status;
	107
	108	status = amd_ec_wait_write(smbus);
	109	if (status)
	110	return status;
1da177e4 LT	111	outb(AMD_EC_CMD_RD, smbus->base + AMD_EC_CMD);
1da177e4 LT	112
97140342 DB	113	status = amd_ec_wait_write(smbus);
	114	if (status)
	115	return status;
1da177e4 LT	116	outb(address, smbus->base + AMD_EC_DATA);
1da177e4 LT	117
97140342 DB	118	status = amd_ec_wait_read(smbus);
	119	if (status)
	120	return status;
1da177e4 LT	121	*data = inb(smbus->base + AMD_EC_DATA);
	122
	123	return 0;
	124	}
	125
88b9e750 JD	126	static unsigned int amd_ec_write(struct amd_smbus *smbus, unsigned char address,
88b9e750 JD	127	unsigned char data)
1da177e4	128	{
97140342 DB	129	int status;
	130
	131	status = amd_ec_wait_write(smbus);
	132	if (status)
	133	return status;
1da177e4 LT	134	outb(AMD_EC_CMD_WR, smbus->base + AMD_EC_CMD);
1da177e4 LT	135
97140342 DB	136	status = amd_ec_wait_write(smbus);
	137	if (status)
	138	return status;
1da177e4 LT	139	outb(address, smbus->base + AMD_EC_DATA);
1da177e4 LT	140
97140342 DB	141	status = amd_ec_wait_write(smbus);
	142	if (status)
	143	return status;
1da177e4 LT	144	outb(data, smbus->base + AMD_EC_DATA);
	145
	146	return 0;
	147	}
	148
	149	/*
	150	* ACPI 2.0 chapter 13 SMBus 2.0 EC register model
	151	*/
	152
	153	#define AMD_SMB_PRTCL 0x00 /* protocol, PEC */
	154	#define AMD_SMB_STS 0x01 /* status */
	155	#define AMD_SMB_ADDR 0x02 /* address */
	156	#define AMD_SMB_CMD 0x03 /* command */
	157	#define AMD_SMB_DATA 0x04 /* 32 data registers */
	158	#define AMD_SMB_BCNT 0x24 /* number of data bytes */
	159	#define AMD_SMB_ALRM_A 0x25 /* alarm address */
	160	#define AMD_SMB_ALRM_D 0x26 /* 2 bytes alarm data */
	161
	162	#define AMD_SMB_STS_DONE 0x80
	163	#define AMD_SMB_STS_ALRM 0x40
	164	#define AMD_SMB_STS_RES 0x20
	165	#define AMD_SMB_STS_STATUS 0x1f
	166
	167	#define AMD_SMB_STATUS_OK 0x00
	168	#define AMD_SMB_STATUS_FAIL 0x07
	169	#define AMD_SMB_STATUS_DNAK 0x10
	170	#define AMD_SMB_STATUS_DERR 0x11
	171	#define AMD_SMB_STATUS_CMD_DENY 0x12
	172	#define AMD_SMB_STATUS_UNKNOWN 0x13
	173	#define AMD_SMB_STATUS_ACC_DENY 0x17
	174	#define AMD_SMB_STATUS_TIMEOUT 0x18
	175	#define AMD_SMB_STATUS_NOTSUP 0x19
	176	#define AMD_SMB_STATUS_BUSY 0x1A
	177	#define AMD_SMB_STATUS_PEC 0x1F
	178
	179	#define AMD_SMB_PRTCL_WRITE 0x00
	180	#define AMD_SMB_PRTCL_READ 0x01
	181	#define AMD_SMB_PRTCL_QUICK 0x02
	182	#define AMD_SMB_PRTCL_BYTE 0x04
	183	#define AMD_SMB_PRTCL_BYTE_DATA 0x06
	184	#define AMD_SMB_PRTCL_WORD_DATA 0x08
	185	#define AMD_SMB_PRTCL_BLOCK_DATA 0x0a
	186	#define AMD_SMB_PRTCL_PROC_CALL 0x0c
	187	#define AMD_SMB_PRTCL_BLOCK_PROC_CALL 0x0d
	188	#define AMD_SMB_PRTCL_I2C_BLOCK_DATA 0x4a
	189	#define AMD_SMB_PRTCL_PEC 0x80
	190
	191
88b9e750 JD	192	static s32 amd8111_access(struct i2c_adapter * adap, u16 addr,
	193	unsigned short flags, char read_write, u8 command, int size,
	194	union i2c_smbus_data * data)
1da177e4 LT	195	{
	196	struct amd_smbus *smbus = adap->algo_data;
	197	unsigned char protocol, len, pec, temp[2];
	198	int i;
	199
88b9e750 JD	200	protocol = (read_write == I2C_SMBUS_READ) ? AMD_SMB_PRTCL_READ
88b9e750 JD	201	: AMD_SMB_PRTCL_WRITE;
1da177e4 LT	202	pec = (flags & I2C_CLIENT_PEC) ? AMD_SMB_PRTCL_PEC : 0;
	203
	204	switch (size) {
1da177e4 LT	205	case I2C_SMBUS_QUICK:
	206	protocol \|= AMD_SMB_PRTCL_QUICK;
	207	read_write = I2C_SMBUS_WRITE;
	208	break;
	209
	210	case I2C_SMBUS_BYTE:
	211	if (read_write == I2C_SMBUS_WRITE)
	212	amd_ec_write(smbus, AMD_SMB_CMD, command);
	213	protocol \|= AMD_SMB_PRTCL_BYTE;
	214	break;
	215
	216	case I2C_SMBUS_BYTE_DATA:
	217	amd_ec_write(smbus, AMD_SMB_CMD, command);
	218	if (read_write == I2C_SMBUS_WRITE)
	219	amd_ec_write(smbus, AMD_SMB_DATA, data->byte);
	220	protocol \|= AMD_SMB_PRTCL_BYTE_DATA;
	221	break;
	222
	223	case I2C_SMBUS_WORD_DATA:
	224	amd_ec_write(smbus, AMD_SMB_CMD, command);
	225	if (read_write == I2C_SMBUS_WRITE) {
88b9e750 JD	226	amd_ec_write(smbus, AMD_SMB_DATA,
	227	data->word & 0xff);
	228	amd_ec_write(smbus, AMD_SMB_DATA + 1,
	229	data->word >> 8);
1da177e4 LT	230	}
	231	protocol \|= AMD_SMB_PRTCL_WORD_DATA \| pec;
	232	break;
	233
	234	case I2C_SMBUS_BLOCK_DATA:
	235	amd_ec_write(smbus, AMD_SMB_CMD, command);
	236	if (read_write == I2C_SMBUS_WRITE) {
88b9e750 JD	237	len = min_t(u8, data->block[0],
88b9e750 JD	238	I2C_SMBUS_BLOCK_MAX);
1da177e4 LT	239	amd_ec_write(smbus, AMD_SMB_BCNT, len);
1da177e4 LT	240	for (i = 0; i < len; i++)
88b9e750 JD	241	amd_ec_write(smbus, AMD_SMB_DATA + i,
88b9e750 JD	242	data->block[i + 1]);
1da177e4 LT	243	}
	244	protocol \|= AMD_SMB_PRTCL_BLOCK_DATA \| pec;
	245	break;
	246
	247	case I2C_SMBUS_I2C_BLOCK_DATA:
88b9e750 JD	248	len = min_t(u8, data->block[0],
88b9e750 JD	249	I2C_SMBUS_BLOCK_MAX);
1da177e4 LT	250	amd_ec_write(smbus, AMD_SMB_CMD, command);
	251	amd_ec_write(smbus, AMD_SMB_BCNT, len);
	252	if (read_write == I2C_SMBUS_WRITE)
	253	for (i = 0; i < len; i++)
88b9e750 JD	254	amd_ec_write(smbus, AMD_SMB_DATA + i,
88b9e750 JD	255	data->block[i + 1]);
1da177e4 LT	256	protocol \|= AMD_SMB_PRTCL_I2C_BLOCK_DATA;
	257	break;
	258
	259	case I2C_SMBUS_PROC_CALL:
	260	amd_ec_write(smbus, AMD_SMB_CMD, command);
88b9e750	261	amd_ec_write(smbus, AMD_SMB_DATA, data->word & 0xff);
1da177e4 LT	262	amd_ec_write(smbus, AMD_SMB_DATA + 1, data->word >> 8);
	263	protocol = AMD_SMB_PRTCL_PROC_CALL \| pec;
	264	read_write = I2C_SMBUS_READ;
	265	break;
	266
	267	case I2C_SMBUS_BLOCK_PROC_CALL:
58791fd8 JD	268	len = min_t(u8, data->block[0],
58791fd8 JD	269	I2C_SMBUS_BLOCK_MAX - 1);
1da177e4 LT	270	amd_ec_write(smbus, AMD_SMB_CMD, command);
	271	amd_ec_write(smbus, AMD_SMB_BCNT, len);
	272	for (i = 0; i < len; i++)
88b9e750 JD	273	amd_ec_write(smbus, AMD_SMB_DATA + i,
88b9e750 JD	274	data->block[i + 1]);
1da177e4 LT	275	protocol = AMD_SMB_PRTCL_BLOCK_PROC_CALL \| pec;
	276	read_write = I2C_SMBUS_READ;
	277	break;
	278
1da177e4 LT	279	default:
1da177e4 LT	280	dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
97140342	281	return -EOPNOTSUPP;
1da177e4 LT	282	}
	283
	284	amd_ec_write(smbus, AMD_SMB_ADDR, addr << 1);
	285	amd_ec_write(smbus, AMD_SMB_PRTCL, protocol);
	286
97140342 DB	287	/* FIXME this discards status from ec_read(); so temp[0] will
	288	* hold stack garbage ... the rest of this routine will act
	289	* nonsensically. Ignored ec_write() status might explain
	290	* some such failures...
	291	*/
1da177e4 LT	292	amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
	293
	294	if (~temp[0] & AMD_SMB_STS_DONE) {
	295	udelay(500);
	296	amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
	297	}
	298
	299	if (~temp[0] & AMD_SMB_STS_DONE) {
	300	msleep(1);
	301	amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
	302	}
	303
	304	if ((~temp[0] & AMD_SMB_STS_DONE) \|\| (temp[0] & AMD_SMB_STS_STATUS))
97140342	305	return -EIO;
1da177e4 LT	306
	307	if (read_write == I2C_SMBUS_WRITE)
	308	return 0;
	309
	310	switch (size) {
1da177e4 LT	311	case I2C_SMBUS_BYTE:
	312	case I2C_SMBUS_BYTE_DATA:
	313	amd_ec_read(smbus, AMD_SMB_DATA, &data->byte);
	314	break;
	315
	316	case I2C_SMBUS_WORD_DATA:
	317	case I2C_SMBUS_PROC_CALL:
	318	amd_ec_read(smbus, AMD_SMB_DATA, temp + 0);
	319	amd_ec_read(smbus, AMD_SMB_DATA + 1, temp + 1);
	320	data->word = (temp[1] << 8) \| temp[0];
	321	break;
	322
	323	case I2C_SMBUS_BLOCK_DATA:
	324	case I2C_SMBUS_BLOCK_PROC_CALL:
	325	amd_ec_read(smbus, AMD_SMB_BCNT, &len);
88b9e750	326	len = min_t(u8, len, I2C_SMBUS_BLOCK_MAX);
1da177e4 LT	327	case I2C_SMBUS_I2C_BLOCK_DATA:
1da177e4 LT	328	for (i = 0; i < len; i++)
88b9e750 JD	329	amd_ec_read(smbus, AMD_SMB_DATA + i,
88b9e750 JD	330	data->block + i + 1);
1da177e4 LT	331	data->block[0] = len;
	332	break;
	333	}
	334
	335	return 0;
	336	}
	337
	338
	339	static u32 amd8111_func(struct i2c_adapter *adapter)
	340	{
88b9e750 JD	341	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
88b9e750 JD	342	I2C_FUNC_SMBUS_BYTE_DATA \|
1da177e4 LT	343	I2C_FUNC_SMBUS_WORD_DATA \| I2C_FUNC_SMBUS_BLOCK_DATA \|
1da177e4 LT	344	I2C_FUNC_SMBUS_PROC_CALL \| I2C_FUNC_SMBUS_BLOCK_PROC_CALL \|
6662cbb9	345	I2C_FUNC_SMBUS_I2C_BLOCK \| I2C_FUNC_SMBUS_PEC;
1da177e4 LT	346	}
1da177e4 LT	347
8f9082c5	348	static const struct i2c_algorithm smbus_algorithm = {
1da177e4 LT	349	.smbus_xfer = amd8111_access,
	350	.functionality = amd8111_func,
	351	};
	352
	353
	354	static struct pci_device_id amd8111_ids[] = {
	355	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS2) },
	356	{ 0, }
	357	};
	358
	359	MODULE_DEVICE_TABLE (pci, amd8111_ids);
	360
88b9e750 JD	361	static int __devinit amd8111_probe(struct pci_dev *dev,
88b9e750 JD	362	const struct pci_device_id *id)
1da177e4 LT	363	{
1da177e4 LT	364	struct amd_smbus *smbus;
88b9e750	365	int error;
1da177e4	366
88b9e750	367	if (!(pci_resource_flags(dev, 0) & IORESOURCE_IO))
1da177e4 LT	368	return -ENODEV;
1da177e4 LT	369
5263ebb5	370	smbus = kzalloc(sizeof(struct amd_smbus), GFP_KERNEL);
1da177e4 LT	371	if (!smbus)
1da177e4 LT	372	return -ENOMEM;
1da177e4 LT	373
	374	smbus->dev = dev;
	375	smbus->base = pci_resource_start(dev, 0);
	376	smbus->size = pci_resource_len(dev, 0);
	377
54fb4a05	378	error = acpi_check_resource_conflict(&dev->resource[0]);
18669eab JD	379	if (error) {
18669eab JD	380	error = -ENODEV;
54fb4a05	381	goto out_kfree;
18669eab	382	}
54fb4a05	383
88b9e750 JD	384	if (!request_region(smbus->base, smbus->size, amd8111_driver.name)) {
88b9e750 JD	385	error = -EBUSY;
1da177e4	386	goto out_kfree;
88b9e750	387	}
1da177e4 LT	388
1da177e4 LT	389	smbus->adapter.owner = THIS_MODULE;
2096b956	390	snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
1da177e4	391	"SMBus2 AMD8111 adapter at %04x", smbus->base);
3401b2ff	392	smbus->adapter.class = I2C_CLASS_HWMON \| I2C_CLASS_SPD;
1da177e4 LT	393	smbus->adapter.algo = &smbus_algorithm;
	394	smbus->adapter.algo_data = smbus;
	395
405ae7d3	396	/* set up the sysfs linkage to our parent device */
1da177e4 LT	397	smbus->adapter.dev.parent = &dev->dev;
1da177e4 LT	398
88b9e750	399	pci_write_config_dword(smbus->dev, AMD_PCI_MISC, 0);
1da177e4 LT	400	error = i2c_add_adapter(&smbus->adapter);
	401	if (error)
	402	goto out_release_region;
	403
1da177e4 LT	404	pci_set_drvdata(dev, smbus);
	405	return 0;
	406
	407	out_release_region:
	408	release_region(smbus->base, smbus->size);
	409	out_kfree:
	410	kfree(smbus);
88b9e750	411	return error;
1da177e4 LT	412	}
1da177e4 LT	413
1da177e4 LT	414	static void __devexit amd8111_remove(struct pci_dev *dev)
	415	{
	416	struct amd_smbus *smbus = pci_get_drvdata(dev);
	417
	418	i2c_del_adapter(&smbus->adapter);
	419	release_region(smbus->base, smbus->size);
	420	kfree(smbus);
	421	}
	422
	423	static struct pci_driver amd8111_driver = {
	424	.name = "amd8111_smbus2",
	425	.id_table = amd8111_ids,
	426	.probe = amd8111_probe,
	427	.remove = __devexit_p(amd8111_remove),
	428	};
	429
	430	static int __init i2c_amd8111_init(void)
	431	{
	432	return pci_register_driver(&amd8111_driver);
	433	}
	434
1da177e4 LT	435	static void __exit i2c_amd8111_exit(void)
	436	{
	437	pci_unregister_driver(&amd8111_driver);
	438	}
	439
	440	module_init(i2c_amd8111_init);
	441	module_exit(i2c_amd8111_exit);