[deliverable/linux.git] / drivers / i2c / busses / i2c-amd8111.c

/*
 * SMBus 2.0 driver for AMD-8111 IO-Hub.
 *
 * Copyright (c) 2002 Vojtech Pavlik
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation version 2.
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/stddef.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <asm/io.h>

MODULE_LICENSE("GPL");
MODULE_AUTHOR ("Vojtech Pavlik <vojtech@suse.cz>");
MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver");

struct amd_smbus {
	struct pci_dev *dev;
	struct i2c_adapter adapter;
	int base;
	int size;
};

static struct pci_driver amd8111_driver;

/*
 * AMD PCI control registers definitions.
 */

#define AMD_PCI_MISC	0x48

#define AMD_PCI_MISC_SCI	0x04	/* deliver SCI */
#define AMD_PCI_MISC_INT	0x02	/* deliver PCI IRQ */
#define AMD_PCI_MISC_SPEEDUP	0x01	/* 16x clock speedup */

/*
 * ACPI 2.0 chapter 13 PCI interface definitions.
 */

#define AMD_EC_DATA	0x00	/* data register */
#define AMD_EC_SC	0x04	/* status of controller */
#define AMD_EC_CMD	0x04	/* command register */
#define AMD_EC_ICR	0x08	/* interrupt control register */

#define AMD_EC_SC_SMI	0x04	/* smi event pending */
#define AMD_EC_SC_SCI	0x02	/* sci event pending */
#define AMD_EC_SC_BURST	0x01	/* burst mode enabled */
#define AMD_EC_SC_CMD	0x08	/* byte in data reg is command */
#define AMD_EC_SC_IBF	0x02	/* data ready for embedded controller */
#define AMD_EC_SC_OBF	0x01	/* data ready for host */

#define AMD_EC_CMD_RD	0x80	/* read EC */
#define AMD_EC_CMD_WR	0x81	/* write EC */
#define AMD_EC_CMD_BE	0x82	/* enable burst mode */
#define AMD_EC_CMD_BD	0x83	/* disable burst mode */
#define AMD_EC_CMD_QR	0x84	/* query EC */

/*
 * ACPI 2.0 chapter 13 access of registers of the EC
 */

static unsigned int amd_ec_wait_write(struct amd_smbus *smbus)
{
	int timeout = 500;

	while (timeout-- && (inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF))
		udelay(1);

	if (!timeout) {
		dev_warn(&smbus->dev->dev, "Timeout while waiting for IBF to clear\n");
		return -1;
	}

	return 0;
}

static unsigned int amd_ec_wait_read(struct amd_smbus *smbus)
{
	int timeout = 500;

	while (timeout-- && (~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF))
		udelay(1);

	if (!timeout) {
		dev_warn(&smbus->dev->dev, "Timeout while waiting for OBF to set\n");
		return -1;
	}

	return 0;
}

static unsigned int amd_ec_read(struct amd_smbus *smbus, unsigned char address, unsigned char *data)
{
	if (amd_ec_wait_write(smbus))
		return -1;
	outb(AMD_EC_CMD_RD, smbus->base + AMD_EC_CMD);

	if (amd_ec_wait_write(smbus))
		return -1;
	outb(address, smbus->base + AMD_EC_DATA);

	if (amd_ec_wait_read(smbus))
		return -1;
	*data = inb(smbus->base + AMD_EC_DATA);

	return 0;
}

static unsigned int amd_ec_write(struct amd_smbus *smbus, unsigned char address, unsigned char data)
{
	if (amd_ec_wait_write(smbus))
		return -1;
	outb(AMD_EC_CMD_WR, smbus->base + AMD_EC_CMD);

	if (amd_ec_wait_write(smbus))
		return -1;
	outb(address, smbus->base + AMD_EC_DATA);

	if (amd_ec_wait_write(smbus))
		return -1;
	outb(data, smbus->base + AMD_EC_DATA);

	return 0;
}

/*
 * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
 */

#define AMD_SMB_PRTCL	0x00	/* protocol, PEC */
#define AMD_SMB_STS	0x01	/* status */
#define AMD_SMB_ADDR	0x02	/* address */
#define AMD_SMB_CMD	0x03	/* command */
#define AMD_SMB_DATA	0x04	/* 32 data registers */
#define AMD_SMB_BCNT	0x24	/* number of data bytes */
#define AMD_SMB_ALRM_A	0x25	/* alarm address */
#define AMD_SMB_ALRM_D	0x26	/* 2 bytes alarm data */

#define AMD_SMB_STS_DONE	0x80
#define AMD_SMB_STS_ALRM	0x40
#define AMD_SMB_STS_RES		0x20
#define AMD_SMB_STS_STATUS	0x1f

#define AMD_SMB_STATUS_OK	0x00
#define AMD_SMB_STATUS_FAIL	0x07
#define AMD_SMB_STATUS_DNAK	0x10
#define AMD_SMB_STATUS_DERR	0x11
#define AMD_SMB_STATUS_CMD_DENY	0x12
#define AMD_SMB_STATUS_UNKNOWN	0x13
#define AMD_SMB_STATUS_ACC_DENY	0x17
#define AMD_SMB_STATUS_TIMEOUT	0x18
#define AMD_SMB_STATUS_NOTSUP	0x19
#define AMD_SMB_STATUS_BUSY	0x1A
#define AMD_SMB_STATUS_PEC	0x1F

#define AMD_SMB_PRTCL_WRITE		0x00
#define AMD_SMB_PRTCL_READ		0x01
#define AMD_SMB_PRTCL_QUICK		0x02
#define AMD_SMB_PRTCL_BYTE		0x04
#define AMD_SMB_PRTCL_BYTE_DATA		0x06
#define AMD_SMB_PRTCL_WORD_DATA		0x08
#define AMD_SMB_PRTCL_BLOCK_DATA	0x0a
#define AMD_SMB_PRTCL_PROC_CALL		0x0c
#define AMD_SMB_PRTCL_BLOCK_PROC_CALL	0x0d
#define AMD_SMB_PRTCL_I2C_BLOCK_DATA	0x4a
#define AMD_SMB_PRTCL_PEC		0x80


static s32 amd8111_access(struct i2c_adapter * adap, u16 addr, unsigned short flags,
		char read_write, u8 command, int size, union i2c_smbus_data * data)
{
	struct amd_smbus *smbus = adap->algo_data;
	unsigned char protocol, len, pec, temp[2];
	int i;

	protocol = (read_write == I2C_SMBUS_READ) ? AMD_SMB_PRTCL_READ : AMD_SMB_PRTCL_WRITE;
	pec = (flags & I2C_CLIENT_PEC) ? AMD_SMB_PRTCL_PEC : 0;

	switch (size) {

		case I2C_SMBUS_QUICK:
			protocol |= AMD_SMB_PRTCL_QUICK;
			read_write = I2C_SMBUS_WRITE;
			break;

		case I2C_SMBUS_BYTE:
			if (read_write == I2C_SMBUS_WRITE)
				amd_ec_write(smbus, AMD_SMB_CMD, command);
			protocol |= AMD_SMB_PRTCL_BYTE;
			break;

		case I2C_SMBUS_BYTE_DATA:
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			if (read_write == I2C_SMBUS_WRITE)
				amd_ec_write(smbus, AMD_SMB_DATA, data->byte);
			protocol |= AMD_SMB_PRTCL_BYTE_DATA;
			break;

		case I2C_SMBUS_WORD_DATA:
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			if (read_write == I2C_SMBUS_WRITE) {
				amd_ec_write(smbus, AMD_SMB_DATA, data->word);
				amd_ec_write(smbus, AMD_SMB_DATA + 1, data->word >> 8);
			}
			protocol |= AMD_SMB_PRTCL_WORD_DATA | pec;
			break;

		case I2C_SMBUS_BLOCK_DATA:
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			if (read_write == I2C_SMBUS_WRITE) {
				len = min_t(u8, data->block[0], 32);
				amd_ec_write(smbus, AMD_SMB_BCNT, len);
				for (i = 0; i < len; i++)
					amd_ec_write(smbus, AMD_SMB_DATA + i, data->block[i + 1]);
			}
			protocol |= AMD_SMB_PRTCL_BLOCK_DATA | pec;
			break;

		case I2C_SMBUS_I2C_BLOCK_DATA:
			len = min_t(u8, data->block[0], 32);
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			amd_ec_write(smbus, AMD_SMB_BCNT, len);
			if (read_write == I2C_SMBUS_WRITE)
				for (i = 0; i < len; i++)
					amd_ec_write(smbus, AMD_SMB_DATA + i, data->block[i + 1]);
			protocol |= AMD_SMB_PRTCL_I2C_BLOCK_DATA;
			break;

		case I2C_SMBUS_PROC_CALL:
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			amd_ec_write(smbus, AMD_SMB_DATA, data->word);
			amd_ec_write(smbus, AMD_SMB_DATA + 1, data->word >> 8);
			protocol = AMD_SMB_PRTCL_PROC_CALL | pec;
			read_write = I2C_SMBUS_READ;
			break;

		case I2C_SMBUS_BLOCK_PROC_CALL:
			len = min_t(u8, data->block[0], 31);
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			amd_ec_write(smbus, AMD_SMB_BCNT, len);
			for (i = 0; i < len; i++)
				amd_ec_write(smbus, AMD_SMB_DATA + i, data->block[i + 1]);
			protocol = AMD_SMB_PRTCL_BLOCK_PROC_CALL | pec;
			read_write = I2C_SMBUS_READ;
			break;

		case I2C_SMBUS_WORD_DATA_PEC:
		case I2C_SMBUS_BLOCK_DATA_PEC:
		case I2C_SMBUS_PROC_CALL_PEC:
		case I2C_SMBUS_BLOCK_PROC_CALL_PEC:
			dev_warn(&adap->dev, "Unexpected software PEC transaction %d\n.", size);
			return -1;

		default:
			dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
			return -1;
	}

	amd_ec_write(smbus, AMD_SMB_ADDR, addr << 1);
	amd_ec_write(smbus, AMD_SMB_PRTCL, protocol);

	amd_ec_read(smbus, AMD_SMB_STS, temp + 0);

	if (~temp[0] & AMD_SMB_STS_DONE) {
		udelay(500);
		amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
	}

	if (~temp[0] & AMD_SMB_STS_DONE) {
		msleep(1);
		amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
	}

	if ((~temp[0] & AMD_SMB_STS_DONE) || (temp[0] & AMD_SMB_STS_STATUS))
		return -1;

	if (read_write == I2C_SMBUS_WRITE)
		return 0;

	switch (size) {

		case I2C_SMBUS_BYTE:
		case I2C_SMBUS_BYTE_DATA:
			amd_ec_read(smbus, AMD_SMB_DATA, &data->byte);
			break;

		case I2C_SMBUS_WORD_DATA:
		case I2C_SMBUS_PROC_CALL:
			amd_ec_read(smbus, AMD_SMB_DATA, temp + 0);
			amd_ec_read(smbus, AMD_SMB_DATA + 1, temp + 1);
			data->word = (temp[1] << 8) | temp[0];
			break;

		case I2C_SMBUS_BLOCK_DATA:
		case I2C_SMBUS_BLOCK_PROC_CALL:
			amd_ec_read(smbus, AMD_SMB_BCNT, &len);
			len = min_t(u8, len, 32);
		case I2C_SMBUS_I2C_BLOCK_DATA:
			for (i = 0; i < len; i++)
				amd_ec_read(smbus, AMD_SMB_DATA + i, data->block + i + 1);
			data->block[0] = len;
			break;
	}

	return 0;
}


static u32 amd8111_func(struct i2c_adapter *adapter)
{
	return	I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA |
		I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA |
		I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
		I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_HWPEC_CALC;
}

static struct i2c_algorithm smbus_algorithm = {
	.smbus_xfer = amd8111_access,
	.functionality = amd8111_func,
};


static struct pci_device_id amd8111_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS2) },
	{ 0, }
};

MODULE_DEVICE_TABLE (pci, amd8111_ids);

static int __devinit amd8111_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct amd_smbus *smbus;
	int error = -ENODEV;

	if (~pci_resource_flags(dev, 0) & IORESOURCE_IO)
		return -ENODEV;

	smbus = kmalloc(sizeof(struct amd_smbus), GFP_KERNEL);
	if (!smbus)
		return -ENOMEM;
	memset(smbus, 0, sizeof(struct amd_smbus));

	smbus->dev = dev;
	smbus->base = pci_resource_start(dev, 0);
	smbus->size = pci_resource_len(dev, 0);

	if (!request_region(smbus->base, smbus->size, amd8111_driver.name))
		goto out_kfree;

	smbus->adapter.owner = THIS_MODULE;
	snprintf(smbus->adapter.name, I2C_NAME_SIZE,
		"SMBus2 AMD8111 adapter at %04x", smbus->base);
	smbus->adapter.class = I2C_CLASS_HWMON;
	smbus->adapter.algo = &smbus_algorithm;
	smbus->adapter.algo_data = smbus;

	/* set up the driverfs linkage to our parent device */
	smbus->adapter.dev.parent = &dev->dev;

	error = i2c_add_adapter(&smbus->adapter);
	if (error)
		goto out_release_region;

	pci_write_config_dword(smbus->dev, AMD_PCI_MISC, 0);
	pci_set_drvdata(dev, smbus);
	return 0;

 out_release_region:
	release_region(smbus->base, smbus->size);
 out_kfree:
	kfree(smbus);
	return -1;
}


static void __devexit amd8111_remove(struct pci_dev *dev)
{
	struct amd_smbus *smbus = pci_get_drvdata(dev);

	i2c_del_adapter(&smbus->adapter);
	release_region(smbus->base, smbus->size);
	kfree(smbus);
}

static struct pci_driver amd8111_driver = {
	.owner		= THIS_MODULE,
	.name		= "amd8111_smbus2",
	.id_table	= amd8111_ids,
	.probe		= amd8111_probe,
	.remove		= __devexit_p(amd8111_remove),
};

static int __init i2c_amd8111_init(void)
{
	return pci_register_driver(&amd8111_driver);
}


static void __exit i2c_amd8111_exit(void)
{
	pci_unregister_driver(&amd8111_driver);
}

module_init(i2c_amd8111_init);
module_exit(i2c_amd8111_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* SMBus 2.0 driver for AMD-8111 IO-Hub.
	3	*
	4	* Copyright (c) 2002 Vojtech Pavlik
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation version 2.
	9	*/
	10
1da177e4 LT	11	#include <linux/module.h>
	12	#include <linux/pci.h>
	13	#include <linux/kernel.h>
	14	#include <linux/stddef.h>
	15	#include <linux/sched.h>
	16	#include <linux/ioport.h>
	17	#include <linux/init.h>
	18	#include <linux/i2c.h>
	19	#include <linux/delay.h>
	20	#include <asm/io.h>
	21
	22	MODULE_LICENSE("GPL");
	23	MODULE_AUTHOR ("Vojtech Pavlik <vojtech@suse.cz>");
	24	MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver");
	25
	26	struct amd_smbus {
	27	struct pci_dev *dev;
	28	struct i2c_adapter adapter;
	29	int base;
	30	int size;
	31	};
	32
d6072f84 JD	33	static struct pci_driver amd8111_driver;
d6072f84 JD	34
1da177e4 LT	35	/*
	36	* AMD PCI control registers definitions.
	37	*/
	38
	39	#define AMD_PCI_MISC 0x48
	40
	41	#define AMD_PCI_MISC_SCI 0x04 /* deliver SCI */
	42	#define AMD_PCI_MISC_INT 0x02 /* deliver PCI IRQ */
	43	#define AMD_PCI_MISC_SPEEDUP 0x01 /* 16x clock speedup */
	44
	45	/*
	46	* ACPI 2.0 chapter 13 PCI interface definitions.
	47	*/
	48
	49	#define AMD_EC_DATA 0x00 /* data register */
	50	#define AMD_EC_SC 0x04 /* status of controller */
	51	#define AMD_EC_CMD 0x04 /* command register */
	52	#define AMD_EC_ICR 0x08 /* interrupt control register */
	53
	54	#define AMD_EC_SC_SMI 0x04 /* smi event pending */
	55	#define AMD_EC_SC_SCI 0x02 /* sci event pending */
	56	#define AMD_EC_SC_BURST 0x01 /* burst mode enabled */
	57	#define AMD_EC_SC_CMD 0x08 /* byte in data reg is command */
	58	#define AMD_EC_SC_IBF 0x02 /* data ready for embedded controller */
	59	#define AMD_EC_SC_OBF 0x01 /* data ready for host */
	60
	61	#define AMD_EC_CMD_RD 0x80 /* read EC */
	62	#define AMD_EC_CMD_WR 0x81 /* write EC */
	63	#define AMD_EC_CMD_BE 0x82 /* enable burst mode */
	64	#define AMD_EC_CMD_BD 0x83 /* disable burst mode */
	65	#define AMD_EC_CMD_QR 0x84 /* query EC */
	66
	67	/*
	68	* ACPI 2.0 chapter 13 access of registers of the EC
	69	*/
	70
	71	static unsigned int amd_ec_wait_write(struct amd_smbus *smbus)
	72	{
	73	int timeout = 500;
	74
	75	while (timeout-- && (inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF))
	76	udelay(1);
	77
	78	if (!timeout) {
	79	dev_warn(&smbus->dev->dev, "Timeout while waiting for IBF to clear\n");
	80	return -1;
	81	}
	82
	83	return 0;
	84	}
	85
	86	static unsigned int amd_ec_wait_read(struct amd_smbus *smbus)
	87	{
	88	int timeout = 500;
	89
	90	while (timeout-- && (~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF))
	91	udelay(1);
	92
	93	if (!timeout) {
	94	dev_warn(&smbus->dev->dev, "Timeout while waiting for OBF to set\n");
	95	return -1;
	96	}
	97
	98	return 0;
99	}
100
101	static unsigned int amd_ec_read(struct amd_smbus smbus, unsigned char address, unsigned char data)
102	{
103	if (amd_ec_wait_write(smbus))
104	return -1;
105	outb(AMD_EC_CMD_RD, smbus->base + AMD_EC_CMD);
106
107	if (amd_ec_wait_write(smbus))
108	return -1;
109	outb(address, smbus->base + AMD_EC_DATA);
110
111	if (amd_ec_wait_read(smbus))
112	return -1;
113	*data = inb(smbus->base + AMD_EC_DATA);
114
115	return 0;
116	}
117
118	static unsigned int amd_ec_write(struct amd_smbus *smbus, unsigned char address, unsigned char data)
119	{
120	if (amd_ec_wait_write(smbus))
121	return -1;
122	outb(AMD_EC_CMD_WR, smbus->base + AMD_EC_CMD);
123
124	if (amd_ec_wait_write(smbus))
125	return -1;
126	outb(address, smbus->base + AMD_EC_DATA);
127
128	if (amd_ec_wait_write(smbus))
129	return -1;
130	outb(data, smbus->base + AMD_EC_DATA);
131
132	return 0;
133	}
134
135	/*
136	* ACPI 2.0 chapter 13 SMBus 2.0 EC register model
137	*/
138
139	#define AMD_SMB_PRTCL 0x00 /* protocol, PEC */
140	#define AMD_SMB_STS 0x01 /* status */
141	#define AMD_SMB_ADDR 0x02 /* address */
142	#define AMD_SMB_CMD 0x03 /* command */
143	#define AMD_SMB_DATA 0x04 /* 32 data registers */
144	#define AMD_SMB_BCNT 0x24 /* number of data bytes */
145	#define AMD_SMB_ALRM_A 0x25 /* alarm address */
146	#define AMD_SMB_ALRM_D 0x26 /* 2 bytes alarm data */
147
148	#define AMD_SMB_STS_DONE 0x80
149	#define AMD_SMB_STS_ALRM 0x40
150	#define AMD_SMB_STS_RES 0x20
151	#define AMD_SMB_STS_STATUS 0x1f
152
153	#define AMD_SMB_STATUS_OK 0x00
154	#define AMD_SMB_STATUS_FAIL 0x07
155	#define AMD_SMB_STATUS_DNAK 0x10
156	#define AMD_SMB_STATUS_DERR 0x11
157	#define AMD_SMB_STATUS_CMD_DENY 0x12
158	#define AMD_SMB_STATUS_UNKNOWN 0x13
159	#define AMD_SMB_STATUS_ACC_DENY 0x17
160	#define AMD_SMB_STATUS_TIMEOUT 0x18
161	#define AMD_SMB_STATUS_NOTSUP 0x19
162	#define AMD_SMB_STATUS_BUSY 0x1A
163	#define AMD_SMB_STATUS_PEC 0x1F
164
165	#define AMD_SMB_PRTCL_WRITE 0x00
166	#define AMD_SMB_PRTCL_READ 0x01
167	#define AMD_SMB_PRTCL_QUICK 0x02
168	#define AMD_SMB_PRTCL_BYTE 0x04
169	#define AMD_SMB_PRTCL_BYTE_DATA 0x06
170	#define AMD_SMB_PRTCL_WORD_DATA 0x08
171	#define AMD_SMB_PRTCL_BLOCK_DATA 0x0a
172	#define AMD_SMB_PRTCL_PROC_CALL 0x0c
173	#define AMD_SMB_PRTCL_BLOCK_PROC_CALL 0x0d
174	#define AMD_SMB_PRTCL_I2C_BLOCK_DATA 0x4a
175	#define AMD_SMB_PRTCL_PEC 0x80
176
177
178	static s32 amd8111_access(struct i2c_adapter * adap, u16 addr, unsigned short flags,
179	char read_write, u8 command, int size, union i2c_smbus_data * data)
180	{
181	struct amd_smbus *smbus = adap->algo_data;
182	unsigned char protocol, len, pec, temp[2];
183	int i;
184
185	protocol = (read_write == I2C_SMBUS_READ) ? AMD_SMB_PRTCL_READ : AMD_SMB_PRTCL_WRITE;
186	pec = (flags & I2C_CLIENT_PEC) ? AMD_SMB_PRTCL_PEC : 0;
187
188	switch (size) {
189
190	case I2C_SMBUS_QUICK:
191	protocol \|= AMD_SMB_PRTCL_QUICK;
192	read_write = I2C_SMBUS_WRITE;
193	break;
194
195	case I2C_SMBUS_BYTE:
196	if (read_write == I2C_SMBUS_WRITE)
197	amd_ec_write(smbus, AMD_SMB_CMD, command);
198	protocol \|= AMD_SMB_PRTCL_BYTE;
199	break;
200
201	case I2C_SMBUS_BYTE_DATA:
202	amd_ec_write(smbus, AMD_SMB_CMD, command);
203	if (read_write == I2C_SMBUS_WRITE)
204	amd_ec_write(smbus, AMD_SMB_DATA, data->byte);
205	protocol \|= AMD_SMB_PRTCL_BYTE_DATA;
206	break;
207
208	case I2C_SMBUS_WORD_DATA:
209	amd_ec_write(smbus, AMD_SMB_CMD, command);
210	if (read_write == I2C_SMBUS_WRITE) {
211	amd_ec_write(smbus, AMD_SMB_DATA, data->word);
212	amd_ec_write(smbus, AMD_SMB_DATA + 1, data->word >> 8);
213	}
214	protocol \|= AMD_SMB_PRTCL_WORD_DATA \| pec;
215	break;
216
217	case I2C_SMBUS_BLOCK_DATA:
218	amd_ec_write(smbus, AMD_SMB_CMD, command);
219	if (read_write == I2C_SMBUS_WRITE) {
220	len = min_t(u8, data->block[0], 32);
221	amd_ec_write(smbus, AMD_SMB_BCNT, len);
222	for (i = 0; i < len; i++)
223	amd_ec_write(smbus, AMD_SMB_DATA + i, data->block[i + 1]);
224	}
225	protocol \|= AMD_SMB_PRTCL_BLOCK_DATA \| pec;
226	break;
227
228	case I2C_SMBUS_I2C_BLOCK_DATA:
229	len = min_t(u8, data->block[0], 32);
230	amd_ec_write(smbus, AMD_SMB_CMD, command);
231	amd_ec_write(smbus, AMD_SMB_BCNT, len);
232	if (read_write == I2C_SMBUS_WRITE)
233	for (i = 0; i < len; i++)
234	amd_ec_write(smbus, AMD_SMB_DATA + i, data->block[i + 1]);
235	protocol \|= AMD_SMB_PRTCL_I2C_BLOCK_DATA;
236	break;
237
238	case I2C_SMBUS_PROC_CALL:
239	amd_ec_write(smbus, AMD_SMB_CMD, command);
240	amd_ec_write(smbus, AMD_SMB_DATA, data->word);
241	amd_ec_write(smbus, AMD_SMB_DATA + 1, data->word >> 8);
242	protocol = AMD_SMB_PRTCL_PROC_CALL \| pec;
243	read_write = I2C_SMBUS_READ;
244	break;
245
246	case I2C_SMBUS_BLOCK_PROC_CALL:
1da177e4 LT	247	len = min_t(u8, data->block[0], 31);
	248	amd_ec_write(smbus, AMD_SMB_CMD, command);
	249	amd_ec_write(smbus, AMD_SMB_BCNT, len);
	250	for (i = 0; i < len; i++)
	251	amd_ec_write(smbus, AMD_SMB_DATA + i, data->block[i + 1]);
	252	protocol = AMD_SMB_PRTCL_BLOCK_PROC_CALL \| pec;
	253	read_write = I2C_SMBUS_READ;
	254	break;
	255
	256	case I2C_SMBUS_WORD_DATA_PEC:
	257	case I2C_SMBUS_BLOCK_DATA_PEC:
	258	case I2C_SMBUS_PROC_CALL_PEC:
	259	case I2C_SMBUS_BLOCK_PROC_CALL_PEC:
	260	dev_warn(&adap->dev, "Unexpected software PEC transaction %d\n.", size);
	261	return -1;
	262
	263	default:
	264	dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
	265	return -1;
	266	}
	267
	268	amd_ec_write(smbus, AMD_SMB_ADDR, addr << 1);
	269	amd_ec_write(smbus, AMD_SMB_PRTCL, protocol);
	270
	271	amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
	272
	273	if (~temp[0] & AMD_SMB_STS_DONE) {
	274	udelay(500);
	275	amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
	276	}
	277
	278	if (~temp[0] & AMD_SMB_STS_DONE) {
	279	msleep(1);
	280	amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
	281	}
	282
	283	if ((~temp[0] & AMD_SMB_STS_DONE) \|\| (temp[0] & AMD_SMB_STS_STATUS))
	284	return -1;
	285
	286	if (read_write == I2C_SMBUS_WRITE)
	287	return 0;
	288
	289	switch (size) {
	290
	291	case I2C_SMBUS_BYTE:
	292	case I2C_SMBUS_BYTE_DATA:
	293	amd_ec_read(smbus, AMD_SMB_DATA, &data->byte);
	294	break;
	295
	296	case I2C_SMBUS_WORD_DATA:
	297	case I2C_SMBUS_PROC_CALL:
	298	amd_ec_read(smbus, AMD_SMB_DATA, temp + 0);
	299	amd_ec_read(smbus, AMD_SMB_DATA + 1, temp + 1);
	300	data->word = (temp[1] << 8) \| temp[0];
	301	break;
	302
	303	case I2C_SMBUS_BLOCK_DATA:
	304	case I2C_SMBUS_BLOCK_PROC_CALL:
	305	amd_ec_read(smbus, AMD_SMB_BCNT, &len);
	306	len = min_t(u8, len, 32);
	307	case I2C_SMBUS_I2C_BLOCK_DATA:
	308	for (i = 0; i < len; i++)
	309	amd_ec_read(smbus, AMD_SMB_DATA + i, data->block + i + 1);
	310	data->block[0] = len;
311	break;
312	}
313
314	return 0;
315	}
316
317
318	static u32 amd8111_func(struct i2c_adapter *adapter)
319	{
320	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \| I2C_FUNC_SMBUS_BYTE_DATA \|
321	I2C_FUNC_SMBUS_WORD_DATA \| I2C_FUNC_SMBUS_BLOCK_DATA \|
322	I2C_FUNC_SMBUS_PROC_CALL \| I2C_FUNC_SMBUS_BLOCK_PROC_CALL \|
323	I2C_FUNC_SMBUS_I2C_BLOCK \| I2C_FUNC_SMBUS_HWPEC_CALC;
324	}
325
326	static struct i2c_algorithm smbus_algorithm = {
1da177e4 LT	327	.smbus_xfer = amd8111_access,
	328	.functionality = amd8111_func,
	329	};
	330
	331
	332	static struct pci_device_id amd8111_ids[] = {
	333	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS2) },
	334	{ 0, }
	335	};
	336
	337	MODULE_DEVICE_TABLE (pci, amd8111_ids);
	338
	339	static int __devinit amd8111_probe(struct pci_dev dev, const struct pci_device_id id)
	340	{
	341	struct amd_smbus *smbus;
	342	int error = -ENODEV;
	343
	344	if (~pci_resource_flags(dev, 0) & IORESOURCE_IO)
	345	return -ENODEV;
	346
	347	smbus = kmalloc(sizeof(struct amd_smbus), GFP_KERNEL);
	348	if (!smbus)
	349	return -ENOMEM;
	350	memset(smbus, 0, sizeof(struct amd_smbus));
	351
	352	smbus->dev = dev;
	353	smbus->base = pci_resource_start(dev, 0);
	354	smbus->size = pci_resource_len(dev, 0);
	355
d6072f84	356	if (!request_region(smbus->base, smbus->size, amd8111_driver.name))
1da177e4 LT	357	goto out_kfree;
	358
	359	smbus->adapter.owner = THIS_MODULE;
	360	snprintf(smbus->adapter.name, I2C_NAME_SIZE,
	361	"SMBus2 AMD8111 adapter at %04x", smbus->base);
	362	smbus->adapter.class = I2C_CLASS_HWMON;
	363	smbus->adapter.algo = &smbus_algorithm;
	364	smbus->adapter.algo_data = smbus;
	365
	366	/* set up the driverfs linkage to our parent device */
	367	smbus->adapter.dev.parent = &dev->dev;
	368
	369	error = i2c_add_adapter(&smbus->adapter);
	370	if (error)
	371	goto out_release_region;
	372
	373	pci_write_config_dword(smbus->dev, AMD_PCI_MISC, 0);
	374	pci_set_drvdata(dev, smbus);
	375	return 0;
	376
	377	out_release_region:
	378	release_region(smbus->base, smbus->size);
	379	out_kfree:
	380	kfree(smbus);
	381	return -1;
	382	}
	383
	384
	385	static void __devexit amd8111_remove(struct pci_dev *dev)
	386	{
	387	struct amd_smbus *smbus = pci_get_drvdata(dev);
	388
	389	i2c_del_adapter(&smbus->adapter);
	390	release_region(smbus->base, smbus->size);
	391	kfree(smbus);
	392	}
	393
	394	static struct pci_driver amd8111_driver = {
ccd7aa0c	395	.owner = THIS_MODULE,
1da177e4 LT	396	.name = "amd8111_smbus2",
	397	.id_table = amd8111_ids,
	398	.probe = amd8111_probe,
	399	.remove = __devexit_p(amd8111_remove),
	400	};
	401
	402	static int __init i2c_amd8111_init(void)
	403	{
	404	return pci_register_driver(&amd8111_driver);
	405	}
	406
	407
	408	static void __exit i2c_amd8111_exit(void)
	409	{
	410	pci_unregister_driver(&amd8111_driver);
	411	}
	412
	413	module_init(i2c_amd8111_init);
	414	module_exit(i2c_amd8111_exit);