[deliverable/linux.git] / drivers / i2c / busses / i2c-au1550.c

/*
 * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface
 * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com>
 *
 * 2.6 port by Matt Porter <mporter@kernel.crashing.org>
 *
 * The documentation describes this as an SMBus controller, but it doesn't
 * understand any of the SMBus protocol in hardware.  It's really an I2C
 * controller that could emulate most of the SMBus in software.
 *
 * This is just a skeleton adapter to use with the Au1550 PSC
 * algorithm.  It was developed for the Pb1550, but will work with
 * any Au1550 board that has a similar PSC configuration.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/errno.h>
#include <linux/i2c.h>
#include <linux/slab.h>

#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_psc.h>

#define PSC_SEL		0x00
#define PSC_CTRL	0x04
#define PSC_SMBCFG	0x08
#define PSC_SMBMSK	0x0C
#define PSC_SMBPCR	0x10
#define PSC_SMBSTAT	0x14
#define PSC_SMBEVNT	0x18
#define PSC_SMBTXRX	0x1C
#define PSC_SMBTMR	0x20

struct i2c_au1550_data {
	void __iomem *psc_base;
	int	xfer_timeout;
	struct i2c_adapter adap;
};

static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v)
{
	__raw_writel(v, a->psc_base + r);
	wmb();
}

static inline unsigned long RD(struct i2c_au1550_data *a, int r)
{
	return __raw_readl(a->psc_base + r);
}

static int wait_xfer_done(struct i2c_au1550_data *adap)
{
	int i;

	/* Wait for Tx Buffer Empty */
	for (i = 0; i < adap->xfer_timeout; i++) {
		if (RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_TE)
			return 0;

		udelay(1);
	}

	return -ETIMEDOUT;
}

static int wait_ack(struct i2c_au1550_data *adap)
{
	unsigned long stat;

	if (wait_xfer_done(adap))
		return -ETIMEDOUT;

	stat = RD(adap, PSC_SMBEVNT);
	if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0)
		return -ETIMEDOUT;

	return 0;
}

static int wait_master_done(struct i2c_au1550_data *adap)
{
	int i;

	/* Wait for Master Done. */
	for (i = 0; i < 2 * adap->xfer_timeout; i++) {
		if ((RD(adap, PSC_SMBEVNT) & PSC_SMBEVNT_MD) != 0)
			return 0;
		udelay(1);
	}

	return -ETIMEDOUT;
}

static int
do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q)
{
	unsigned long stat;

	/* Reset the FIFOs, clear events. */
	stat = RD(adap, PSC_SMBSTAT);
	WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR);

	if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) {
		WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC);
		while ((RD(adap, PSC_SMBPCR) & PSC_SMBPCR_DC) != 0)
			cpu_relax();
		udelay(50);
	}

	/* Write out the i2c chip address and specify operation */
	addr <<= 1;
	if (rd)
		addr |= 1;

	/* zero-byte xfers stop immediately */
	if (q)
		addr |= PSC_SMBTXRX_STP;

	/* Put byte into fifo, start up master. */
	WR(adap, PSC_SMBTXRX, addr);
	WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS);
	if (wait_ack(adap))
		return -EIO;
	return (q) ? wait_master_done(adap) : 0;
}

static int wait_for_rx_byte(struct i2c_au1550_data *adap, unsigned char *out)
{
	int j;

	if (wait_xfer_done(adap))
		return -EIO;

	j =  adap->xfer_timeout * 100;
	do {
		j--;
		if (j <= 0)
			return -EIO;

		if ((RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_RE) == 0)
			j = 0;
		else
			udelay(1);
	} while (j > 0);

	*out = RD(adap, PSC_SMBTXRX);

	return 0;
}

static int i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
		    unsigned int len)
{
	int i;

	if (len == 0)
		return 0;

	/* A read is performed by stuffing the transmit fifo with
	 * zero bytes for timing, waiting for bytes to appear in the
	 * receive fifo, then reading the bytes.
	 */
	i = 0;
	while (i < (len - 1)) {
		WR(adap, PSC_SMBTXRX, 0);
		if (wait_for_rx_byte(adap, &buf[i]))
			return -EIO;

		i++;
	}

	/* The last byte has to indicate transfer done. */
	WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP);
	if (wait_master_done(adap))
		return -EIO;

	buf[i] = (unsigned char)(RD(adap, PSC_SMBTXRX) & 0xff);
	return 0;
}

static int i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,
		     unsigned int len)
{
	int i;
	unsigned long data;

	if (len == 0)
		return 0;

	i = 0;
	while (i < (len-1)) {
		data = buf[i];
		WR(adap, PSC_SMBTXRX, data);
		if (wait_ack(adap))
			return -EIO;
		i++;
	}

	/* The last byte has to indicate transfer done. */
	data = buf[i];
	data |= PSC_SMBTXRX_STP;
	WR(adap, PSC_SMBTXRX, data);
	if (wait_master_done(adap))
		return -EIO;
	return 0;
}

static int
au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
{
	struct i2c_au1550_data *adap = i2c_adap->algo_data;
	struct i2c_msg *p;
	int i, err = 0;

	WR(adap, PSC_CTRL, PSC_CTRL_ENABLE);

	for (i = 0; !err && i < num; i++) {
		p = &msgs[i];
		err = do_address(adap, p->addr, p->flags & I2C_M_RD,
				 (p->len == 0));
		if (err || !p->len)
			continue;
		if (p->flags & I2C_M_RD)
			err = i2c_read(adap, p->buf, p->len);
		else
			err = i2c_write(adap, p->buf, p->len);
	}

	/* Return the number of messages processed, or the error code.
	*/
	if (err == 0)
		err = num;

	WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND);

	return err;
}

static u32 au1550_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm au1550_algo = {
	.master_xfer	= au1550_xfer,
	.functionality	= au1550_func,
};

static void i2c_au1550_setup(struct i2c_au1550_data *priv)
{
	unsigned long cfg;

	WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
	WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE);
	WR(priv, PSC_SMBCFG, 0);
	WR(priv, PSC_CTRL, PSC_CTRL_ENABLE);
	while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
		cpu_relax();

	cfg = PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | PSC_SMBCFG_DD_DISABLE;
	WR(priv, PSC_SMBCFG, cfg);

	/* Divide by 8 to get a 6.25 MHz clock.  The later protocol
	 * timings are based on this clock.
	 */
	cfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
	WR(priv, PSC_SMBCFG, cfg);
	WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK);

	/* Set the protocol timer values.  See Table 71 in the
	 * Au1550 Data Book for standard timing values.
	 */
	WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(20) | \
		PSC_SMBTMR_SET_PU(20) | PSC_SMBTMR_SET_SH(20) | \
		PSC_SMBTMR_SET_SU(20) | PSC_SMBTMR_SET_CL(20) | \
		PSC_SMBTMR_SET_CH(20));

	cfg |= PSC_SMBCFG_DE_ENABLE;
	WR(priv, PSC_SMBCFG, cfg);
	while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
		cpu_relax();

	WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND);
}

static void i2c_au1550_disable(struct i2c_au1550_data *priv)
{
	WR(priv, PSC_SMBCFG, 0);
	WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
}

/*
 * registering functions to load algorithms at runtime
 * Prior to calling us, the 50MHz clock frequency and routing
 * must have been set up for the PSC indicated by the adapter.
 */
static int
i2c_au1550_probe(struct platform_device *pdev)
{
	struct i2c_au1550_data *priv;
	struct resource *r;
	int ret;

	priv = devm_kzalloc(&pdev->dev, sizeof(struct i2c_au1550_data),
			    GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->psc_base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(priv->psc_base))
		return PTR_ERR(priv->psc_base);

	priv->xfer_timeout = 200;

	priv->adap.nr = pdev->id;
	priv->adap.algo = &au1550_algo;
	priv->adap.algo_data = priv;
	priv->adap.dev.parent = &pdev->dev;
	strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));

	/* Now, set up the PSC for SMBus PIO mode. */
	i2c_au1550_setup(priv);

	ret = i2c_add_numbered_adapter(&priv->adap);
	if (ret) {
		i2c_au1550_disable(priv);
		return ret;
	}

	platform_set_drvdata(pdev, priv);
	return 0;
}

static int i2c_au1550_remove(struct platform_device *pdev)
{
	struct i2c_au1550_data *priv = platform_get_drvdata(pdev);

	i2c_del_adapter(&priv->adap);
	i2c_au1550_disable(priv);
	return 0;
}

#ifdef CONFIG_PM
static int i2c_au1550_suspend(struct device *dev)
{
	struct i2c_au1550_data *priv = dev_get_drvdata(dev);

	i2c_au1550_disable(priv);

	return 0;
}

static int i2c_au1550_resume(struct device *dev)
{
	struct i2c_au1550_data *priv = dev_get_drvdata(dev);

	i2c_au1550_setup(priv);

	return 0;
}

static const struct dev_pm_ops i2c_au1550_pmops = {
	.suspend	= i2c_au1550_suspend,
	.resume		= i2c_au1550_resume,
};

#define AU1XPSC_SMBUS_PMOPS (&i2c_au1550_pmops)

#else
#define AU1XPSC_SMBUS_PMOPS NULL
#endif

static struct platform_driver au1xpsc_smbus_driver = {
	.driver = {
		.name	= "au1xpsc_smbus",
		.pm	= AU1XPSC_SMBUS_PMOPS,
	},
	.probe		= i2c_au1550_probe,
	.remove		= i2c_au1550_remove,
};

module_platform_driver(au1xpsc_smbus_driver);

MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC.");
MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:au1xpsc_smbus");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface
	3	* Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com>
	4	*
	5	* 2.6 port by Matt Porter <mporter@kernel.crashing.org>
	6	*
	7	* The documentation describes this as an SMBus controller, but it doesn't
	8	* understand any of the SMBus protocol in hardware. It's really an I2C
	9	* controller that could emulate most of the SMBus in software.
	10	*
	11	* This is just a skeleton adapter to use with the Au1550 PSC
	12	* algorithm. It was developed for the Pb1550, but will work with
	13	* any Au1550 board that has a similar PSC configuration.
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* as published by the Free Software Foundation; either version 2
	18	* of the License, or (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
1da177e4 LT	24	*/
1da177e4 LT	25
1da177e4 LT	26	#include <linux/delay.h>
	27	#include <linux/kernel.h>
	28	#include <linux/module.h>
8b798c4d	29	#include <linux/platform_device.h>
1da177e4 LT	30	#include <linux/errno.h>
1da177e4 LT	31	#include <linux/i2c.h>
8b798c4d	32	#include <linux/slab.h>
1da177e4	33
50d5676e	34	#include <asm/mach-au1x00/au1000.h>
1da177e4 LT	35	#include <asm/mach-au1x00/au1xxx_psc.h>
1da177e4 LT	36
c5de6467 ML	37	#define PSC_SEL 0x00
	38	#define PSC_CTRL 0x04
	39	#define PSC_SMBCFG 0x08
	40	#define PSC_SMBMSK 0x0C
	41	#define PSC_SMBPCR 0x10
	42	#define PSC_SMBSTAT 0x14
	43	#define PSC_SMBEVNT 0x18
	44	#define PSC_SMBTXRX 0x1C
	45	#define PSC_SMBTMR 0x20
	46
8b798c4d	47	struct i2c_au1550_data {
c5de6467	48	void __iomem *psc_base;
8b798c4d	49	int xfer_timeout;
8b798c4d	50	struct i2c_adapter adap;
8b798c4d	51	};
1da177e4	52
c5de6467	53	static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v)
1da177e4	54	{
c5de6467 ML	55	__raw_writel(v, a->psc_base + r);
	56	wmb();
	57	}
1da177e4	58
c5de6467 ML	59	static inline unsigned long RD(struct i2c_au1550_data *a, int r)
	60	{
	61	return __raw_readl(a->psc_base + r);
	62	}
1da177e4	63
c5de6467 ML	64	static int wait_xfer_done(struct i2c_au1550_data *adap)
	65	{
	66	int i;
	67
	68	/* Wait for Tx Buffer Empty */
1da177e4	69	for (i = 0; i < adap->xfer_timeout; i++) {
c5de6467	70	if (RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_TE)
1da177e4	71	return 0;
a202707e	72
1da177e4 LT	73	udelay(1);
	74	}
	75
	76	return -ETIMEDOUT;
	77	}
	78
c5de6467	79	static int wait_ack(struct i2c_au1550_data *adap)
1da177e4	80	{
c5de6467	81	unsigned long stat;
1da177e4 LT	82
	83	if (wait_xfer_done(adap))
	84	return -ETIMEDOUT;
	85
c5de6467	86	stat = RD(adap, PSC_SMBEVNT);
1da177e4 LT	87	if ((stat & (PSC_SMBEVNT_DN \| PSC_SMBEVNT_AN \| PSC_SMBEVNT_AL)) != 0)
	88	return -ETIMEDOUT;
	89
	90	return 0;
	91	}
	92
c5de6467	93	static int wait_master_done(struct i2c_au1550_data *adap)
1da177e4	94	{
c5de6467	95	int i;
1da177e4	96
c5de6467	97	/* Wait for Master Done. */
84785f12	98	for (i = 0; i < 2 * adap->xfer_timeout; i++) {
c5de6467	99	if ((RD(adap, PSC_SMBEVNT) & PSC_SMBEVNT_MD) != 0)
1da177e4 LT	100	return 0;
	101	udelay(1);
	102	}
	103
	104	return -ETIMEDOUT;
	105	}
	106
	107	static int
91f27958	108	do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q)
1da177e4	109	{
c5de6467	110	unsigned long stat;
1da177e4	111
c5de6467 ML	112	/* Reset the FIFOs, clear events. */
	113	stat = RD(adap, PSC_SMBSTAT);
	114	WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR);
8859942e DP	115
8859942e DP	116	if (!(stat & PSC_SMBSTAT_TE) \|\| !(stat & PSC_SMBSTAT_RE)) {
c5de6467 ML	117	WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC);
	118	while ((RD(adap, PSC_SMBPCR) & PSC_SMBPCR_DC) != 0)
	119	cpu_relax();
8859942e DP	120	udelay(50);
8859942e DP	121	}
1da177e4	122
c5de6467	123	/* Write out the i2c chip address and specify operation */
1da177e4 LT	124	addr <<= 1;
	125	if (rd)
	126	addr \|= 1;
	127
91f27958 ML	128	/* zero-byte xfers stop immediately */
	129	if (q)
	130	addr \|= PSC_SMBTXRX_STP;
	131
c5de6467 ML	132	/* Put byte into fifo, start up master. */
	133	WR(adap, PSC_SMBTXRX, addr);
	134	WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS);
1da177e4 LT	135	if (wait_ack(adap))
1da177e4 LT	136	return -EIO;
91f27958	137	return (q) ? wait_master_done(adap) : 0;
1da177e4 LT	138	}
1da177e4 LT	139
c5de6467	140	static int wait_for_rx_byte(struct i2c_au1550_data adap, unsigned char out)
1da177e4	141	{
c5de6467	142	int j;
1da177e4 LT	143
	144	if (wait_xfer_done(adap))
	145	return -EIO;
	146
1da177e4 LT	147	j = adap->xfer_timeout * 100;
	148	do {
	149	j--;
	150	if (j <= 0)
	151	return -EIO;
	152
c5de6467	153	if ((RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_RE) == 0)
1da177e4 LT	154	j = 0;
	155	else
	156	udelay(1);
	157	} while (j > 0);
c5de6467 ML	158
c5de6467 ML	159	*out = RD(adap, PSC_SMBTXRX);
1da177e4 LT	160
	161	return 0;
	162	}
	163
c5de6467	164	static int i2c_read(struct i2c_au1550_data adap, unsigned char buf,
1da177e4 LT	165	unsigned int len)
1da177e4 LT	166	{
c5de6467	167	int i;
1da177e4 LT	168
	169	if (len == 0)
	170	return 0;
	171
	172	/* A read is performed by stuffing the transmit fifo with
	173	* zero bytes for timing, waiting for bytes to appear in the
	174	* receive fifo, then reading the bytes.
	175	*/
1da177e4	176	i = 0;
c5de6467 ML	177	while (i < (len - 1)) {
	178	WR(adap, PSC_SMBTXRX, 0);
	179	if (wait_for_rx_byte(adap, &buf[i]))
1da177e4 LT	180	return -EIO;
1da177e4 LT	181
1da177e4 LT	182	i++;
	183	}
	184
c5de6467 ML	185	/* The last byte has to indicate transfer done. */
c5de6467 ML	186	WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP);
1da177e4 LT	187	if (wait_master_done(adap))
	188	return -EIO;
	189
c5de6467	190	buf[i] = (unsigned char)(RD(adap, PSC_SMBTXRX) & 0xff);
1da177e4 LT	191	return 0;
	192	}
	193
c5de6467	194	static int i2c_write(struct i2c_au1550_data adap, unsigned char buf,
1da177e4 LT	195	unsigned int len)
1da177e4 LT	196	{
c5de6467 ML	197	int i;
c5de6467 ML	198	unsigned long data;
1da177e4 LT	199
	200	if (len == 0)
	201	return 0;
	202
1da177e4 LT	203	i = 0;
	204	while (i < (len-1)) {
	205	data = buf[i];
c5de6467	206	WR(adap, PSC_SMBTXRX, data);
1da177e4 LT	207	if (wait_ack(adap))
	208	return -EIO;
	209	i++;
	210	}
	211
c5de6467	212	/* The last byte has to indicate transfer done. */
1da177e4 LT	213	data = buf[i];
1da177e4 LT	214	data \|= PSC_SMBTXRX_STP;
c5de6467	215	WR(adap, PSC_SMBTXRX, data);
1da177e4 LT	216	if (wait_master_done(adap))
	217	return -EIO;
	218	return 0;
	219	}
	220
	221	static int
	222	au1550_xfer(struct i2c_adapter i2c_adap, struct i2c_msg msgs, int num)
	223	{
	224	struct i2c_au1550_data *adap = i2c_adap->algo_data;
	225	struct i2c_msg *p;
	226	int i, err = 0;
	227
c5de6467	228	WR(adap, PSC_CTRL, PSC_CTRL_ENABLE);
f09f71b2	229
1da177e4 LT	230	for (i = 0; !err && i < num; i++) {
1da177e4 LT	231	p = &msgs[i];
91f27958 ML	232	err = do_address(adap, p->addr, p->flags & I2C_M_RD,
91f27958 ML	233	(p->len == 0));
1da177e4 LT	234	if (err \|\| !p->len)
	235	continue;
	236	if (p->flags & I2C_M_RD)
	237	err = i2c_read(adap, p->buf, p->len);
	238	else
	239	err = i2c_write(adap, p->buf, p->len);
	240	}
	241
	242	/* Return the number of messages processed, or the error code.
	243	*/
	244	if (err == 0)
	245	err = num;
f09f71b2	246
c5de6467	247	WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND);
f09f71b2	248
1da177e4 LT	249	return err;
	250	}
	251
c5de6467	252	static u32 au1550_func(struct i2c_adapter *adap)
1da177e4	253	{
6ed07134	254	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
1da177e4 LT	255	}
1da177e4 LT	256
8f9082c5	257	static const struct i2c_algorithm au1550_algo = {
1da177e4 LT	258	.master_xfer = au1550_xfer,
	259	.functionality = au1550_func,
	260	};
	261
f09f71b2 ML	262	static void i2c_au1550_setup(struct i2c_au1550_data *priv)
f09f71b2 ML	263	{
c5de6467	264	unsigned long cfg;
f09f71b2	265
c5de6467 ML	266	WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
	267	WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE);
	268	WR(priv, PSC_SMBCFG, 0);
	269	WR(priv, PSC_CTRL, PSC_CTRL_ENABLE);
	270	while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
	271	cpu_relax();
	272
	273	cfg = PSC_SMBCFG_RT_FIFO8 \| PSC_SMBCFG_TT_FIFO8 \| PSC_SMBCFG_DD_DISABLE;
	274	WR(priv, PSC_SMBCFG, cfg);
f09f71b2 ML	275
	276	/* Divide by 8 to get a 6.25 MHz clock. The later protocol
	277	* timings are based on this clock.
	278	*/
c5de6467 ML	279	cfg \|= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
	280	WR(priv, PSC_SMBCFG, cfg);
	281	WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK);
f09f71b2 ML	282
	283	/* Set the protocol timer values. See Table 71 in the
	284	* Au1550 Data Book for standard timing values.
	285	*/
8a5e3d47 ML	286	WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) \| PSC_SMBTMR_SET_PS(20) \| \
	287	PSC_SMBTMR_SET_PU(20) \| PSC_SMBTMR_SET_SH(20) \| \
	288	PSC_SMBTMR_SET_SU(20) \| PSC_SMBTMR_SET_CL(20) \| \
	289	PSC_SMBTMR_SET_CH(20));
f09f71b2	290
c5de6467 ML	291	cfg \|= PSC_SMBCFG_DE_ENABLE;
	292	WR(priv, PSC_SMBCFG, cfg);
	293	while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
	294	cpu_relax();
f09f71b2	295
c5de6467	296	WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND);
f09f71b2 ML	297	}
	298
	299	static void i2c_au1550_disable(struct i2c_au1550_data *priv)
	300	{
c5de6467 ML	301	WR(priv, PSC_SMBCFG, 0);
c5de6467 ML	302	WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
f09f71b2 ML	303	}
f09f71b2 ML	304
1da177e4 LT	305	/*
	306	* registering functions to load algorithms at runtime
	307	* Prior to calling us, the 50MHz clock frequency and routing
	308	* must have been set up for the PSC indicated by the adapter.
	309	*/
0b255e92	310	static int
8b798c4d	311	i2c_au1550_probe(struct platform_device *pdev)
1da177e4	312	{
8b798c4d	313	struct i2c_au1550_data *priv;
8b798c4d	314	struct resource *r;
8b798c4d ML	315	int ret;
8b798c4d ML	316
174f2366 AL	317	priv = devm_kzalloc(&pdev->dev, sizeof(struct i2c_au1550_data),
	318	GFP_KERNEL);
	319	if (!priv)
	320	return -ENOMEM;
1da177e4	321
174f2366 AL	322	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	323	priv->psc_base = devm_ioremap_resource(&pdev->dev, r);
	324	if (IS_ERR(priv->psc_base))
	325	return PTR_ERR(priv->psc_base);
8b798c4d	326
8b798c4d	327	priv->xfer_timeout = 200;
8b798c4d	328
8b798c4d ML	329	priv->adap.nr = pdev->id;
	330	priv->adap.algo = &au1550_algo;
	331	priv->adap.algo_data = priv;
	332	priv->adap.dev.parent = &pdev->dev;
	333	strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));
1da177e4	334
c5de6467	335	/* Now, set up the PSC for SMBus PIO mode. */
f09f71b2	336	i2c_au1550_setup(priv);
1da177e4	337
8b798c4d	338	ret = i2c_add_numbered_adapter(&priv->adap);
174f2366 AL	339	if (ret) {
	340	i2c_au1550_disable(priv);
	341	return ret;
8b798c4d ML	342	}
8b798c4d ML	343
174f2366 AL	344	platform_set_drvdata(pdev, priv);
174f2366 AL	345	return 0;
8b798c4d	346	}
1da177e4	347
0b255e92	348	static int i2c_au1550_remove(struct platform_device *pdev)
1da177e4	349	{
8b798c4d	350	struct i2c_au1550_data *priv = platform_get_drvdata(pdev);
8b798c4d	351
8b798c4d	352	i2c_del_adapter(&priv->adap);
f09f71b2	353	i2c_au1550_disable(priv);
8b798c4d	354	return 0;
1da177e4 LT	355	}
1da177e4 LT	356
f09f71b2	357	#ifdef CONFIG_PM
46f344e2	358	static int i2c_au1550_suspend(struct device *dev)
1da177e4	359	{
46f344e2	360	struct i2c_au1550_data *priv = dev_get_drvdata(dev);
8b798c4d	361
f09f71b2 ML	362	i2c_au1550_disable(priv);
f09f71b2 ML	363
1da177e4 LT	364	return 0;
	365	}
	366
46f344e2	367	static int i2c_au1550_resume(struct device *dev)
1da177e4	368	{
46f344e2	369	struct i2c_au1550_data *priv = dev_get_drvdata(dev);
8b798c4d	370
f09f71b2 ML	371	i2c_au1550_setup(priv);
f09f71b2 ML	372
1da177e4 LT	373	return 0;
1da177e4 LT	374	}
46f344e2 ML	375
	376	static const struct dev_pm_ops i2c_au1550_pmops = {
	377	.suspend = i2c_au1550_suspend,
	378	.resume = i2c_au1550_resume,
	379	};
	380
	381	#define AU1XPSC_SMBUS_PMOPS (&i2c_au1550_pmops)
	382
f09f71b2	383	#else
46f344e2	384	#define AU1XPSC_SMBUS_PMOPS NULL
f09f71b2	385	#endif
1da177e4	386
8b798c4d ML	387	static struct platform_driver au1xpsc_smbus_driver = {
	388	.driver = {
	389	.name = "au1xpsc_smbus",
46f344e2	390	.pm = AU1XPSC_SMBUS_PMOPS,
8b798c4d ML	391	},
8b798c4d ML	392	.probe = i2c_au1550_probe,
0b255e92	393	.remove = i2c_au1550_remove,
1da177e4 LT	394	};
1da177e4 LT	395
a3664b51	396	module_platform_driver(au1xpsc_smbus_driver);
1da177e4 LT	397
	398	MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC.");
	399	MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550");
	400	MODULE_LICENSE("GPL");
add8eda7	401	MODULE_ALIAS("platform:au1xpsc_smbus");