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1da177e4 LT |
1 | /* |
2 | * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface | |
3 | * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com> | |
4 | * | |
5 | * 2.6 port by Matt Porter <mporter@kernel.crashing.org> | |
6 | * | |
7 | * The documentation describes this as an SMBus controller, but it doesn't | |
8 | * understand any of the SMBus protocol in hardware. It's really an I2C | |
9 | * controller that could emulate most of the SMBus in software. | |
10 | * | |
11 | * This is just a skeleton adapter to use with the Au1550 PSC | |
12 | * algorithm. It was developed for the Pb1550, but will work with | |
13 | * any Au1550 board that has a similar PSC configuration. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version 2 | |
18 | * of the License, or (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/delay.h> |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/errno.h> | |
35 | #include <linux/i2c.h> | |
36 | ||
37 | #include <asm/mach-au1x00/au1000.h> | |
38 | #include <asm/mach-pb1x00/pb1550.h> | |
39 | #include <asm/mach-au1x00/au1xxx_psc.h> | |
40 | ||
41 | #include "i2c-au1550.h" | |
42 | ||
43 | static int | |
44 | wait_xfer_done(struct i2c_au1550_data *adap) | |
45 | { | |
46 | u32 stat; | |
47 | int i; | |
48 | volatile psc_smb_t *sp; | |
49 | ||
50 | sp = (volatile psc_smb_t *)(adap->psc_base); | |
51 | ||
52 | /* Wait for Tx FIFO Underflow. | |
53 | */ | |
54 | for (i = 0; i < adap->xfer_timeout; i++) { | |
55 | stat = sp->psc_smbevnt; | |
56 | au_sync(); | |
57 | if ((stat & PSC_SMBEVNT_TU) != 0) { | |
58 | /* Clear it. */ | |
59 | sp->psc_smbevnt = PSC_SMBEVNT_TU; | |
60 | au_sync(); | |
61 | return 0; | |
62 | } | |
63 | udelay(1); | |
64 | } | |
65 | ||
66 | return -ETIMEDOUT; | |
67 | } | |
68 | ||
69 | static int | |
70 | wait_ack(struct i2c_au1550_data *adap) | |
71 | { | |
72 | u32 stat; | |
73 | volatile psc_smb_t *sp; | |
74 | ||
75 | if (wait_xfer_done(adap)) | |
76 | return -ETIMEDOUT; | |
77 | ||
78 | sp = (volatile psc_smb_t *)(adap->psc_base); | |
79 | ||
80 | stat = sp->psc_smbevnt; | |
81 | au_sync(); | |
82 | ||
83 | if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0) | |
84 | return -ETIMEDOUT; | |
85 | ||
86 | return 0; | |
87 | } | |
88 | ||
89 | static int | |
90 | wait_master_done(struct i2c_au1550_data *adap) | |
91 | { | |
92 | u32 stat; | |
93 | int i; | |
94 | volatile psc_smb_t *sp; | |
95 | ||
96 | sp = (volatile psc_smb_t *)(adap->psc_base); | |
97 | ||
98 | /* Wait for Master Done. | |
99 | */ | |
100 | for (i = 0; i < adap->xfer_timeout; i++) { | |
101 | stat = sp->psc_smbevnt; | |
102 | au_sync(); | |
103 | if ((stat & PSC_SMBEVNT_MD) != 0) | |
104 | return 0; | |
105 | udelay(1); | |
106 | } | |
107 | ||
108 | return -ETIMEDOUT; | |
109 | } | |
110 | ||
111 | static int | |
112 | do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd) | |
113 | { | |
114 | volatile psc_smb_t *sp; | |
115 | u32 stat; | |
116 | ||
117 | sp = (volatile psc_smb_t *)(adap->psc_base); | |
118 | ||
119 | /* Reset the FIFOs, clear events. | |
120 | */ | |
8859942e | 121 | stat = sp->psc_smbstat; |
1da177e4 LT |
122 | sp->psc_smbevnt = PSC_SMBEVNT_ALLCLR; |
123 | au_sync(); | |
8859942e DP |
124 | |
125 | if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) { | |
126 | sp->psc_smbpcr = PSC_SMBPCR_DC; | |
1da177e4 | 127 | au_sync(); |
8859942e DP |
128 | do { |
129 | stat = sp->psc_smbpcr; | |
130 | au_sync(); | |
131 | } while ((stat & PSC_SMBPCR_DC) != 0); | |
132 | udelay(50); | |
133 | } | |
1da177e4 LT |
134 | |
135 | /* Write out the i2c chip address and specify operation | |
136 | */ | |
137 | addr <<= 1; | |
138 | if (rd) | |
139 | addr |= 1; | |
140 | ||
141 | /* Put byte into fifo, start up master. | |
142 | */ | |
143 | sp->psc_smbtxrx = addr; | |
144 | au_sync(); | |
145 | sp->psc_smbpcr = PSC_SMBPCR_MS; | |
146 | au_sync(); | |
147 | if (wait_ack(adap)) | |
148 | return -EIO; | |
149 | return 0; | |
150 | } | |
151 | ||
152 | static u32 | |
153 | wait_for_rx_byte(struct i2c_au1550_data *adap, u32 *ret_data) | |
154 | { | |
155 | int j; | |
156 | u32 data, stat; | |
157 | volatile psc_smb_t *sp; | |
158 | ||
159 | if (wait_xfer_done(adap)) | |
160 | return -EIO; | |
161 | ||
162 | sp = (volatile psc_smb_t *)(adap->psc_base); | |
163 | ||
164 | j = adap->xfer_timeout * 100; | |
165 | do { | |
166 | j--; | |
167 | if (j <= 0) | |
168 | return -EIO; | |
169 | ||
170 | stat = sp->psc_smbstat; | |
171 | au_sync(); | |
172 | if ((stat & PSC_SMBSTAT_RE) == 0) | |
173 | j = 0; | |
174 | else | |
175 | udelay(1); | |
176 | } while (j > 0); | |
177 | data = sp->psc_smbtxrx; | |
178 | au_sync(); | |
179 | *ret_data = data; | |
180 | ||
181 | return 0; | |
182 | } | |
183 | ||
184 | static int | |
185 | i2c_read(struct i2c_au1550_data *adap, unsigned char *buf, | |
186 | unsigned int len) | |
187 | { | |
188 | int i; | |
189 | u32 data; | |
190 | volatile psc_smb_t *sp; | |
191 | ||
192 | if (len == 0) | |
193 | return 0; | |
194 | ||
195 | /* A read is performed by stuffing the transmit fifo with | |
196 | * zero bytes for timing, waiting for bytes to appear in the | |
197 | * receive fifo, then reading the bytes. | |
198 | */ | |
199 | ||
200 | sp = (volatile psc_smb_t *)(adap->psc_base); | |
201 | ||
202 | i = 0; | |
203 | while (i < (len-1)) { | |
204 | sp->psc_smbtxrx = 0; | |
205 | au_sync(); | |
206 | if (wait_for_rx_byte(adap, &data)) | |
207 | return -EIO; | |
208 | ||
209 | buf[i] = data; | |
210 | i++; | |
211 | } | |
212 | ||
213 | /* The last byte has to indicate transfer done. | |
214 | */ | |
215 | sp->psc_smbtxrx = PSC_SMBTXRX_STP; | |
216 | au_sync(); | |
217 | if (wait_master_done(adap)) | |
218 | return -EIO; | |
219 | ||
220 | data = sp->psc_smbtxrx; | |
221 | au_sync(); | |
222 | buf[i] = data; | |
223 | return 0; | |
224 | } | |
225 | ||
226 | static int | |
227 | i2c_write(struct i2c_au1550_data *adap, unsigned char *buf, | |
228 | unsigned int len) | |
229 | { | |
230 | int i; | |
231 | u32 data; | |
232 | volatile psc_smb_t *sp; | |
233 | ||
234 | if (len == 0) | |
235 | return 0; | |
236 | ||
237 | sp = (volatile psc_smb_t *)(adap->psc_base); | |
238 | ||
239 | i = 0; | |
240 | while (i < (len-1)) { | |
241 | data = buf[i]; | |
242 | sp->psc_smbtxrx = data; | |
243 | au_sync(); | |
244 | if (wait_ack(adap)) | |
245 | return -EIO; | |
246 | i++; | |
247 | } | |
248 | ||
249 | /* The last byte has to indicate transfer done. | |
250 | */ | |
251 | data = buf[i]; | |
252 | data |= PSC_SMBTXRX_STP; | |
253 | sp->psc_smbtxrx = data; | |
254 | au_sync(); | |
255 | if (wait_master_done(adap)) | |
256 | return -EIO; | |
257 | return 0; | |
258 | } | |
259 | ||
260 | static int | |
261 | au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) | |
262 | { | |
263 | struct i2c_au1550_data *adap = i2c_adap->algo_data; | |
264 | struct i2c_msg *p; | |
265 | int i, err = 0; | |
266 | ||
267 | for (i = 0; !err && i < num; i++) { | |
268 | p = &msgs[i]; | |
269 | err = do_address(adap, p->addr, p->flags & I2C_M_RD); | |
270 | if (err || !p->len) | |
271 | continue; | |
272 | if (p->flags & I2C_M_RD) | |
273 | err = i2c_read(adap, p->buf, p->len); | |
274 | else | |
275 | err = i2c_write(adap, p->buf, p->len); | |
276 | } | |
277 | ||
278 | /* Return the number of messages processed, or the error code. | |
279 | */ | |
280 | if (err == 0) | |
281 | err = num; | |
282 | return err; | |
283 | } | |
284 | ||
285 | static u32 | |
286 | au1550_func(struct i2c_adapter *adap) | |
287 | { | |
288 | return I2C_FUNC_I2C; | |
289 | } | |
290 | ||
291 | static struct i2c_algorithm au1550_algo = { | |
1da177e4 LT |
292 | .master_xfer = au1550_xfer, |
293 | .functionality = au1550_func, | |
294 | }; | |
295 | ||
296 | /* | |
297 | * registering functions to load algorithms at runtime | |
298 | * Prior to calling us, the 50MHz clock frequency and routing | |
299 | * must have been set up for the PSC indicated by the adapter. | |
300 | */ | |
301 | int | |
302 | i2c_au1550_add_bus(struct i2c_adapter *i2c_adap) | |
303 | { | |
304 | struct i2c_au1550_data *adap = i2c_adap->algo_data; | |
305 | volatile psc_smb_t *sp; | |
306 | u32 stat; | |
307 | ||
308 | i2c_adap->algo = &au1550_algo; | |
309 | ||
310 | /* Now, set up the PSC for SMBus PIO mode. | |
311 | */ | |
312 | sp = (volatile psc_smb_t *)(adap->psc_base); | |
313 | sp->psc_ctrl = PSC_CTRL_DISABLE; | |
314 | au_sync(); | |
315 | sp->psc_sel = PSC_SEL_PS_SMBUSMODE; | |
316 | sp->psc_smbcfg = 0; | |
317 | au_sync(); | |
318 | sp->psc_ctrl = PSC_CTRL_ENABLE; | |
319 | au_sync(); | |
320 | do { | |
321 | stat = sp->psc_smbstat; | |
322 | au_sync(); | |
323 | } while ((stat & PSC_SMBSTAT_SR) == 0); | |
324 | ||
325 | sp->psc_smbcfg = (PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | | |
326 | PSC_SMBCFG_DD_DISABLE); | |
327 | ||
328 | /* Divide by 8 to get a 6.25 MHz clock. The later protocol | |
329 | * timings are based on this clock. | |
330 | */ | |
331 | sp->psc_smbcfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8); | |
332 | sp->psc_smbmsk = PSC_SMBMSK_ALLMASK; | |
333 | au_sync(); | |
334 | ||
335 | /* Set the protocol timer values. See Table 71 in the | |
336 | * Au1550 Data Book for standard timing values. | |
337 | */ | |
338 | sp->psc_smbtmr = PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \ | |
339 | PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \ | |
340 | PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \ | |
341 | PSC_SMBTMR_SET_CH(15); | |
342 | au_sync(); | |
343 | ||
344 | sp->psc_smbcfg |= PSC_SMBCFG_DE_ENABLE; | |
345 | do { | |
346 | stat = sp->psc_smbstat; | |
347 | au_sync(); | |
348 | } while ((stat & PSC_SMBSTAT_DR) == 0); | |
349 | ||
350 | return i2c_add_adapter(i2c_adap); | |
351 | } | |
352 | ||
353 | ||
354 | int | |
355 | i2c_au1550_del_bus(struct i2c_adapter *adap) | |
356 | { | |
357 | return i2c_del_adapter(adap); | |
358 | } | |
359 | ||
360 | static int | |
361 | pb1550_reg(struct i2c_client *client) | |
362 | { | |
363 | return 0; | |
364 | } | |
365 | ||
366 | static int | |
367 | pb1550_unreg(struct i2c_client *client) | |
368 | { | |
369 | return 0; | |
370 | } | |
371 | ||
372 | static struct i2c_au1550_data pb1550_i2c_info = { | |
373 | SMBUS_PSC_BASE, 200, 200 | |
374 | }; | |
375 | ||
376 | static struct i2c_adapter pb1550_board_adapter = { | |
377 | name: "pb1550 adapter", | |
378 | id: I2C_HW_AU1550_PSC, | |
379 | algo: NULL, | |
380 | algo_data: &pb1550_i2c_info, | |
381 | client_register: pb1550_reg, | |
382 | client_unregister: pb1550_unreg, | |
383 | }; | |
384 | ||
385 | /* BIG hack to support the control interface on the Wolfson WM8731 | |
386 | * audio codec on the Pb1550 board. We get an address and two data | |
387 | * bytes to write, create an i2c message, and send it across the | |
388 | * i2c transfer function. We do this here because we have access to | |
389 | * the i2c adapter structure. | |
390 | */ | |
391 | static struct i2c_msg wm_i2c_msg; /* We don't want this stuff on the stack */ | |
392 | static u8 i2cbuf[2]; | |
393 | ||
394 | int | |
395 | pb1550_wm_codec_write(u8 addr, u8 reg, u8 val) | |
396 | { | |
397 | wm_i2c_msg.addr = addr; | |
398 | wm_i2c_msg.flags = 0; | |
399 | wm_i2c_msg.buf = i2cbuf; | |
400 | wm_i2c_msg.len = 2; | |
401 | i2cbuf[0] = reg; | |
402 | i2cbuf[1] = val; | |
403 | ||
404 | return pb1550_board_adapter.algo->master_xfer(&pb1550_board_adapter, &wm_i2c_msg, 1); | |
405 | } | |
406 | ||
407 | static int __init | |
408 | i2c_au1550_init(void) | |
409 | { | |
410 | printk(KERN_INFO "Au1550 I2C: "); | |
411 | ||
412 | /* This is where we would set up a 50MHz clock source | |
413 | * and routing. On the Pb1550, the SMBus is PSC2, which | |
414 | * uses a shared clock with USB. This has been already | |
415 | * configured by Yamon as a 48MHz clock, close enough | |
416 | * for our work. | |
417 | */ | |
418 | if (i2c_au1550_add_bus(&pb1550_board_adapter) < 0) { | |
419 | printk("failed to initialize.\n"); | |
420 | return -ENODEV; | |
421 | } | |
422 | ||
423 | printk("initialized.\n"); | |
424 | return 0; | |
425 | } | |
426 | ||
427 | static void __exit | |
428 | i2c_au1550_exit(void) | |
429 | { | |
430 | i2c_au1550_del_bus(&pb1550_board_adapter); | |
431 | } | |
432 | ||
433 | MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC."); | |
434 | MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550"); | |
435 | MODULE_LICENSE("GPL"); | |
436 | ||
437 | module_init (i2c_au1550_init); | |
438 | module_exit (i2c_au1550_exit); |