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df8eb569 SB |
1 | /* |
2 | * I2C bus driver for the Cadence I2C controller. | |
3 | * | |
4 | * Copyright (C) 2009 - 2014 Xilinx, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it | |
7 | * and/or modify it under the terms of the GNU General Public | |
8 | * License as published by the Free Software Foundation; | |
9 | * either version 2 of the License, or (at your option) any | |
10 | * later version. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/i2c.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/platform_device.h> | |
63cab195 | 20 | #include <linux/of.h> |
7fa32329 | 21 | #include <linux/pm_runtime.h> |
df8eb569 SB |
22 | |
23 | /* Register offsets for the I2C device. */ | |
24 | #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */ | |
25 | #define CDNS_I2C_SR_OFFSET 0x04 /* Status Register, RO */ | |
26 | #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */ | |
27 | #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */ | |
28 | #define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */ | |
29 | #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */ | |
30 | #define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */ | |
31 | #define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */ | |
32 | #define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */ | |
33 | ||
34 | /* Control Register Bit mask definitions */ | |
35 | #define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */ | |
36 | #define CDNS_I2C_CR_ACK_EN BIT(3) | |
37 | #define CDNS_I2C_CR_NEA BIT(2) | |
38 | #define CDNS_I2C_CR_MS BIT(1) | |
39 | /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */ | |
40 | #define CDNS_I2C_CR_RW BIT(0) | |
41 | /* 1 = Auto init FIFO to zeroes */ | |
42 | #define CDNS_I2C_CR_CLR_FIFO BIT(6) | |
43 | #define CDNS_I2C_CR_DIVA_SHIFT 14 | |
44 | #define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT) | |
45 | #define CDNS_I2C_CR_DIVB_SHIFT 8 | |
46 | #define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT) | |
47 | ||
48 | /* Status Register Bit mask definitions */ | |
49 | #define CDNS_I2C_SR_BA BIT(8) | |
50 | #define CDNS_I2C_SR_RXDV BIT(5) | |
51 | ||
52 | /* | |
53 | * I2C Address Register Bit mask definitions | |
54 | * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0] | |
55 | * bits. A write access to this register always initiates a transfer if the I2C | |
56 | * is in master mode. | |
57 | */ | |
58 | #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */ | |
59 | ||
60 | /* | |
61 | * I2C Interrupt Registers Bit mask definitions | |
62 | * All the four interrupt registers (Status/Mask/Enable/Disable) have the same | |
63 | * bit definitions. | |
64 | */ | |
65 | #define CDNS_I2C_IXR_ARB_LOST BIT(9) | |
66 | #define CDNS_I2C_IXR_RX_UNF BIT(7) | |
67 | #define CDNS_I2C_IXR_TX_OVF BIT(6) | |
68 | #define CDNS_I2C_IXR_RX_OVF BIT(5) | |
69 | #define CDNS_I2C_IXR_SLV_RDY BIT(4) | |
70 | #define CDNS_I2C_IXR_TO BIT(3) | |
71 | #define CDNS_I2C_IXR_NACK BIT(2) | |
72 | #define CDNS_I2C_IXR_DATA BIT(1) | |
73 | #define CDNS_I2C_IXR_COMP BIT(0) | |
74 | ||
75 | #define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ | |
76 | CDNS_I2C_IXR_RX_UNF | \ | |
77 | CDNS_I2C_IXR_TX_OVF | \ | |
78 | CDNS_I2C_IXR_RX_OVF | \ | |
79 | CDNS_I2C_IXR_SLV_RDY | \ | |
80 | CDNS_I2C_IXR_TO | \ | |
81 | CDNS_I2C_IXR_NACK | \ | |
82 | CDNS_I2C_IXR_DATA | \ | |
83 | CDNS_I2C_IXR_COMP) | |
84 | ||
85 | #define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ | |
86 | CDNS_I2C_IXR_RX_UNF | \ | |
87 | CDNS_I2C_IXR_TX_OVF | \ | |
88 | CDNS_I2C_IXR_RX_OVF | \ | |
89 | CDNS_I2C_IXR_NACK) | |
90 | ||
91 | #define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ | |
92 | CDNS_I2C_IXR_RX_UNF | \ | |
93 | CDNS_I2C_IXR_TX_OVF | \ | |
94 | CDNS_I2C_IXR_RX_OVF | \ | |
95 | CDNS_I2C_IXR_NACK | \ | |
96 | CDNS_I2C_IXR_DATA | \ | |
97 | CDNS_I2C_IXR_COMP) | |
98 | ||
99 | #define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000) | |
7fa32329 SD |
100 | /* timeout for pm runtime autosuspend */ |
101 | #define CNDS_I2C_PM_TIMEOUT 1000 /* ms */ | |
df8eb569 SB |
102 | |
103 | #define CDNS_I2C_FIFO_DEPTH 16 | |
104 | /* FIFO depth at which the DATA interrupt occurs */ | |
105 | #define CDNS_I2C_DATA_INTR_DEPTH (CDNS_I2C_FIFO_DEPTH - 2) | |
106 | #define CDNS_I2C_MAX_TRANSFER_SIZE 255 | |
107 | /* Transfer size in multiples of data interrupt depth */ | |
108 | #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3) | |
109 | ||
110 | #define DRIVER_NAME "cdns-i2c" | |
111 | ||
112 | #define CDNS_I2C_SPEED_MAX 400000 | |
113 | #define CDNS_I2C_SPEED_DEFAULT 100000 | |
114 | ||
115 | #define CDNS_I2C_DIVA_MAX 4 | |
116 | #define CDNS_I2C_DIVB_MAX 64 | |
117 | ||
681d15a0 VM |
118 | #define CDNS_I2C_TIMEOUT_MAX 0xFF |
119 | ||
63cab195 AKV |
120 | #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0) |
121 | ||
df8eb569 SB |
122 | #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset) |
123 | #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset) | |
124 | ||
125 | /** | |
126 | * struct cdns_i2c - I2C device private data structure | |
30e31a1f SD |
127 | * |
128 | * @dev: Pointer to device structure | |
df8eb569 SB |
129 | * @membase: Base address of the I2C device |
130 | * @adap: I2C adapter instance | |
131 | * @p_msg: Message pointer | |
132 | * @err_status: Error status in Interrupt Status Register | |
133 | * @xfer_done: Transfer complete status | |
134 | * @p_send_buf: Pointer to transmit buffer | |
135 | * @p_recv_buf: Pointer to receive buffer | |
df8eb569 SB |
136 | * @send_count: Number of bytes still expected to send |
137 | * @recv_count: Number of bytes still expected to receive | |
9fae82e1 | 138 | * @curr_recv_count: Number of bytes to be received in current transfer |
df8eb569 SB |
139 | * @irq: IRQ number |
140 | * @input_clk: Input clock to I2C controller | |
141 | * @i2c_clk: Maximum I2C clock speed | |
142 | * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit | |
143 | * @clk: Pointer to struct clk | |
144 | * @clk_rate_change_nb: Notifier block for clock rate changes | |
63cab195 | 145 | * @quirks: flag for broken hold bit usage in r1p10 |
df8eb569 SB |
146 | */ |
147 | struct cdns_i2c { | |
7fa32329 | 148 | struct device *dev; |
df8eb569 SB |
149 | void __iomem *membase; |
150 | struct i2c_adapter adap; | |
151 | struct i2c_msg *p_msg; | |
152 | int err_status; | |
153 | struct completion xfer_done; | |
154 | unsigned char *p_send_buf; | |
155 | unsigned char *p_recv_buf; | |
df8eb569 SB |
156 | unsigned int send_count; |
157 | unsigned int recv_count; | |
9fae82e1 | 158 | unsigned int curr_recv_count; |
df8eb569 SB |
159 | int irq; |
160 | unsigned long input_clk; | |
161 | unsigned int i2c_clk; | |
162 | unsigned int bus_hold_flag; | |
163 | struct clk *clk; | |
164 | struct notifier_block clk_rate_change_nb; | |
63cab195 AKV |
165 | u32 quirks; |
166 | }; | |
167 | ||
168 | struct cdns_platform_data { | |
169 | u32 quirks; | |
df8eb569 SB |
170 | }; |
171 | ||
172 | #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \ | |
173 | clk_rate_change_nb) | |
174 | ||
175 | /** | |
30e31a1f | 176 | * cdns_i2c_clear_bus_hold - Clear bus hold bit |
df8eb569 SB |
177 | * @id: Pointer to driver data struct |
178 | * | |
179 | * Helper to clear the controller's bus hold bit. | |
180 | */ | |
181 | static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id) | |
182 | { | |
183 | u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); | |
184 | if (reg & CDNS_I2C_CR_HOLD) | |
185 | cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET); | |
186 | } | |
187 | ||
63cab195 AKV |
188 | static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround) |
189 | { | |
190 | return (hold_wrkaround && | |
191 | (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1)); | |
192 | } | |
193 | ||
df8eb569 SB |
194 | /** |
195 | * cdns_i2c_isr - Interrupt handler for the I2C device | |
196 | * @irq: irq number for the I2C device | |
197 | * @ptr: void pointer to cdns_i2c structure | |
198 | * | |
199 | * This function handles the data interrupt, transfer complete interrupt and | |
200 | * the error interrupts of the I2C device. | |
201 | * | |
202 | * Return: IRQ_HANDLED always | |
203 | */ | |
204 | static irqreturn_t cdns_i2c_isr(int irq, void *ptr) | |
205 | { | |
9fae82e1 HK |
206 | unsigned int isr_status, avail_bytes, updatetx; |
207 | unsigned int bytes_to_send; | |
63cab195 | 208 | bool hold_quirk; |
df8eb569 SB |
209 | struct cdns_i2c *id = ptr; |
210 | /* Signal completion only after everything is updated */ | |
211 | int done_flag = 0; | |
212 | irqreturn_t status = IRQ_NONE; | |
213 | ||
214 | isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); | |
9fae82e1 | 215 | cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); |
df8eb569 SB |
216 | |
217 | /* Handling nack and arbitration lost interrupt */ | |
218 | if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) { | |
219 | done_flag = 1; | |
220 | status = IRQ_HANDLED; | |
221 | } | |
222 | ||
9fae82e1 HK |
223 | /* |
224 | * Check if transfer size register needs to be updated again for a | |
225 | * large data receive operation. | |
226 | */ | |
227 | updatetx = 0; | |
228 | if (id->recv_count > id->curr_recv_count) | |
229 | updatetx = 1; | |
230 | ||
63cab195 AKV |
231 | hold_quirk = (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx; |
232 | ||
9fae82e1 HK |
233 | /* When receiving, handle data interrupt and completion interrupt */ |
234 | if (id->p_recv_buf && | |
235 | ((isr_status & CDNS_I2C_IXR_COMP) || | |
236 | (isr_status & CDNS_I2C_IXR_DATA))) { | |
237 | /* Read data if receive data valid is set */ | |
238 | while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & | |
239 | CDNS_I2C_SR_RXDV) { | |
240 | /* | |
241 | * Clear hold bit that was set for FIFO control if | |
242 | * RX data left is less than FIFO depth, unless | |
243 | * repeated start is selected. | |
244 | */ | |
245 | if ((id->recv_count < CDNS_I2C_FIFO_DEPTH) && | |
246 | !id->bus_hold_flag) | |
247 | cdns_i2c_clear_bus_hold(id); | |
df8eb569 | 248 | |
df8eb569 SB |
249 | *(id->p_recv_buf)++ = |
250 | cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); | |
9fae82e1 HK |
251 | id->recv_count--; |
252 | id->curr_recv_count--; | |
df8eb569 | 253 | |
63cab195 | 254 | if (cdns_is_holdquirk(id, hold_quirk)) |
9fae82e1 HK |
255 | break; |
256 | } | |
df8eb569 | 257 | |
9fae82e1 HK |
258 | /* |
259 | * The controller sends NACK to the slave when transfer size | |
260 | * register reaches zero without considering the HOLD bit. | |
261 | * This workaround is implemented for large data transfers to | |
262 | * maintain transfer size non-zero while performing a large | |
263 | * receive operation. | |
264 | */ | |
63cab195 | 265 | if (cdns_is_holdquirk(id, hold_quirk)) { |
9fae82e1 HK |
266 | /* wait while fifo is full */ |
267 | while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) != | |
268 | (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH)) | |
269 | ; | |
df8eb569 | 270 | |
df8eb569 | 271 | /* |
9fae82e1 HK |
272 | * Check number of bytes to be received against maximum |
273 | * transfer size and update register accordingly. | |
df8eb569 | 274 | */ |
9fae82e1 HK |
275 | if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) > |
276 | CDNS_I2C_TRANSFER_SIZE) { | |
277 | cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, | |
278 | CDNS_I2C_XFER_SIZE_OFFSET); | |
279 | id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE + | |
280 | CDNS_I2C_FIFO_DEPTH; | |
df8eb569 | 281 | } else { |
9fae82e1 HK |
282 | cdns_i2c_writereg(id->recv_count - |
283 | CDNS_I2C_FIFO_DEPTH, | |
284 | CDNS_I2C_XFER_SIZE_OFFSET); | |
285 | id->curr_recv_count = id->recv_count; | |
df8eb569 | 286 | } |
63cab195 AKV |
287 | } else if (id->recv_count && !hold_quirk && |
288 | !id->curr_recv_count) { | |
289 | ||
290 | /* Set the slave address in address register*/ | |
291 | cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, | |
292 | CDNS_I2C_ADDR_OFFSET); | |
293 | ||
294 | if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) { | |
295 | cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, | |
296 | CDNS_I2C_XFER_SIZE_OFFSET); | |
297 | id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE; | |
298 | } else { | |
299 | cdns_i2c_writereg(id->recv_count, | |
300 | CDNS_I2C_XFER_SIZE_OFFSET); | |
301 | id->curr_recv_count = id->recv_count; | |
302 | } | |
9fae82e1 HK |
303 | } |
304 | ||
305 | /* Clear hold (if not repeated start) and signal completion */ | |
306 | if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) { | |
df8eb569 SB |
307 | if (!id->bus_hold_flag) |
308 | cdns_i2c_clear_bus_hold(id); | |
9fae82e1 HK |
309 | done_flag = 1; |
310 | } | |
311 | ||
312 | status = IRQ_HANDLED; | |
313 | } | |
314 | ||
315 | /* When sending, handle transfer complete interrupt */ | |
316 | if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) { | |
317 | /* | |
318 | * If there is more data to be sent, calculate the | |
319 | * space available in FIFO and fill with that many bytes. | |
320 | */ | |
321 | if (id->send_count) { | |
322 | avail_bytes = CDNS_I2C_FIFO_DEPTH - | |
323 | cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); | |
324 | if (id->send_count > avail_bytes) | |
325 | bytes_to_send = avail_bytes; | |
326 | else | |
327 | bytes_to_send = id->send_count; | |
328 | ||
329 | while (bytes_to_send--) { | |
330 | cdns_i2c_writereg( | |
331 | (*(id->p_send_buf)++), | |
332 | CDNS_I2C_DATA_OFFSET); | |
333 | id->send_count--; | |
334 | } | |
335 | } else { | |
df8eb569 | 336 | /* |
9fae82e1 HK |
337 | * Signal the completion of transaction and |
338 | * clear the hold bus bit if there are no | |
339 | * further messages to be processed. | |
df8eb569 | 340 | */ |
df8eb569 SB |
341 | done_flag = 1; |
342 | } | |
9fae82e1 HK |
343 | if (!id->send_count && !id->bus_hold_flag) |
344 | cdns_i2c_clear_bus_hold(id); | |
df8eb569 SB |
345 | |
346 | status = IRQ_HANDLED; | |
347 | } | |
348 | ||
349 | /* Update the status for errors */ | |
350 | id->err_status = isr_status & CDNS_I2C_IXR_ERR_INTR_MASK; | |
351 | if (id->err_status) | |
352 | status = IRQ_HANDLED; | |
353 | ||
df8eb569 SB |
354 | if (done_flag) |
355 | complete(&id->xfer_done); | |
356 | ||
357 | return status; | |
358 | } | |
359 | ||
360 | /** | |
361 | * cdns_i2c_mrecv - Prepare and start a master receive operation | |
362 | * @id: pointer to the i2c device structure | |
363 | */ | |
364 | static void cdns_i2c_mrecv(struct cdns_i2c *id) | |
365 | { | |
366 | unsigned int ctrl_reg; | |
367 | unsigned int isr_status; | |
368 | ||
369 | id->p_recv_buf = id->p_msg->buf; | |
370 | id->recv_count = id->p_msg->len; | |
371 | ||
372 | /* Put the controller in master receive mode and clear the FIFO */ | |
373 | ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); | |
374 | ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO; | |
375 | ||
376 | if (id->p_msg->flags & I2C_M_RECV_LEN) | |
377 | id->recv_count = I2C_SMBUS_BLOCK_MAX + 1; | |
378 | ||
9fae82e1 HK |
379 | id->curr_recv_count = id->recv_count; |
380 | ||
df8eb569 SB |
381 | /* |
382 | * Check for the message size against FIFO depth and set the | |
383 | * 'hold bus' bit if it is greater than FIFO depth. | |
384 | */ | |
385 | if (id->recv_count > CDNS_I2C_FIFO_DEPTH) | |
386 | ctrl_reg |= CDNS_I2C_CR_HOLD; | |
387 | ||
388 | cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); | |
389 | ||
390 | /* Clear the interrupts in interrupt status register */ | |
391 | isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); | |
392 | cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); | |
393 | ||
394 | /* | |
395 | * The no. of bytes to receive is checked against the limit of | |
396 | * max transfer size. Set transfer size register with no of bytes | |
397 | * receive if it is less than transfer size and transfer size if | |
398 | * it is more. Enable the interrupts. | |
399 | */ | |
9fae82e1 | 400 | if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) { |
df8eb569 SB |
401 | cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, |
402 | CDNS_I2C_XFER_SIZE_OFFSET); | |
9fae82e1 HK |
403 | id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE; |
404 | } else { | |
df8eb569 | 405 | cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET); |
9fae82e1 HK |
406 | } |
407 | ||
df8eb569 SB |
408 | /* Clear the bus hold flag if bytes to receive is less than FIFO size */ |
409 | if (!id->bus_hold_flag && | |
410 | ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) && | |
411 | (id->recv_count <= CDNS_I2C_FIFO_DEPTH)) | |
412 | cdns_i2c_clear_bus_hold(id); | |
413 | /* Set the slave address in address register - triggers operation */ | |
414 | cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, | |
415 | CDNS_I2C_ADDR_OFFSET); | |
416 | cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); | |
417 | } | |
418 | ||
419 | /** | |
420 | * cdns_i2c_msend - Prepare and start a master send operation | |
421 | * @id: pointer to the i2c device | |
422 | */ | |
423 | static void cdns_i2c_msend(struct cdns_i2c *id) | |
424 | { | |
425 | unsigned int avail_bytes; | |
426 | unsigned int bytes_to_send; | |
427 | unsigned int ctrl_reg; | |
428 | unsigned int isr_status; | |
429 | ||
430 | id->p_recv_buf = NULL; | |
431 | id->p_send_buf = id->p_msg->buf; | |
432 | id->send_count = id->p_msg->len; | |
433 | ||
434 | /* Set the controller in Master transmit mode and clear the FIFO. */ | |
435 | ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); | |
436 | ctrl_reg &= ~CDNS_I2C_CR_RW; | |
437 | ctrl_reg |= CDNS_I2C_CR_CLR_FIFO; | |
438 | ||
439 | /* | |
440 | * Check for the message size against FIFO depth and set the | |
441 | * 'hold bus' bit if it is greater than FIFO depth. | |
442 | */ | |
443 | if (id->send_count > CDNS_I2C_FIFO_DEPTH) | |
444 | ctrl_reg |= CDNS_I2C_CR_HOLD; | |
445 | cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); | |
446 | ||
447 | /* Clear the interrupts in interrupt status register. */ | |
448 | isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); | |
449 | cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); | |
450 | ||
451 | /* | |
452 | * Calculate the space available in FIFO. Check the message length | |
453 | * against the space available, and fill the FIFO accordingly. | |
454 | * Enable the interrupts. | |
455 | */ | |
456 | avail_bytes = CDNS_I2C_FIFO_DEPTH - | |
457 | cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); | |
458 | ||
459 | if (id->send_count > avail_bytes) | |
460 | bytes_to_send = avail_bytes; | |
461 | else | |
462 | bytes_to_send = id->send_count; | |
463 | ||
464 | while (bytes_to_send--) { | |
465 | cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET); | |
466 | id->send_count--; | |
467 | } | |
468 | ||
469 | /* | |
470 | * Clear the bus hold flag if there is no more data | |
471 | * and if it is the last message. | |
472 | */ | |
473 | if (!id->bus_hold_flag && !id->send_count) | |
474 | cdns_i2c_clear_bus_hold(id); | |
475 | /* Set the slave address in address register - triggers operation. */ | |
476 | cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, | |
477 | CDNS_I2C_ADDR_OFFSET); | |
478 | ||
479 | cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); | |
480 | } | |
481 | ||
482 | /** | |
483 | * cdns_i2c_master_reset - Reset the interface | |
484 | * @adap: pointer to the i2c adapter driver instance | |
485 | * | |
486 | * This function cleanup the fifos, clear the hold bit and status | |
487 | * and disable the interrupts. | |
488 | */ | |
489 | static void cdns_i2c_master_reset(struct i2c_adapter *adap) | |
490 | { | |
491 | struct cdns_i2c *id = adap->algo_data; | |
492 | u32 regval; | |
493 | ||
494 | /* Disable the interrupts */ | |
495 | cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET); | |
496 | /* Clear the hold bit and fifos */ | |
497 | regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); | |
498 | regval &= ~CDNS_I2C_CR_HOLD; | |
499 | regval |= CDNS_I2C_CR_CLR_FIFO; | |
500 | cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET); | |
501 | /* Update the transfercount register to zero */ | |
502 | cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET); | |
503 | /* Clear the interupt status register */ | |
504 | regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); | |
505 | cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET); | |
506 | /* Clear the status register */ | |
507 | regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET); | |
508 | cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET); | |
509 | } | |
510 | ||
511 | static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg, | |
512 | struct i2c_adapter *adap) | |
513 | { | |
e2efb897 | 514 | unsigned long time_left; |
df8eb569 SB |
515 | u32 reg; |
516 | ||
517 | id->p_msg = msg; | |
518 | id->err_status = 0; | |
519 | reinit_completion(&id->xfer_done); | |
520 | ||
521 | /* Check for the TEN Bit mode on each msg */ | |
522 | reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); | |
523 | if (msg->flags & I2C_M_TEN) { | |
524 | if (reg & CDNS_I2C_CR_NEA) | |
525 | cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA, | |
526 | CDNS_I2C_CR_OFFSET); | |
527 | } else { | |
528 | if (!(reg & CDNS_I2C_CR_NEA)) | |
529 | cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA, | |
530 | CDNS_I2C_CR_OFFSET); | |
531 | } | |
532 | ||
533 | /* Check for the R/W flag on each msg */ | |
534 | if (msg->flags & I2C_M_RD) | |
535 | cdns_i2c_mrecv(id); | |
536 | else | |
537 | cdns_i2c_msend(id); | |
538 | ||
539 | /* Wait for the signal of completion */ | |
e2efb897 NMG |
540 | time_left = wait_for_completion_timeout(&id->xfer_done, adap->timeout); |
541 | if (time_left == 0) { | |
df8eb569 SB |
542 | cdns_i2c_master_reset(adap); |
543 | dev_err(id->adap.dev.parent, | |
544 | "timeout waiting on completion\n"); | |
545 | return -ETIMEDOUT; | |
546 | } | |
547 | ||
548 | cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, | |
549 | CDNS_I2C_IDR_OFFSET); | |
550 | ||
551 | /* If it is bus arbitration error, try again */ | |
552 | if (id->err_status & CDNS_I2C_IXR_ARB_LOST) | |
553 | return -EAGAIN; | |
554 | ||
555 | return 0; | |
556 | } | |
557 | ||
558 | /** | |
559 | * cdns_i2c_master_xfer - The main i2c transfer function | |
560 | * @adap: pointer to the i2c adapter driver instance | |
561 | * @msgs: pointer to the i2c message structure | |
562 | * @num: the number of messages to transfer | |
563 | * | |
564 | * Initiates the send/recv activity based on the transfer message received. | |
565 | * | |
566 | * Return: number of msgs processed on success, negative error otherwise | |
567 | */ | |
568 | static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, | |
569 | int num) | |
570 | { | |
571 | int ret, count; | |
572 | u32 reg; | |
573 | struct cdns_i2c *id = adap->algo_data; | |
63cab195 | 574 | bool hold_quirk; |
df8eb569 | 575 | |
7fa32329 SD |
576 | ret = pm_runtime_get_sync(id->dev); |
577 | if (ret < 0) | |
578 | return ret; | |
df8eb569 | 579 | /* Check if the bus is free */ |
7fa32329 SD |
580 | if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA) { |
581 | ret = -EAGAIN; | |
582 | goto out; | |
583 | } | |
df8eb569 | 584 | |
63cab195 | 585 | hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT); |
df8eb569 SB |
586 | /* |
587 | * Set the flag to one when multiple messages are to be | |
588 | * processed with a repeated start. | |
589 | */ | |
590 | if (num > 1) { | |
8a86c3ae HK |
591 | /* |
592 | * This controller does not give completion interrupt after a | |
593 | * master receive message if HOLD bit is set (repeated start), | |
594 | * resulting in SW timeout. Hence, if a receive message is | |
595 | * followed by any other message, an error is returned | |
596 | * indicating that this sequence is not supported. | |
597 | */ | |
63cab195 | 598 | for (count = 0; (count < num - 1 && hold_quirk); count++) { |
8a86c3ae HK |
599 | if (msgs[count].flags & I2C_M_RD) { |
600 | dev_warn(adap->dev.parent, | |
601 | "Can't do repeated start after a receive message\n"); | |
7fa32329 SD |
602 | ret = -EOPNOTSUPP; |
603 | goto out; | |
8a86c3ae HK |
604 | } |
605 | } | |
df8eb569 SB |
606 | id->bus_hold_flag = 1; |
607 | reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); | |
608 | reg |= CDNS_I2C_CR_HOLD; | |
609 | cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET); | |
610 | } else { | |
611 | id->bus_hold_flag = 0; | |
612 | } | |
613 | ||
614 | /* Process the msg one by one */ | |
615 | for (count = 0; count < num; count++, msgs++) { | |
616 | if (count == (num - 1)) | |
617 | id->bus_hold_flag = 0; | |
618 | ||
619 | ret = cdns_i2c_process_msg(id, msgs, adap); | |
620 | if (ret) | |
7fa32329 | 621 | goto out; |
df8eb569 SB |
622 | |
623 | /* Report the other error interrupts to application */ | |
624 | if (id->err_status) { | |
625 | cdns_i2c_master_reset(adap); | |
626 | ||
7fa32329 SD |
627 | if (id->err_status & CDNS_I2C_IXR_NACK) { |
628 | ret = -ENXIO; | |
629 | goto out; | |
630 | } | |
631 | ret = -EIO; | |
632 | goto out; | |
df8eb569 SB |
633 | } |
634 | } | |
635 | ||
7fa32329 SD |
636 | ret = num; |
637 | out: | |
638 | pm_runtime_mark_last_busy(id->dev); | |
639 | pm_runtime_put_autosuspend(id->dev); | |
640 | return ret; | |
df8eb569 SB |
641 | } |
642 | ||
643 | /** | |
644 | * cdns_i2c_func - Returns the supported features of the I2C driver | |
645 | * @adap: pointer to the i2c adapter structure | |
646 | * | |
647 | * Return: 32 bit value, each bit corresponding to a feature | |
648 | */ | |
649 | static u32 cdns_i2c_func(struct i2c_adapter *adap) | |
650 | { | |
651 | return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | | |
652 | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | | |
653 | I2C_FUNC_SMBUS_BLOCK_DATA; | |
654 | } | |
655 | ||
656 | static const struct i2c_algorithm cdns_i2c_algo = { | |
657 | .master_xfer = cdns_i2c_master_xfer, | |
658 | .functionality = cdns_i2c_func, | |
659 | }; | |
660 | ||
661 | /** | |
662 | * cdns_i2c_calc_divs - Calculate clock dividers | |
663 | * @f: I2C clock frequency | |
664 | * @input_clk: Input clock frequency | |
665 | * @a: First divider (return value) | |
666 | * @b: Second divider (return value) | |
667 | * | |
668 | * f is used as input and output variable. As input it is used as target I2C | |
669 | * frequency. On function exit f holds the actually resulting I2C frequency. | |
670 | * | |
671 | * Return: 0 on success, negative errno otherwise. | |
672 | */ | |
673 | static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, | |
674 | unsigned int *a, unsigned int *b) | |
675 | { | |
676 | unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp; | |
677 | unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0; | |
678 | unsigned int last_error, current_error; | |
679 | ||
680 | /* calculate (divisor_a+1) x (divisor_b+1) */ | |
681 | temp = input_clk / (22 * fscl); | |
682 | ||
683 | /* | |
684 | * If the calculated value is negative or 0, the fscl input is out of | |
685 | * range. Return error. | |
686 | */ | |
687 | if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX))) | |
688 | return -EINVAL; | |
689 | ||
690 | last_error = -1; | |
691 | for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) { | |
692 | div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); | |
693 | ||
694 | if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX)) | |
695 | continue; | |
696 | div_b--; | |
697 | ||
698 | actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); | |
699 | ||
700 | if (actual_fscl > fscl) | |
701 | continue; | |
702 | ||
703 | current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) : | |
704 | (fscl - actual_fscl)); | |
705 | ||
706 | if (last_error > current_error) { | |
707 | calc_div_a = div_a; | |
708 | calc_div_b = div_b; | |
709 | best_fscl = actual_fscl; | |
710 | last_error = current_error; | |
711 | } | |
712 | } | |
713 | ||
714 | *a = calc_div_a; | |
715 | *b = calc_div_b; | |
716 | *f = best_fscl; | |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
721 | /** | |
722 | * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device | |
723 | * @clk_in: I2C clock input frequency in Hz | |
724 | * @id: Pointer to the I2C device structure | |
725 | * | |
726 | * The device must be idle rather than busy transferring data before setting | |
727 | * these device options. | |
728 | * The data rate is set by values in the control register. | |
729 | * The formula for determining the correct register values is | |
730 | * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1)) | |
731 | * See the hardware data sheet for a full explanation of setting the serial | |
732 | * clock rate. The clock can not be faster than the input clock divide by 22. | |
733 | * The two most common clock rates are 100KHz and 400KHz. | |
734 | * | |
735 | * Return: 0 on success, negative error otherwise | |
736 | */ | |
737 | static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id) | |
738 | { | |
739 | unsigned int div_a, div_b; | |
740 | unsigned int ctrl_reg; | |
741 | int ret = 0; | |
742 | unsigned long fscl = id->i2c_clk; | |
743 | ||
744 | ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b); | |
745 | if (ret) | |
746 | return ret; | |
747 | ||
748 | ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); | |
749 | ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK); | |
750 | ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) | | |
751 | (div_b << CDNS_I2C_CR_DIVB_SHIFT)); | |
752 | cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); | |
753 | ||
754 | return 0; | |
755 | } | |
756 | ||
757 | /** | |
758 | * cdns_i2c_clk_notifier_cb - Clock rate change callback | |
759 | * @nb: Pointer to notifier block | |
760 | * @event: Notification reason | |
761 | * @data: Pointer to notification data object | |
762 | * | |
763 | * This function is called when the cdns_i2c input clock frequency changes. | |
764 | * The callback checks whether a valid bus frequency can be generated after the | |
765 | * change. If so, the change is acknowledged, otherwise the change is aborted. | |
766 | * New dividers are written to the HW in the pre- or post change notification | |
767 | * depending on the scaling direction. | |
768 | * | |
769 | * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK | |
e0603c8d | 770 | * to acknowledge the change, NOTIFY_DONE if the notification is |
df8eb569 SB |
771 | * considered irrelevant. |
772 | */ | |
773 | static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long | |
774 | event, void *data) | |
775 | { | |
776 | struct clk_notifier_data *ndata = data; | |
777 | struct cdns_i2c *id = to_cdns_i2c(nb); | |
778 | ||
948c58a0 | 779 | if (pm_runtime_suspended(id->dev)) |
df8eb569 SB |
780 | return NOTIFY_OK; |
781 | ||
782 | switch (event) { | |
783 | case PRE_RATE_CHANGE: | |
784 | { | |
785 | unsigned long input_clk = ndata->new_rate; | |
786 | unsigned long fscl = id->i2c_clk; | |
787 | unsigned int div_a, div_b; | |
788 | int ret; | |
789 | ||
790 | ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b); | |
791 | if (ret) { | |
792 | dev_warn(id->adap.dev.parent, | |
793 | "clock rate change rejected\n"); | |
794 | return NOTIFY_STOP; | |
795 | } | |
796 | ||
797 | /* scale up */ | |
798 | if (ndata->new_rate > ndata->old_rate) | |
799 | cdns_i2c_setclk(ndata->new_rate, id); | |
800 | ||
801 | return NOTIFY_OK; | |
802 | } | |
803 | case POST_RATE_CHANGE: | |
804 | id->input_clk = ndata->new_rate; | |
805 | /* scale down */ | |
806 | if (ndata->new_rate < ndata->old_rate) | |
807 | cdns_i2c_setclk(ndata->new_rate, id); | |
808 | return NOTIFY_OK; | |
809 | case ABORT_RATE_CHANGE: | |
810 | /* scale up */ | |
811 | if (ndata->new_rate > ndata->old_rate) | |
812 | cdns_i2c_setclk(ndata->old_rate, id); | |
813 | return NOTIFY_OK; | |
814 | default: | |
815 | return NOTIFY_DONE; | |
816 | } | |
817 | } | |
818 | ||
819 | /** | |
30e31a1f SD |
820 | * cdns_i2c_runtime_suspend - Runtime suspend method for the driver |
821 | * @dev: Address of the platform_device structure | |
df8eb569 SB |
822 | * |
823 | * Put the driver into low power mode. | |
824 | * | |
825 | * Return: 0 always | |
826 | */ | |
7fa32329 | 827 | static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev) |
df8eb569 | 828 | { |
7fa32329 | 829 | struct platform_device *pdev = to_platform_device(dev); |
df8eb569 SB |
830 | struct cdns_i2c *xi2c = platform_get_drvdata(pdev); |
831 | ||
832 | clk_disable(xi2c->clk); | |
df8eb569 SB |
833 | |
834 | return 0; | |
835 | } | |
836 | ||
837 | /** | |
30e31a1f SD |
838 | * cdns_i2c_runtime_resume - Runtime resume |
839 | * @dev: Address of the platform_device structure | |
df8eb569 | 840 | * |
30e31a1f | 841 | * Runtime resume callback. |
df8eb569 SB |
842 | * |
843 | * Return: 0 on success and error value on error | |
844 | */ | |
7fa32329 | 845 | static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev) |
df8eb569 | 846 | { |
7fa32329 | 847 | struct platform_device *pdev = to_platform_device(dev); |
df8eb569 SB |
848 | struct cdns_i2c *xi2c = platform_get_drvdata(pdev); |
849 | int ret; | |
850 | ||
851 | ret = clk_enable(xi2c->clk); | |
852 | if (ret) { | |
7fa32329 | 853 | dev_err(dev, "Cannot enable clock.\n"); |
df8eb569 SB |
854 | return ret; |
855 | } | |
856 | ||
df8eb569 SB |
857 | return 0; |
858 | } | |
859 | ||
7fa32329 SD |
860 | static const struct dev_pm_ops cdns_i2c_dev_pm_ops = { |
861 | SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend, | |
862 | cdns_i2c_runtime_resume, NULL) | |
863 | }; | |
df8eb569 | 864 | |
63cab195 AKV |
865 | static const struct cdns_platform_data r1p10_i2c_def = { |
866 | .quirks = CDNS_I2C_BROKEN_HOLD_BIT, | |
867 | }; | |
868 | ||
869 | static const struct of_device_id cdns_i2c_of_match[] = { | |
870 | { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def }, | |
871 | { .compatible = "cdns,i2c-r1p14",}, | |
872 | { /* end of table */ } | |
873 | }; | |
874 | MODULE_DEVICE_TABLE(of, cdns_i2c_of_match); | |
875 | ||
df8eb569 SB |
876 | /** |
877 | * cdns_i2c_probe - Platform registration call | |
878 | * @pdev: Handle to the platform device structure | |
879 | * | |
880 | * This function does all the memory allocation and registration for the i2c | |
881 | * device. User can modify the address mode to 10 bit address mode using the | |
882 | * ioctl call with option I2C_TENBIT. | |
883 | * | |
884 | * Return: 0 on success, negative error otherwise | |
885 | */ | |
886 | static int cdns_i2c_probe(struct platform_device *pdev) | |
887 | { | |
888 | struct resource *r_mem; | |
889 | struct cdns_i2c *id; | |
890 | int ret; | |
63cab195 | 891 | const struct of_device_id *match; |
df8eb569 SB |
892 | |
893 | id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL); | |
894 | if (!id) | |
895 | return -ENOMEM; | |
896 | ||
7fa32329 | 897 | id->dev = &pdev->dev; |
df8eb569 SB |
898 | platform_set_drvdata(pdev, id); |
899 | ||
63cab195 AKV |
900 | match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node); |
901 | if (match && match->data) { | |
902 | const struct cdns_platform_data *data = match->data; | |
903 | id->quirks = data->quirks; | |
904 | } | |
905 | ||
df8eb569 SB |
906 | r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
907 | id->membase = devm_ioremap_resource(&pdev->dev, r_mem); | |
908 | if (IS_ERR(id->membase)) | |
909 | return PTR_ERR(id->membase); | |
910 | ||
911 | id->irq = platform_get_irq(pdev, 0); | |
912 | ||
a1f64317 | 913 | id->adap.owner = THIS_MODULE; |
df8eb569 SB |
914 | id->adap.dev.of_node = pdev->dev.of_node; |
915 | id->adap.algo = &cdns_i2c_algo; | |
916 | id->adap.timeout = CDNS_I2C_TIMEOUT; | |
917 | id->adap.retries = 3; /* Default retry value. */ | |
918 | id->adap.algo_data = id; | |
919 | id->adap.dev.parent = &pdev->dev; | |
920 | init_completion(&id->xfer_done); | |
921 | snprintf(id->adap.name, sizeof(id->adap.name), | |
922 | "Cadence I2C at %08lx", (unsigned long)r_mem->start); | |
923 | ||
924 | id->clk = devm_clk_get(&pdev->dev, NULL); | |
925 | if (IS_ERR(id->clk)) { | |
926 | dev_err(&pdev->dev, "input clock not found.\n"); | |
927 | return PTR_ERR(id->clk); | |
928 | } | |
929 | ret = clk_prepare_enable(id->clk); | |
7fa32329 | 930 | if (ret) |
df8eb569 | 931 | dev_err(&pdev->dev, "Unable to enable clock.\n"); |
7fa32329 SD |
932 | |
933 | pm_runtime_enable(id->dev); | |
934 | pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT); | |
935 | pm_runtime_use_autosuspend(id->dev); | |
936 | pm_runtime_set_active(id->dev); | |
937 | ||
df8eb569 SB |
938 | id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb; |
939 | if (clk_notifier_register(id->clk, &id->clk_rate_change_nb)) | |
940 | dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); | |
941 | id->input_clk = clk_get_rate(id->clk); | |
942 | ||
943 | ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", | |
944 | &id->i2c_clk); | |
945 | if (ret || (id->i2c_clk > CDNS_I2C_SPEED_MAX)) | |
946 | id->i2c_clk = CDNS_I2C_SPEED_DEFAULT; | |
947 | ||
948 | cdns_i2c_writereg(CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS, | |
949 | CDNS_I2C_CR_OFFSET); | |
950 | ||
951 | ret = cdns_i2c_setclk(id->input_clk, id); | |
952 | if (ret) { | |
953 | dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk); | |
954 | ret = -EINVAL; | |
955 | goto err_clk_dis; | |
956 | } | |
957 | ||
958 | ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0, | |
959 | DRIVER_NAME, id); | |
960 | if (ret) { | |
961 | dev_err(&pdev->dev, "cannot get irq %d\n", id->irq); | |
962 | goto err_clk_dis; | |
963 | } | |
964 | ||
965 | ret = i2c_add_adapter(&id->adap); | |
966 | if (ret < 0) { | |
967 | dev_err(&pdev->dev, "reg adap failed: %d\n", ret); | |
968 | goto err_clk_dis; | |
969 | } | |
970 | ||
681d15a0 VM |
971 | /* |
972 | * Cadence I2C controller has a bug wherein it generates | |
973 | * invalid read transaction after HW timeout in master receiver mode. | |
974 | * HW timeout is not used by this driver and the interrupt is disabled. | |
975 | * But the feature itself cannot be disabled. Hence maximum value | |
976 | * is written to this register to reduce the chances of error. | |
977 | */ | |
978 | cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET); | |
979 | ||
df8eb569 SB |
980 | dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n", |
981 | id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq); | |
982 | ||
983 | return 0; | |
984 | ||
985 | err_clk_dis: | |
986 | clk_disable_unprepare(id->clk); | |
7fa32329 SD |
987 | pm_runtime_set_suspended(&pdev->dev); |
988 | pm_runtime_disable(&pdev->dev); | |
df8eb569 SB |
989 | return ret; |
990 | } | |
991 | ||
992 | /** | |
993 | * cdns_i2c_remove - Unregister the device after releasing the resources | |
994 | * @pdev: Handle to the platform device structure | |
995 | * | |
996 | * This function frees all the resources allocated to the device. | |
997 | * | |
998 | * Return: 0 always | |
999 | */ | |
1000 | static int cdns_i2c_remove(struct platform_device *pdev) | |
1001 | { | |
1002 | struct cdns_i2c *id = platform_get_drvdata(pdev); | |
1003 | ||
1004 | i2c_del_adapter(&id->adap); | |
1005 | clk_notifier_unregister(id->clk, &id->clk_rate_change_nb); | |
1006 | clk_disable_unprepare(id->clk); | |
7fa32329 | 1007 | pm_runtime_disable(&pdev->dev); |
df8eb569 SB |
1008 | |
1009 | return 0; | |
1010 | } | |
1011 | ||
df8eb569 SB |
1012 | static struct platform_driver cdns_i2c_drv = { |
1013 | .driver = { | |
1014 | .name = DRIVER_NAME, | |
df8eb569 SB |
1015 | .of_match_table = cdns_i2c_of_match, |
1016 | .pm = &cdns_i2c_dev_pm_ops, | |
1017 | }, | |
1018 | .probe = cdns_i2c_probe, | |
1019 | .remove = cdns_i2c_remove, | |
1020 | }; | |
1021 | ||
1022 | module_platform_driver(cdns_i2c_drv); | |
1023 | ||
1024 | MODULE_AUTHOR("Xilinx Inc."); | |
1025 | MODULE_DESCRIPTION("Cadence I2C bus driver"); | |
1026 | MODULE_LICENSE("GPL"); |