Commit | Line | Data |
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1ab52cf9 | 1 | /* |
a0e06ea6 | 2 | * Synopsys DesignWare I2C adapter driver (master only). |
1ab52cf9 BS |
3 | * |
4 | * Based on the TI DAVINCI I2C adapter driver. | |
5 | * | |
6 | * Copyright (C) 2006 Texas Instruments. | |
7 | * Copyright (C) 2007 MontaVista Software Inc. | |
8 | * Copyright (C) 2009 Provigent Ltd. | |
9 | * | |
10 | * ---------------------------------------------------------------------------- | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * ---------------------------------------------------------------------------- | |
26 | * | |
27 | */ | |
e68bb91b | 28 | #include <linux/export.h> |
1ab52cf9 BS |
29 | #include <linux/clk.h> |
30 | #include <linux/errno.h> | |
1ab52cf9 | 31 | #include <linux/err.h> |
2373f6b9 | 32 | #include <linux/i2c.h> |
1ab52cf9 | 33 | #include <linux/interrupt.h> |
1ab52cf9 | 34 | #include <linux/io.h> |
18dbdda8 | 35 | #include <linux/pm_runtime.h> |
2373f6b9 DB |
36 | #include <linux/delay.h> |
37 | #include "i2c-designware-core.h" | |
ce6eb574 | 38 | |
f3fa9f3d DB |
39 | /* |
40 | * Registers offset | |
41 | */ | |
42 | #define DW_IC_CON 0x0 | |
43 | #define DW_IC_TAR 0x4 | |
44 | #define DW_IC_DATA_CMD 0x10 | |
45 | #define DW_IC_SS_SCL_HCNT 0x14 | |
46 | #define DW_IC_SS_SCL_LCNT 0x18 | |
47 | #define DW_IC_FS_SCL_HCNT 0x1c | |
48 | #define DW_IC_FS_SCL_LCNT 0x20 | |
49 | #define DW_IC_INTR_STAT 0x2c | |
50 | #define DW_IC_INTR_MASK 0x30 | |
51 | #define DW_IC_RAW_INTR_STAT 0x34 | |
52 | #define DW_IC_RX_TL 0x38 | |
53 | #define DW_IC_TX_TL 0x3c | |
54 | #define DW_IC_CLR_INTR 0x40 | |
55 | #define DW_IC_CLR_RX_UNDER 0x44 | |
56 | #define DW_IC_CLR_RX_OVER 0x48 | |
57 | #define DW_IC_CLR_TX_OVER 0x4c | |
58 | #define DW_IC_CLR_RD_REQ 0x50 | |
59 | #define DW_IC_CLR_TX_ABRT 0x54 | |
60 | #define DW_IC_CLR_RX_DONE 0x58 | |
61 | #define DW_IC_CLR_ACTIVITY 0x5c | |
62 | #define DW_IC_CLR_STOP_DET 0x60 | |
63 | #define DW_IC_CLR_START_DET 0x64 | |
64 | #define DW_IC_CLR_GEN_CALL 0x68 | |
65 | #define DW_IC_ENABLE 0x6c | |
66 | #define DW_IC_STATUS 0x70 | |
67 | #define DW_IC_TXFLR 0x74 | |
68 | #define DW_IC_RXFLR 0x78 | |
69 | #define DW_IC_TX_ABRT_SOURCE 0x80 | |
70 | #define DW_IC_COMP_PARAM_1 0xf4 | |
71 | #define DW_IC_COMP_TYPE 0xfc | |
72 | #define DW_IC_COMP_TYPE_VALUE 0x44570140 | |
73 | ||
74 | #define DW_IC_INTR_RX_UNDER 0x001 | |
75 | #define DW_IC_INTR_RX_OVER 0x002 | |
76 | #define DW_IC_INTR_RX_FULL 0x004 | |
77 | #define DW_IC_INTR_TX_OVER 0x008 | |
78 | #define DW_IC_INTR_TX_EMPTY 0x010 | |
79 | #define DW_IC_INTR_RD_REQ 0x020 | |
80 | #define DW_IC_INTR_TX_ABRT 0x040 | |
81 | #define DW_IC_INTR_RX_DONE 0x080 | |
82 | #define DW_IC_INTR_ACTIVITY 0x100 | |
83 | #define DW_IC_INTR_STOP_DET 0x200 | |
84 | #define DW_IC_INTR_START_DET 0x400 | |
85 | #define DW_IC_INTR_GEN_CALL 0x800 | |
86 | ||
87 | #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ | |
88 | DW_IC_INTR_TX_EMPTY | \ | |
89 | DW_IC_INTR_TX_ABRT | \ | |
90 | DW_IC_INTR_STOP_DET) | |
91 | ||
92 | #define DW_IC_STATUS_ACTIVITY 0x1 | |
93 | ||
94 | #define DW_IC_ERR_TX_ABRT 0x1 | |
95 | ||
96 | /* | |
97 | * status codes | |
98 | */ | |
99 | #define STATUS_IDLE 0x0 | |
100 | #define STATUS_WRITE_IN_PROGRESS 0x1 | |
101 | #define STATUS_READ_IN_PROGRESS 0x2 | |
102 | ||
103 | #define TIMEOUT 20 /* ms */ | |
104 | ||
105 | /* | |
106 | * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register | |
107 | * | |
108 | * only expected abort codes are listed here | |
109 | * refer to the datasheet for the full list | |
110 | */ | |
111 | #define ABRT_7B_ADDR_NOACK 0 | |
112 | #define ABRT_10ADDR1_NOACK 1 | |
113 | #define ABRT_10ADDR2_NOACK 2 | |
114 | #define ABRT_TXDATA_NOACK 3 | |
115 | #define ABRT_GCALL_NOACK 4 | |
116 | #define ABRT_GCALL_READ 5 | |
117 | #define ABRT_SBYTE_ACKDET 7 | |
118 | #define ABRT_SBYTE_NORSTRT 9 | |
119 | #define ABRT_10B_RD_NORSTRT 10 | |
120 | #define ABRT_MASTER_DIS 11 | |
121 | #define ARB_LOST 12 | |
122 | ||
123 | #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) | |
124 | #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) | |
125 | #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) | |
126 | #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) | |
127 | #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) | |
128 | #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) | |
129 | #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) | |
130 | #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) | |
131 | #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) | |
132 | #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) | |
133 | #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) | |
134 | ||
135 | #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ | |
136 | DW_IC_TX_ABRT_10ADDR1_NOACK | \ | |
137 | DW_IC_TX_ABRT_10ADDR2_NOACK | \ | |
138 | DW_IC_TX_ABRT_TXDATA_NOACK | \ | |
139 | DW_IC_TX_ABRT_GCALL_NOACK) | |
140 | ||
1ab52cf9 | 141 | static char *abort_sources[] = { |
a0e06ea6 | 142 | [ABRT_7B_ADDR_NOACK] = |
1ab52cf9 | 143 | "slave address not acknowledged (7bit mode)", |
a0e06ea6 | 144 | [ABRT_10ADDR1_NOACK] = |
1ab52cf9 | 145 | "first address byte not acknowledged (10bit mode)", |
a0e06ea6 | 146 | [ABRT_10ADDR2_NOACK] = |
1ab52cf9 | 147 | "second address byte not acknowledged (10bit mode)", |
a0e06ea6 | 148 | [ABRT_TXDATA_NOACK] = |
1ab52cf9 | 149 | "data not acknowledged", |
a0e06ea6 | 150 | [ABRT_GCALL_NOACK] = |
1ab52cf9 | 151 | "no acknowledgement for a general call", |
a0e06ea6 | 152 | [ABRT_GCALL_READ] = |
1ab52cf9 | 153 | "read after general call", |
a0e06ea6 | 154 | [ABRT_SBYTE_ACKDET] = |
1ab52cf9 | 155 | "start byte acknowledged", |
a0e06ea6 | 156 | [ABRT_SBYTE_NORSTRT] = |
1ab52cf9 | 157 | "trying to send start byte when restart is disabled", |
a0e06ea6 | 158 | [ABRT_10B_RD_NORSTRT] = |
1ab52cf9 | 159 | "trying to read when restart is disabled (10bit mode)", |
a0e06ea6 | 160 | [ABRT_MASTER_DIS] = |
1ab52cf9 | 161 | "trying to use disabled adapter", |
a0e06ea6 | 162 | [ARB_LOST] = |
1ab52cf9 BS |
163 | "lost arbitration", |
164 | }; | |
165 | ||
2373f6b9 | 166 | u32 dw_readl(struct dw_i2c_dev *dev, int offset) |
7f279601 | 167 | { |
a8a9f3fe | 168 | u32 value; |
18c4089e | 169 | |
a8a9f3fe SR |
170 | if (dev->accessor_flags & ACCESS_16BIT) |
171 | value = readw(dev->base + offset) | | |
172 | (readw(dev->base + offset + 2) << 16); | |
173 | else | |
174 | value = readl(dev->base + offset); | |
175 | ||
176 | if (dev->accessor_flags & ACCESS_SWAP) | |
18c4089e JHD |
177 | return swab32(value); |
178 | else | |
179 | return value; | |
7f279601 JHD |
180 | } |
181 | ||
2373f6b9 | 182 | void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset) |
7f279601 | 183 | { |
a8a9f3fe | 184 | if (dev->accessor_flags & ACCESS_SWAP) |
18c4089e JHD |
185 | b = swab32(b); |
186 | ||
a8a9f3fe SR |
187 | if (dev->accessor_flags & ACCESS_16BIT) { |
188 | writew((u16)b, dev->base + offset); | |
189 | writew((u16)(b >> 16), dev->base + offset + 2); | |
190 | } else { | |
191 | writel(b, dev->base + offset); | |
192 | } | |
7f279601 JHD |
193 | } |
194 | ||
d60c7e81 SK |
195 | static u32 |
196 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) | |
197 | { | |
198 | /* | |
199 | * DesignWare I2C core doesn't seem to have solid strategy to meet | |
200 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec | |
201 | * will result in violation of the tHD;STA spec. | |
202 | */ | |
203 | if (cond) | |
204 | /* | |
205 | * Conditional expression: | |
206 | * | |
207 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH | |
208 | * | |
209 | * This is based on the DW manuals, and represents an ideal | |
210 | * configuration. The resulting I2C bus speed will be | |
211 | * faster than any of the others. | |
212 | * | |
213 | * If your hardware is free from tHD;STA issue, try this one. | |
214 | */ | |
215 | return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset; | |
216 | else | |
217 | /* | |
218 | * Conditional expression: | |
219 | * | |
220 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) | |
221 | * | |
222 | * This is just experimental rule; the tHD;STA period turned | |
223 | * out to be proportinal to (_HCNT + 3). With this setting, | |
224 | * we could meet both tHIGH and tHD;STA timing specs. | |
225 | * | |
226 | * If unsure, you'd better to take this alternative. | |
227 | * | |
228 | * The reason why we need to take into account "tf" here, | |
229 | * is the same as described in i2c_dw_scl_lcnt(). | |
230 | */ | |
231 | return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset; | |
232 | } | |
233 | ||
234 | static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) | |
235 | { | |
236 | /* | |
237 | * Conditional expression: | |
238 | * | |
239 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) | |
240 | * | |
241 | * DW I2C core starts counting the SCL CNTs for the LOW period | |
242 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. | |
243 | * In order to meet the tLOW timing spec, we need to take into | |
244 | * account the fall time of SCL signal (tf). Default tf value | |
245 | * should be 0.3 us, for safety. | |
246 | */ | |
247 | return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset; | |
248 | } | |
249 | ||
1ab52cf9 BS |
250 | /** |
251 | * i2c_dw_init() - initialize the designware i2c master hardware | |
252 | * @dev: device private data | |
253 | * | |
254 | * This functions configures and enables the I2C master. | |
255 | * This function is called during I2C init function, and in case of timeout at | |
256 | * run time. | |
257 | */ | |
2373f6b9 | 258 | int i2c_dw_init(struct dw_i2c_dev *dev) |
1ab52cf9 | 259 | { |
1d31b58f | 260 | u32 input_clock_khz; |
e18563fc | 261 | u32 hcnt, lcnt; |
4a423a8c DB |
262 | u32 reg; |
263 | ||
1d31b58f DB |
264 | input_clock_khz = dev->get_clk_rate_khz(dev); |
265 | ||
4a423a8c DB |
266 | reg = dw_readl(dev, DW_IC_COMP_TYPE); |
267 | if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) { | |
a8a9f3fe SR |
268 | /* Configure register endianess access */ |
269 | dev->accessor_flags |= ACCESS_SWAP; | |
270 | } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { | |
271 | /* Configure register access mode 16bit */ | |
272 | dev->accessor_flags |= ACCESS_16BIT; | |
273 | } else if (reg != DW_IC_COMP_TYPE_VALUE) { | |
4a423a8c DB |
274 | dev_err(dev->dev, "Unknown Synopsys component type: " |
275 | "0x%08x\n", reg); | |
276 | return -ENODEV; | |
277 | } | |
1ab52cf9 BS |
278 | |
279 | /* Disable the adapter */ | |
7f279601 | 280 | dw_writel(dev, 0, DW_IC_ENABLE); |
1ab52cf9 BS |
281 | |
282 | /* set standard and fast speed deviders for high/low periods */ | |
d60c7e81 SK |
283 | |
284 | /* Standard-mode */ | |
285 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
286 | 40, /* tHD;STA = tHIGH = 4.0 us */ | |
287 | 3, /* tf = 0.3 us */ | |
288 | 0, /* 0: DW default, 1: Ideal */ | |
289 | 0); /* No offset */ | |
290 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
291 | 47, /* tLOW = 4.7 us */ | |
292 | 3, /* tf = 0.3 us */ | |
293 | 0); /* No offset */ | |
7f279601 JHD |
294 | dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); |
295 | dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); | |
d60c7e81 SK |
296 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
297 | ||
298 | /* Fast-mode */ | |
299 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
300 | 6, /* tHD;STA = tHIGH = 0.6 us */ | |
301 | 3, /* tf = 0.3 us */ | |
302 | 0, /* 0: DW default, 1: Ideal */ | |
303 | 0); /* No offset */ | |
304 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
305 | 13, /* tLOW = 1.3 us */ | |
306 | 3, /* tf = 0.3 us */ | |
307 | 0); /* No offset */ | |
7f279601 JHD |
308 | dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); |
309 | dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); | |
d60c7e81 | 310 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
1ab52cf9 | 311 | |
4cb6d1d6 | 312 | /* Configure Tx/Rx FIFO threshold levels */ |
7f279601 JHD |
313 | dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL); |
314 | dw_writel(dev, 0, DW_IC_RX_TL); | |
4cb6d1d6 | 315 | |
1ab52cf9 | 316 | /* configure the i2c master */ |
e18563fc | 317 | dw_writel(dev, dev->master_cfg , DW_IC_CON); |
4a423a8c | 318 | return 0; |
1ab52cf9 | 319 | } |
e68bb91b | 320 | EXPORT_SYMBOL_GPL(i2c_dw_init); |
1ab52cf9 BS |
321 | |
322 | /* | |
323 | * Waiting for bus not busy | |
324 | */ | |
325 | static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) | |
326 | { | |
327 | int timeout = TIMEOUT; | |
328 | ||
7f279601 | 329 | while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
1ab52cf9 BS |
330 | if (timeout <= 0) { |
331 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
332 | return -ETIMEDOUT; | |
333 | } | |
334 | timeout--; | |
335 | mdelay(1); | |
336 | } | |
337 | ||
338 | return 0; | |
339 | } | |
340 | ||
81e798b7 SK |
341 | static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) |
342 | { | |
343 | struct i2c_msg *msgs = dev->msgs; | |
344 | u32 ic_con; | |
345 | ||
346 | /* Disable the adapter */ | |
7f279601 | 347 | dw_writel(dev, 0, DW_IC_ENABLE); |
81e798b7 SK |
348 | |
349 | /* set the slave (target) address */ | |
7f279601 | 350 | dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR); |
81e798b7 SK |
351 | |
352 | /* if the slave address is ten bit address, enable 10BITADDR */ | |
7f279601 | 353 | ic_con = dw_readl(dev, DW_IC_CON); |
81e798b7 SK |
354 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) |
355 | ic_con |= DW_IC_CON_10BITADDR_MASTER; | |
356 | else | |
357 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; | |
7f279601 | 358 | dw_writel(dev, ic_con, DW_IC_CON); |
81e798b7 SK |
359 | |
360 | /* Enable the adapter */ | |
7f279601 | 361 | dw_writel(dev, 1, DW_IC_ENABLE); |
201d6a70 SK |
362 | |
363 | /* Enable interrupts */ | |
7f279601 | 364 | dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK); |
81e798b7 SK |
365 | } |
366 | ||
1ab52cf9 | 367 | /* |
201d6a70 SK |
368 | * Initiate (and continue) low level master read/write transaction. |
369 | * This function is only called from i2c_dw_isr, and pumping i2c_msg | |
370 | * messages into the tx buffer. Even if the size of i2c_msg data is | |
371 | * longer than the size of the tx buffer, it handles everything. | |
1ab52cf9 | 372 | */ |
2373f6b9 | 373 | void |
e77cf232 | 374 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
1ab52cf9 | 375 | { |
1ab52cf9 | 376 | struct i2c_msg *msgs = dev->msgs; |
81e798b7 | 377 | u32 intr_mask; |
ae72222d | 378 | int tx_limit, rx_limit; |
ed5e1dd5 SK |
379 | u32 addr = msgs[dev->msg_write_idx].addr; |
380 | u32 buf_len = dev->tx_buf_len; | |
69932487 | 381 | u8 *buf = dev->tx_buf; |
1ab52cf9 | 382 | |
201d6a70 | 383 | intr_mask = DW_IC_INTR_DEFAULT_MASK; |
c70c5cd3 | 384 | |
6d2ea487 | 385 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
a0e06ea6 SK |
386 | /* |
387 | * if target address has changed, we need to | |
1ab52cf9 BS |
388 | * reprogram the target address in the i2c |
389 | * adapter when we are done with this transfer | |
390 | */ | |
8f588e40 SK |
391 | if (msgs[dev->msg_write_idx].addr != addr) { |
392 | dev_err(dev->dev, | |
393 | "%s: invalid target address\n", __func__); | |
394 | dev->msg_err = -EINVAL; | |
395 | break; | |
396 | } | |
1ab52cf9 BS |
397 | |
398 | if (msgs[dev->msg_write_idx].len == 0) { | |
399 | dev_err(dev->dev, | |
400 | "%s: invalid message length\n", __func__); | |
401 | dev->msg_err = -EINVAL; | |
8f588e40 | 402 | break; |
1ab52cf9 BS |
403 | } |
404 | ||
405 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { | |
406 | /* new i2c_msg */ | |
26ea15b1 | 407 | buf = msgs[dev->msg_write_idx].buf; |
1ab52cf9 BS |
408 | buf_len = msgs[dev->msg_write_idx].len; |
409 | } | |
410 | ||
7f279601 JHD |
411 | tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR); |
412 | rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR); | |
ae72222d | 413 | |
1ab52cf9 BS |
414 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { |
415 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { | |
7f279601 | 416 | dw_writel(dev, 0x100, DW_IC_DATA_CMD); |
1ab52cf9 BS |
417 | rx_limit--; |
418 | } else | |
7f279601 | 419 | dw_writel(dev, *buf++, DW_IC_DATA_CMD); |
1ab52cf9 BS |
420 | tx_limit--; buf_len--; |
421 | } | |
c70c5cd3 | 422 | |
26ea15b1 | 423 | dev->tx_buf = buf; |
c70c5cd3 SK |
424 | dev->tx_buf_len = buf_len; |
425 | ||
426 | if (buf_len > 0) { | |
427 | /* more bytes to be written */ | |
c70c5cd3 SK |
428 | dev->status |= STATUS_WRITE_IN_PROGRESS; |
429 | break; | |
69151e53 | 430 | } else |
c70c5cd3 | 431 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; |
1ab52cf9 BS |
432 | } |
433 | ||
69151e53 SK |
434 | /* |
435 | * If i2c_msg index search is completed, we don't need TX_EMPTY | |
436 | * interrupt any more. | |
437 | */ | |
438 | if (dev->msg_write_idx == dev->msgs_num) | |
439 | intr_mask &= ~DW_IC_INTR_TX_EMPTY; | |
440 | ||
8f588e40 SK |
441 | if (dev->msg_err) |
442 | intr_mask = 0; | |
443 | ||
2373f6b9 | 444 | dw_writel(dev, intr_mask, DW_IC_INTR_MASK); |
1ab52cf9 BS |
445 | } |
446 | ||
447 | static void | |
78839bd0 | 448 | i2c_dw_read(struct dw_i2c_dev *dev) |
1ab52cf9 | 449 | { |
1ab52cf9 | 450 | struct i2c_msg *msgs = dev->msgs; |
ae72222d | 451 | int rx_valid; |
1ab52cf9 | 452 | |
6d2ea487 | 453 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
ed5e1dd5 | 454 | u32 len; |
1ab52cf9 BS |
455 | u8 *buf; |
456 | ||
457 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) | |
458 | continue; | |
459 | ||
1ab52cf9 BS |
460 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { |
461 | len = msgs[dev->msg_read_idx].len; | |
462 | buf = msgs[dev->msg_read_idx].buf; | |
463 | } else { | |
464 | len = dev->rx_buf_len; | |
465 | buf = dev->rx_buf; | |
466 | } | |
467 | ||
7f279601 | 468 | rx_valid = dw_readl(dev, DW_IC_RXFLR); |
ae72222d | 469 | |
1ab52cf9 | 470 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) |
7f279601 | 471 | *buf++ = dw_readl(dev, DW_IC_DATA_CMD); |
1ab52cf9 BS |
472 | |
473 | if (len > 0) { | |
474 | dev->status |= STATUS_READ_IN_PROGRESS; | |
475 | dev->rx_buf_len = len; | |
476 | dev->rx_buf = buf; | |
477 | return; | |
478 | } else | |
479 | dev->status &= ~STATUS_READ_IN_PROGRESS; | |
480 | } | |
481 | } | |
482 | ||
ce6eb574 SK |
483 | static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) |
484 | { | |
485 | unsigned long abort_source = dev->abort_source; | |
486 | int i; | |
487 | ||
6d1ea0f6 | 488 | if (abort_source & DW_IC_TX_ABRT_NOACK) { |
984b3f57 | 489 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
6d1ea0f6 SK |
490 | dev_dbg(dev->dev, |
491 | "%s: %s\n", __func__, abort_sources[i]); | |
492 | return -EREMOTEIO; | |
493 | } | |
494 | ||
984b3f57 | 495 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
ce6eb574 SK |
496 | dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); |
497 | ||
498 | if (abort_source & DW_IC_TX_ARB_LOST) | |
499 | return -EAGAIN; | |
ce6eb574 SK |
500 | else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) |
501 | return -EINVAL; /* wrong msgs[] data */ | |
502 | else | |
503 | return -EIO; | |
504 | } | |
505 | ||
1ab52cf9 BS |
506 | /* |
507 | * Prepare controller for a transaction and call i2c_dw_xfer_msg | |
508 | */ | |
2373f6b9 | 509 | int |
1ab52cf9 BS |
510 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) |
511 | { | |
512 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); | |
513 | int ret; | |
514 | ||
515 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); | |
516 | ||
517 | mutex_lock(&dev->lock); | |
18dbdda8 | 518 | pm_runtime_get_sync(dev->dev); |
1ab52cf9 BS |
519 | |
520 | INIT_COMPLETION(dev->cmd_complete); | |
521 | dev->msgs = msgs; | |
522 | dev->msgs_num = num; | |
523 | dev->cmd_err = 0; | |
524 | dev->msg_write_idx = 0; | |
525 | dev->msg_read_idx = 0; | |
526 | dev->msg_err = 0; | |
527 | dev->status = STATUS_IDLE; | |
ce6eb574 | 528 | dev->abort_source = 0; |
1ab52cf9 BS |
529 | |
530 | ret = i2c_dw_wait_bus_not_busy(dev); | |
531 | if (ret < 0) | |
532 | goto done; | |
533 | ||
534 | /* start the transfers */ | |
81e798b7 | 535 | i2c_dw_xfer_init(dev); |
1ab52cf9 BS |
536 | |
537 | /* wait for tx to complete */ | |
538 | ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ); | |
539 | if (ret == 0) { | |
540 | dev_err(dev->dev, "controller timed out\n"); | |
541 | i2c_dw_init(dev); | |
542 | ret = -ETIMEDOUT; | |
543 | goto done; | |
544 | } else if (ret < 0) | |
545 | goto done; | |
546 | ||
547 | if (dev->msg_err) { | |
548 | ret = dev->msg_err; | |
549 | goto done; | |
550 | } | |
551 | ||
552 | /* no error */ | |
553 | if (likely(!dev->cmd_err)) { | |
07745399 | 554 | /* Disable the adapter */ |
7f279601 | 555 | dw_writel(dev, 0, DW_IC_ENABLE); |
1ab52cf9 BS |
556 | ret = num; |
557 | goto done; | |
558 | } | |
559 | ||
560 | /* We have an error */ | |
561 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { | |
ce6eb574 SK |
562 | ret = i2c_dw_handle_tx_abort(dev); |
563 | goto done; | |
1ab52cf9 BS |
564 | } |
565 | ret = -EIO; | |
566 | ||
567 | done: | |
18dbdda8 | 568 | pm_runtime_put(dev->dev); |
1ab52cf9 BS |
569 | mutex_unlock(&dev->lock); |
570 | ||
571 | return ret; | |
572 | } | |
e68bb91b | 573 | EXPORT_SYMBOL_GPL(i2c_dw_xfer); |
1ab52cf9 | 574 | |
2373f6b9 | 575 | u32 i2c_dw_func(struct i2c_adapter *adap) |
1ab52cf9 | 576 | { |
2fa8326b DB |
577 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); |
578 | return dev->functionality; | |
1ab52cf9 | 579 | } |
e68bb91b | 580 | EXPORT_SYMBOL_GPL(i2c_dw_func); |
1ab52cf9 | 581 | |
e28000a3 SK |
582 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
583 | { | |
584 | u32 stat; | |
585 | ||
586 | /* | |
587 | * The IC_INTR_STAT register just indicates "enabled" interrupts. | |
588 | * Ths unmasked raw version of interrupt status bits are available | |
589 | * in the IC_RAW_INTR_STAT register. | |
590 | * | |
591 | * That is, | |
2373f6b9 | 592 | * stat = dw_readl(IC_INTR_STAT); |
e28000a3 | 593 | * equals to, |
2373f6b9 | 594 | * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK); |
e28000a3 SK |
595 | * |
596 | * The raw version might be useful for debugging purposes. | |
597 | */ | |
7f279601 | 598 | stat = dw_readl(dev, DW_IC_INTR_STAT); |
e28000a3 SK |
599 | |
600 | /* | |
601 | * Do not use the IC_CLR_INTR register to clear interrupts, or | |
602 | * you'll miss some interrupts, triggered during the period from | |
2373f6b9 | 603 | * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR). |
e28000a3 SK |
604 | * |
605 | * Instead, use the separately-prepared IC_CLR_* registers. | |
606 | */ | |
607 | if (stat & DW_IC_INTR_RX_UNDER) | |
7f279601 | 608 | dw_readl(dev, DW_IC_CLR_RX_UNDER); |
e28000a3 | 609 | if (stat & DW_IC_INTR_RX_OVER) |
7f279601 | 610 | dw_readl(dev, DW_IC_CLR_RX_OVER); |
e28000a3 | 611 | if (stat & DW_IC_INTR_TX_OVER) |
7f279601 | 612 | dw_readl(dev, DW_IC_CLR_TX_OVER); |
e28000a3 | 613 | if (stat & DW_IC_INTR_RD_REQ) |
7f279601 | 614 | dw_readl(dev, DW_IC_CLR_RD_REQ); |
e28000a3 SK |
615 | if (stat & DW_IC_INTR_TX_ABRT) { |
616 | /* | |
617 | * The IC_TX_ABRT_SOURCE register is cleared whenever | |
618 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. | |
619 | */ | |
7f279601 JHD |
620 | dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE); |
621 | dw_readl(dev, DW_IC_CLR_TX_ABRT); | |
e28000a3 SK |
622 | } |
623 | if (stat & DW_IC_INTR_RX_DONE) | |
7f279601 | 624 | dw_readl(dev, DW_IC_CLR_RX_DONE); |
e28000a3 | 625 | if (stat & DW_IC_INTR_ACTIVITY) |
7f279601 | 626 | dw_readl(dev, DW_IC_CLR_ACTIVITY); |
e28000a3 | 627 | if (stat & DW_IC_INTR_STOP_DET) |
7f279601 | 628 | dw_readl(dev, DW_IC_CLR_STOP_DET); |
e28000a3 | 629 | if (stat & DW_IC_INTR_START_DET) |
7f279601 | 630 | dw_readl(dev, DW_IC_CLR_START_DET); |
e28000a3 | 631 | if (stat & DW_IC_INTR_GEN_CALL) |
7f279601 | 632 | dw_readl(dev, DW_IC_CLR_GEN_CALL); |
e28000a3 SK |
633 | |
634 | return stat; | |
635 | } | |
636 | ||
1ab52cf9 BS |
637 | /* |
638 | * Interrupt service routine. This gets called whenever an I2C interrupt | |
639 | * occurs. | |
640 | */ | |
2373f6b9 | 641 | irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) |
1ab52cf9 BS |
642 | { |
643 | struct dw_i2c_dev *dev = dev_id; | |
af06cf6c DB |
644 | u32 stat, enabled; |
645 | ||
646 | enabled = dw_readl(dev, DW_IC_ENABLE); | |
647 | stat = dw_readl(dev, DW_IC_RAW_INTR_STAT); | |
648 | dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__, | |
649 | dev->adapter.name, enabled, stat); | |
650 | if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY)) | |
651 | return IRQ_NONE; | |
1ab52cf9 | 652 | |
e28000a3 | 653 | stat = i2c_dw_read_clear_intrbits(dev); |
e28000a3 | 654 | |
1ab52cf9 | 655 | if (stat & DW_IC_INTR_TX_ABRT) { |
1ab52cf9 BS |
656 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
657 | dev->status = STATUS_IDLE; | |
597fe310 SK |
658 | |
659 | /* | |
660 | * Anytime TX_ABRT is set, the contents of the tx/rx | |
661 | * buffers are flushed. Make sure to skip them. | |
662 | */ | |
7f279601 | 663 | dw_writel(dev, 0, DW_IC_INTR_MASK); |
597fe310 | 664 | goto tx_aborted; |
07745399 SK |
665 | } |
666 | ||
21a89d41 | 667 | if (stat & DW_IC_INTR_RX_FULL) |
07745399 | 668 | i2c_dw_read(dev); |
21a89d41 SK |
669 | |
670 | if (stat & DW_IC_INTR_TX_EMPTY) | |
07745399 | 671 | i2c_dw_xfer_msg(dev); |
07745399 SK |
672 | |
673 | /* | |
674 | * No need to modify or disable the interrupt mask here. | |
675 | * i2c_dw_xfer_msg() will take care of it according to | |
676 | * the current transmit status. | |
677 | */ | |
1ab52cf9 | 678 | |
597fe310 | 679 | tx_aborted: |
8f588e40 | 680 | if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) |
1ab52cf9 BS |
681 | complete(&dev->cmd_complete); |
682 | ||
683 | return IRQ_HANDLED; | |
684 | } | |
e68bb91b | 685 | EXPORT_SYMBOL_GPL(i2c_dw_isr); |
f3fa9f3d DB |
686 | |
687 | void i2c_dw_enable(struct dw_i2c_dev *dev) | |
688 | { | |
689 | /* Enable the adapter */ | |
690 | dw_writel(dev, 1, DW_IC_ENABLE); | |
691 | } | |
e68bb91b | 692 | EXPORT_SYMBOL_GPL(i2c_dw_enable); |
f3fa9f3d | 693 | |
18dbdda8 | 694 | u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev) |
f3fa9f3d | 695 | { |
18dbdda8 DB |
696 | return dw_readl(dev, DW_IC_ENABLE); |
697 | } | |
e68bb91b | 698 | EXPORT_SYMBOL_GPL(i2c_dw_is_enabled); |
f3fa9f3d | 699 | |
18dbdda8 DB |
700 | void i2c_dw_disable(struct dw_i2c_dev *dev) |
701 | { | |
f3fa9f3d DB |
702 | /* Disable controller */ |
703 | dw_writel(dev, 0, DW_IC_ENABLE); | |
704 | ||
705 | /* Disable all interupts */ | |
706 | dw_writel(dev, 0, DW_IC_INTR_MASK); | |
707 | dw_readl(dev, DW_IC_CLR_INTR); | |
708 | } | |
e68bb91b | 709 | EXPORT_SYMBOL_GPL(i2c_dw_disable); |
f3fa9f3d DB |
710 | |
711 | void i2c_dw_clear_int(struct dw_i2c_dev *dev) | |
712 | { | |
713 | dw_readl(dev, DW_IC_CLR_INTR); | |
714 | } | |
e68bb91b | 715 | EXPORT_SYMBOL_GPL(i2c_dw_clear_int); |
f3fa9f3d DB |
716 | |
717 | void i2c_dw_disable_int(struct dw_i2c_dev *dev) | |
718 | { | |
719 | dw_writel(dev, 0, DW_IC_INTR_MASK); | |
720 | } | |
e68bb91b | 721 | EXPORT_SYMBOL_GPL(i2c_dw_disable_int); |
f3fa9f3d DB |
722 | |
723 | u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev) | |
724 | { | |
725 | return dw_readl(dev, DW_IC_COMP_PARAM_1); | |
726 | } | |
e68bb91b | 727 | EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param); |