[deliverable/linux.git] / drivers / i2c / busses / i2c-designware-pcidrv.c

/*
 * Synopsys DesignWare I2C adapter driver (master only).
 *
 * Based on the TI DAVINCI I2C adapter driver.
 *
 * Copyright (C) 2006 Texas Instruments.
 * Copyright (C) 2007 MontaVista Software Inc.
 * Copyright (C) 2009 Provigent Ltd.
 * Copyright (C) 2011 Intel corporation.
 *
 * ----------------------------------------------------------------------------
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * ----------------------------------------------------------------------------
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/pm_runtime.h>
#include "i2c-designware-core.h"

#define DRIVER_NAME "i2c-designware-pci"

enum dw_pci_ctl_id_t {
	moorestown_0,
	moorestown_1,
	moorestown_2,

	medfield_0,
	medfield_1,
	medfield_2,
	medfield_3,
	medfield_4,
	medfield_5,

	baytrail,
	haswell,
};

struct dw_scl_sda_cfg {
	u32 ss_hcnt;
	u32 fs_hcnt;
	u32 ss_lcnt;
	u32 fs_lcnt;
	u32 sda_hold;
};

struct dw_pci_controller {
	u32 bus_num;
	u32 bus_cfg;
	u32 tx_fifo_depth;
	u32 rx_fifo_depth;
	u32 clk_khz;
	u32 functionality;
	struct dw_scl_sda_cfg *scl_sda_cfg;
};

#define INTEL_MID_STD_CFG  (DW_IC_CON_MASTER |			\
				DW_IC_CON_SLAVE_DISABLE |	\
				DW_IC_CON_RESTART_EN)

#define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C |			\
					I2C_FUNC_SMBUS_BYTE |		\
					I2C_FUNC_SMBUS_BYTE_DATA |	\
					I2C_FUNC_SMBUS_WORD_DATA |	\
					I2C_FUNC_SMBUS_I2C_BLOCK)

/* BayTrail HCNT/LCNT/SDA hold time */
static struct dw_scl_sda_cfg byt_config = {
	.ss_hcnt = 0x200,
	.fs_hcnt = 0x55,
	.ss_lcnt = 0x200,
	.fs_lcnt = 0x99,
	.sda_hold = 0x6,
};

/* Haswell HCNT/LCNT/SDA hold time */
static struct dw_scl_sda_cfg hsw_config = {
	.ss_hcnt = 0x01b0,
	.fs_hcnt = 0x48,
	.ss_lcnt = 0x01fb,
	.fs_lcnt = 0xa0,
	.sda_hold = 0x9,
};

static struct  dw_pci_controller  dw_pci_controllers[] = {
	[moorestown_0] = {
		.bus_num     = 0,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[moorestown_1] = {
		.bus_num     = 1,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[moorestown_2] = {
		.bus_num     = 2,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[medfield_0] = {
		.bus_num     = 0,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[medfield_1] = {
		.bus_num     = 1,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[medfield_2] = {
		.bus_num     = 2,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[medfield_3] = {
		.bus_num     = 3,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[medfield_4] = {
		.bus_num     = 4,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[medfield_5] = {
		.bus_num     = 5,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[baytrail] = {
		.bus_num = -1,
		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz = 100000,
		.functionality = I2C_FUNC_10BIT_ADDR,
		.scl_sda_cfg = &byt_config,
	},
	[haswell] = {
		.bus_num = -1,
		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz = 100000,
		.functionality = I2C_FUNC_10BIT_ADDR,
		.scl_sda_cfg = &hsw_config,
	},
};

static struct i2c_algorithm i2c_dw_algo = {
	.master_xfer	= i2c_dw_xfer,
	.functionality	= i2c_dw_func,
};

#ifdef CONFIG_PM
static int i2c_dw_pci_suspend(struct device *dev)
{
	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);

	i2c_dw_disable(pci_get_drvdata(pdev));
	return 0;
}

static int i2c_dw_pci_resume(struct device *dev)
{
	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);

	return i2c_dw_init(pci_get_drvdata(pdev));
}
#endif

static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
			    i2c_dw_pci_resume, NULL);

static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
{
	return dev->controller->clk_khz;
}

static int i2c_dw_pci_probe(struct pci_dev *pdev,
			    const struct pci_device_id *id)
{
	struct dw_i2c_dev *dev;
	struct i2c_adapter *adap;
	int r;
	struct  dw_pci_controller *controller;
	struct dw_scl_sda_cfg *cfg;

	if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
		dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
			id->driver_data);
		return -EINVAL;
	}

	controller = &dw_pci_controllers[id->driver_data];

	r = pcim_enable_device(pdev);
	if (r) {
		dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
			r);
		return r;
	}

	r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
	if (r) {
		dev_err(&pdev->dev, "I/O memory remapping failed\n");
		return r;
	}

	dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
	if (!dev)
		return -ENOMEM;

	init_completion(&dev->cmd_complete);
	mutex_init(&dev->lock);
	dev->clk = NULL;
	dev->controller = controller;
	dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
	dev->base = pcim_iomap_table(pdev)[0];
	dev->dev = &pdev->dev;
	dev->functionality = controller->functionality |
				DW_DEFAULT_FUNCTIONALITY;

	dev->master_cfg =  controller->bus_cfg;
	if (controller->scl_sda_cfg) {
		cfg = controller->scl_sda_cfg;
		dev->ss_hcnt = cfg->ss_hcnt;
		dev->fs_hcnt = cfg->fs_hcnt;
		dev->ss_lcnt = cfg->ss_lcnt;
		dev->fs_lcnt = cfg->fs_lcnt;
		dev->sda_hold_time = cfg->sda_hold;
	}

	pci_set_drvdata(pdev, dev);

	dev->tx_fifo_depth = controller->tx_fifo_depth;
	dev->rx_fifo_depth = controller->rx_fifo_depth;
	r = i2c_dw_init(dev);
	if (r)
		return r;

	adap = &dev->adapter;
	i2c_set_adapdata(adap, dev);
	adap->owner = THIS_MODULE;
	adap->class = 0;
	adap->algo = &i2c_dw_algo;
	adap->dev.parent = &pdev->dev;
	adap->nr = controller->bus_num;

	snprintf(adap->name, sizeof(adap->name), "i2c-designware-pci");

	r = devm_request_irq(&pdev->dev, pdev->irq, i2c_dw_isr, IRQF_SHARED,
			adap->name, dev);
	if (r) {
		dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
		return r;
	}

	i2c_dw_disable_int(dev);
	i2c_dw_clear_int(dev);
	r = i2c_add_numbered_adapter(adap);
	if (r) {
		dev_err(&pdev->dev, "failure adding adapter\n");
		return r;
	}

	pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_put_autosuspend(&pdev->dev);
	pm_runtime_allow(&pdev->dev);

	return 0;
}

static void i2c_dw_pci_remove(struct pci_dev *pdev)
{
	struct dw_i2c_dev *dev = pci_get_drvdata(pdev);

	i2c_dw_disable(dev);
	pm_runtime_forbid(&pdev->dev);
	pm_runtime_get_noresume(&pdev->dev);

	i2c_del_adapter(&dev->adapter);
}

/* work with hotplug and coldplug */
MODULE_ALIAS("i2c_designware-pci");

static const struct pci_device_id i2_designware_pci_ids[] = {
	/* Moorestown */
	{ PCI_VDEVICE(INTEL, 0x0802), moorestown_0 },
	{ PCI_VDEVICE(INTEL, 0x0803), moorestown_1 },
	{ PCI_VDEVICE(INTEL, 0x0804), moorestown_2 },
	/* Medfield */
	{ PCI_VDEVICE(INTEL, 0x0817), medfield_3,},
	{ PCI_VDEVICE(INTEL, 0x0818), medfield_4 },
	{ PCI_VDEVICE(INTEL, 0x0819), medfield_5 },
	{ PCI_VDEVICE(INTEL, 0x082C), medfield_0 },
	{ PCI_VDEVICE(INTEL, 0x082D), medfield_1 },
	{ PCI_VDEVICE(INTEL, 0x082E), medfield_2 },
	/* Baytrail */
	{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F43), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F44), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F45), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F46), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F47), baytrail },
	/* Haswell */
	{ PCI_VDEVICE(INTEL, 0x9c61), haswell },
	{ PCI_VDEVICE(INTEL, 0x9c62), haswell },
	/* Braswell / Cherrytrail */
	{ PCI_VDEVICE(INTEL, 0x22C1), baytrail,},
	{ PCI_VDEVICE(INTEL, 0x22C2), baytrail },
	{ PCI_VDEVICE(INTEL, 0x22C3), baytrail },
	{ PCI_VDEVICE(INTEL, 0x22C4), baytrail },
	{ PCI_VDEVICE(INTEL, 0x22C5), baytrail },
	{ PCI_VDEVICE(INTEL, 0x22C6), baytrail },
	{ PCI_VDEVICE(INTEL, 0x22C7), baytrail },
	{ 0,}
};
MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);

static struct pci_driver dw_i2c_driver = {
	.name		= DRIVER_NAME,
	.id_table	= i2_designware_pci_ids,
	.probe		= i2c_dw_pci_probe,
	.remove		= i2c_dw_pci_remove,
	.driver         = {
		.pm     = &i2c_dw_pm_ops,
	},
};

module_pci_driver(dw_i2c_driver);

MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
MODULE_LICENSE("GPL");
Commit	Line	Data
fe20ff5c DB	1	/*
	2	* Synopsys DesignWare I2C adapter driver (master only).
	3	*
	4	* Based on the TI DAVINCI I2C adapter driver.
	5	*
	6	* Copyright (C) 2006 Texas Instruments.
	7	* Copyright (C) 2007 MontaVista Software Inc.
	8	* Copyright (C) 2009 Provigent Ltd.
	9	* Copyright (C) 2011 Intel corporation.
	10	*
	11	* ----------------------------------------------------------------------------
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License as published by
	15	* the Free Software Foundation; either version 2 of the License, or
	16	* (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
fe20ff5c DB	22	* ----------------------------------------------------------------------------
	23	*
	24	*/
	25
	26	#include <linux/kernel.h>
	27	#include <linux/module.h>
	28	#include <linux/delay.h>
	29	#include <linux/i2c.h>
	30	#include <linux/errno.h>
	31	#include <linux/sched.h>
	32	#include <linux/err.h>
	33	#include <linux/interrupt.h>
	34	#include <linux/io.h>
	35	#include <linux/slab.h>
	36	#include <linux/pci.h>
18dbdda8	37	#include <linux/pm_runtime.h>
fe20ff5c DB	38	#include "i2c-designware-core.h"
	39
	40	#define DRIVER_NAME "i2c-designware-pci"
	41
	42	enum dw_pci_ctl_id_t {
	43	moorestown_0,
	44	moorestown_1,
	45	moorestown_2,
	46
	47	medfield_0,
	48	medfield_1,
	49	medfield_2,
	50	medfield_3,
	51	medfield_4,
	52	medfield_5,
089c729a MW	53
089c729a MW	54	baytrail,
157a801e	55	haswell,
fe20ff5c DB	56	};
fe20ff5c DB	57
8efd1e9e CCE	58	struct dw_scl_sda_cfg {
	59	u32 ss_hcnt;
	60	u32 fs_hcnt;
	61	u32 ss_lcnt;
	62	u32 fs_lcnt;
	63	u32 sda_hold;
	64	};
	65
fe20ff5c DB	66	struct dw_pci_controller {
	67	u32 bus_num;
	68	u32 bus_cfg;
	69	u32 tx_fifo_depth;
	70	u32 rx_fifo_depth;
	71	u32 clk_khz;
ceccd298	72	u32 functionality;
8efd1e9e	73	struct dw_scl_sda_cfg *scl_sda_cfg;
fe20ff5c DB	74	};
	75
	76	#define INTEL_MID_STD_CFG (DW_IC_CON_MASTER \| \
	77	DW_IC_CON_SLAVE_DISABLE \| \
	78	DW_IC_CON_RESTART_EN)
	79
ceccd298 CCE	80	#define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C \| \
	81	I2C_FUNC_SMBUS_BYTE \| \
	82	I2C_FUNC_SMBUS_BYTE_DATA \| \
	83	I2C_FUNC_SMBUS_WORD_DATA \| \
	84	I2C_FUNC_SMBUS_I2C_BLOCK)
	85
8efd1e9e CCE	86	/* BayTrail HCNT/LCNT/SDA hold time */
	87	static struct dw_scl_sda_cfg byt_config = {
	88	.ss_hcnt = 0x200,
	89	.fs_hcnt = 0x55,
	90	.ss_lcnt = 0x200,
	91	.fs_lcnt = 0x99,
	92	.sda_hold = 0x6,
	93	};
	94
157a801e MW	95	/* Haswell HCNT/LCNT/SDA hold time */
	96	static struct dw_scl_sda_cfg hsw_config = {
	97	.ss_hcnt = 0x01b0,
	98	.fs_hcnt = 0x48,
	99	.ss_lcnt = 0x01fb,
	100	.fs_lcnt = 0xa0,
	101	.sda_hold = 0x9,
	102	};
	103
fe20ff5c DB	104	static struct dw_pci_controller dw_pci_controllers[] = {
	105	[moorestown_0] = {
	106	.bus_num = 0,
	107	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	108	.tx_fifo_depth = 32,
	109	.rx_fifo_depth = 32,
	110	.clk_khz = 25000,
	111	},
	112	[moorestown_1] = {
	113	.bus_num = 1,
	114	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	115	.tx_fifo_depth = 32,
	116	.rx_fifo_depth = 32,
	117	.clk_khz = 25000,
	118	},
	119	[moorestown_2] = {
	120	.bus_num = 2,
	121	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	122	.tx_fifo_depth = 32,
	123	.rx_fifo_depth = 32,
	124	.clk_khz = 25000,
	125	},
	126	[medfield_0] = {
	127	.bus_num = 0,
	128	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	129	.tx_fifo_depth = 32,
	130	.rx_fifo_depth = 32,
	131	.clk_khz = 25000,
	132	},
	133	[medfield_1] = {
	134	.bus_num = 1,
	135	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	136	.tx_fifo_depth = 32,
	137	.rx_fifo_depth = 32,
	138	.clk_khz = 25000,
	139	},
	140	[medfield_2] = {
	141	.bus_num = 2,
	142	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	143	.tx_fifo_depth = 32,
	144	.rx_fifo_depth = 32,
	145	.clk_khz = 25000,
	146	},
	147	[medfield_3] = {
	148	.bus_num = 3,
	149	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_STD,
	150	.tx_fifo_depth = 32,
	151	.rx_fifo_depth = 32,
	152	.clk_khz = 25000,
	153	},
	154	[medfield_4] = {
	155	.bus_num = 4,
	156	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	157	.tx_fifo_depth = 32,
	158	.rx_fifo_depth = 32,
	159	.clk_khz = 25000,
	160	},
	161	[medfield_5] = {
	162	.bus_num = 5,
	163	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	164	.tx_fifo_depth = 32,
	165	.rx_fifo_depth = 32,
	166	.clk_khz = 25000,
	167	},
089c729a MW	168	[baytrail] = {
	169	.bus_num = -1,
	170	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	171	.tx_fifo_depth = 32,
	172	.rx_fifo_depth = 32,
	173	.clk_khz = 100000,
ceccd298	174	.functionality = I2C_FUNC_10BIT_ADDR,
8efd1e9e	175	.scl_sda_cfg = &byt_config,
089c729a	176	},
157a801e MW	177	[haswell] = {
	178	.bus_num = -1,
	179	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	180	.tx_fifo_depth = 32,
	181	.rx_fifo_depth = 32,
	182	.clk_khz = 100000,
	183	.functionality = I2C_FUNC_10BIT_ADDR,
	184	.scl_sda_cfg = &hsw_config,
	185	},
fe20ff5c	186	};
0409516a	187
fe20ff5c DB	188	static struct i2c_algorithm i2c_dw_algo = {
	189	.master_xfer = i2c_dw_xfer,
	190	.functionality = i2c_dw_func,
	191	};
	192
be58eda7	193	#ifdef CONFIG_PM
52c28433	194	static int i2c_dw_pci_suspend(struct device *dev)
18dbdda8	195	{
52c28433	196	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
18dbdda8	197
be58eda7	198	i2c_dw_disable(pci_get_drvdata(pdev));
18dbdda8 DB	199	return 0;
	200	}
	201
52c28433	202	static int i2c_dw_pci_resume(struct device *dev)
18dbdda8	203	{
52c28433	204	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
18dbdda8	205
be58eda7	206	return i2c_dw_init(pci_get_drvdata(pdev));
18dbdda8	207	}
be58eda7	208	#endif
18dbdda8	209
be58eda7 MW	210	static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
be58eda7 MW	211	i2c_dw_pci_resume, NULL);
18dbdda8	212
fe20ff5c DB	213	static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
	214	{
	215	return dev->controller->clk_khz;
	216	}
	217
0b255e92	218	static int i2c_dw_pci_probe(struct pci_dev *pdev,
ca0c1ff5	219	const struct pci_device_id *id)
fe20ff5c DB	220	{
	221	struct dw_i2c_dev *dev;
	222	struct i2c_adapter *adap;
fe20ff5c DB	223	int r;
fe20ff5c DB	224	struct dw_pci_controller *controller;
8efd1e9e	225	struct dw_scl_sda_cfg *cfg;
fe20ff5c DB	226
fe20ff5c DB	227	if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
ca0c1ff5	228	dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
fe20ff5c DB	229	id->driver_data);
	230	return -EINVAL;
	231	}
	232
	233	controller = &dw_pci_controllers[id->driver_data];
	234
76cf3fc8	235	r = pcim_enable_device(pdev);
fe20ff5c DB	236	if (r) {
	237	dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
	238	r);
76cf3fc8	239	return r;
fe20ff5c DB	240	}
fe20ff5c DB	241
76cf3fc8	242	r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
fe20ff5c	243	if (r) {
fe20ff5c	244	dev_err(&pdev->dev, "I/O memory remapping failed\n");
76cf3fc8	245	return r;
fe20ff5c DB	246	}
fe20ff5c DB	247
76cf3fc8 AS	248	dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
	249	if (!dev)
	250	return -ENOMEM;
fe20ff5c DB	251
	252	init_completion(&dev->cmd_complete);
	253	mutex_init(&dev->lock);
	254	dev->clk = NULL;
	255	dev->controller = controller;
	256	dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
76cf3fc8 AS	257	dev->base = pcim_iomap_table(pdev)[0];
76cf3fc8 AS	258	dev->dev = &pdev->dev;
ceccd298 CCE	259	dev->functionality = controller->functionality \|
	260	DW_DEFAULT_FUNCTIONALITY;
	261
fe20ff5c	262	dev->master_cfg = controller->bus_cfg;
8efd1e9e CCE	263	if (controller->scl_sda_cfg) {
	264	cfg = controller->scl_sda_cfg;
	265	dev->ss_hcnt = cfg->ss_hcnt;
	266	dev->fs_hcnt = cfg->fs_hcnt;
	267	dev->ss_lcnt = cfg->ss_lcnt;
	268	dev->fs_lcnt = cfg->fs_lcnt;
	269	dev->sda_hold_time = cfg->sda_hold;
	270	}
fe20ff5c DB	271
	272	pci_set_drvdata(pdev, dev);
	273
	274	dev->tx_fifo_depth = controller->tx_fifo_depth;
	275	dev->rx_fifo_depth = controller->rx_fifo_depth;
	276	r = i2c_dw_init(dev);
	277	if (r)
76cf3fc8	278	return r;
fe20ff5c DB	279
	280	adap = &dev->adapter;
	281	i2c_set_adapdata(adap, dev);
	282	adap->owner = THIS_MODULE;
	283	adap->class = 0;
	284	adap->algo = &i2c_dw_algo;
	285	adap->dev.parent = &pdev->dev;
	286	adap->nr = controller->bus_num;
089c729a MW	287
089c729a MW	288	snprintf(adap->name, sizeof(adap->name), "i2c-designware-pci");
fe20ff5c	289
76cf3fc8 AS	290	r = devm_request_irq(&pdev->dev, pdev->irq, i2c_dw_isr, IRQF_SHARED,
76cf3fc8 AS	291	adap->name, dev);
fe20ff5c DB	292	if (r) {
fe20ff5c DB	293	dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
76cf3fc8	294	return r;
fe20ff5c DB	295	}
	296
	297	i2c_dw_disable_int(dev);
	298	i2c_dw_clear_int(dev);
	299	r = i2c_add_numbered_adapter(adap);
	300	if (r) {
	301	dev_err(&pdev->dev, "failure adding adapter\n");
76cf3fc8	302	return r;
fe20ff5c DB	303	}
fe20ff5c DB	304
43452335 MW	305	pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
43452335 MW	306	pm_runtime_use_autosuspend(&pdev->dev);
be58eda7	307	pm_runtime_put_autosuspend(&pdev->dev);
18dbdda8 DB	308	pm_runtime_allow(&pdev->dev);
18dbdda8 DB	309
fe20ff5c	310	return 0;
fe20ff5c DB	311	}
fe20ff5c DB	312
0b255e92	313	static void i2c_dw_pci_remove(struct pci_dev *pdev)
fe20ff5c DB	314	{
	315	struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
	316
18dbdda8 DB	317	i2c_dw_disable(dev);
	318	pm_runtime_forbid(&pdev->dev);
	319	pm_runtime_get_noresume(&pdev->dev);
	320
fe20ff5c	321	i2c_del_adapter(&dev->adapter);
fe20ff5c DB	322	}
	323
	324	/* work with hotplug and coldplug */
	325	MODULE_ALIAS("i2c_designware-pci");
	326
392debf1	327	static const struct pci_device_id i2_designware_pci_ids[] = {
fe20ff5c DB	328	/* Moorestown */
	329	{ PCI_VDEVICE(INTEL, 0x0802), moorestown_0 },
	330	{ PCI_VDEVICE(INTEL, 0x0803), moorestown_1 },
	331	{ PCI_VDEVICE(INTEL, 0x0804), moorestown_2 },
	332	/* Medfield */
	333	{ PCI_VDEVICE(INTEL, 0x0817), medfield_3,},
	334	{ PCI_VDEVICE(INTEL, 0x0818), medfield_4 },
	335	{ PCI_VDEVICE(INTEL, 0x0819), medfield_5 },
	336	{ PCI_VDEVICE(INTEL, 0x082C), medfield_0 },
	337	{ PCI_VDEVICE(INTEL, 0x082D), medfield_1 },
	338	{ PCI_VDEVICE(INTEL, 0x082E), medfield_2 },
089c729a MW	339	/* Baytrail */
	340	{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
	341	{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
	342	{ PCI_VDEVICE(INTEL, 0x0F43), baytrail },
	343	{ PCI_VDEVICE(INTEL, 0x0F44), baytrail },
	344	{ PCI_VDEVICE(INTEL, 0x0F45), baytrail },
	345	{ PCI_VDEVICE(INTEL, 0x0F46), baytrail },
	346	{ PCI_VDEVICE(INTEL, 0x0F47), baytrail },
157a801e MW	347	/* Haswell */
	348	{ PCI_VDEVICE(INTEL, 0x9c61), haswell },
	349	{ PCI_VDEVICE(INTEL, 0x9c62), haswell },
0409516a AC	350	/* Braswell / Cherrytrail */
	351	{ PCI_VDEVICE(INTEL, 0x22C1), baytrail,},
	352	{ PCI_VDEVICE(INTEL, 0x22C2), baytrail },
	353	{ PCI_VDEVICE(INTEL, 0x22C3), baytrail },
	354	{ PCI_VDEVICE(INTEL, 0x22C4), baytrail },
	355	{ PCI_VDEVICE(INTEL, 0x22C5), baytrail },
	356	{ PCI_VDEVICE(INTEL, 0x22C6), baytrail },
	357	{ PCI_VDEVICE(INTEL, 0x22C7), baytrail },
fe20ff5c DB	358	{ 0,}
	359	};
	360	MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
	361
	362	static struct pci_driver dw_i2c_driver = {
	363	.name = DRIVER_NAME,
	364	.id_table = i2_designware_pci_ids,
	365	.probe = i2c_dw_pci_probe,
0b255e92	366	.remove = i2c_dw_pci_remove,
18dbdda8 DB	367	.driver = {
	368	.pm = &i2c_dw_pm_ops,
	369	},
fe20ff5c DB	370	};
fe20ff5c DB	371
56f21788	372	module_pci_driver(dw_i2c_driver);
fe20ff5c DB	373
	374	MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
	375	MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
	376	MODULE_LICENSE("GPL");