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1ab52cf9 | 1 | /* |
a0e06ea6 | 2 | * Synopsys DesignWare I2C adapter driver (master only). |
1ab52cf9 BS |
3 | * |
4 | * Based on the TI DAVINCI I2C adapter driver. | |
5 | * | |
6 | * Copyright (C) 2006 Texas Instruments. | |
7 | * Copyright (C) 2007 MontaVista Software Inc. | |
8 | * Copyright (C) 2009 Provigent Ltd. | |
9 | * | |
10 | * ---------------------------------------------------------------------------- | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * ---------------------------------------------------------------------------- | |
26 | * | |
27 | */ | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/i2c.h> | |
32 | #include <linux/clk.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/sched.h> | |
35 | #include <linux/err.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/io.h> | |
39 | ||
40 | /* | |
41 | * Registers offset | |
42 | */ | |
43 | #define DW_IC_CON 0x0 | |
44 | #define DW_IC_TAR 0x4 | |
45 | #define DW_IC_DATA_CMD 0x10 | |
46 | #define DW_IC_SS_SCL_HCNT 0x14 | |
47 | #define DW_IC_SS_SCL_LCNT 0x18 | |
48 | #define DW_IC_FS_SCL_HCNT 0x1c | |
49 | #define DW_IC_FS_SCL_LCNT 0x20 | |
50 | #define DW_IC_INTR_STAT 0x2c | |
51 | #define DW_IC_INTR_MASK 0x30 | |
e28000a3 | 52 | #define DW_IC_RAW_INTR_STAT 0x34 |
4cb6d1d6 SK |
53 | #define DW_IC_RX_TL 0x38 |
54 | #define DW_IC_TX_TL 0x3c | |
1ab52cf9 | 55 | #define DW_IC_CLR_INTR 0x40 |
e28000a3 SK |
56 | #define DW_IC_CLR_RX_UNDER 0x44 |
57 | #define DW_IC_CLR_RX_OVER 0x48 | |
58 | #define DW_IC_CLR_TX_OVER 0x4c | |
59 | #define DW_IC_CLR_RD_REQ 0x50 | |
60 | #define DW_IC_CLR_TX_ABRT 0x54 | |
61 | #define DW_IC_CLR_RX_DONE 0x58 | |
62 | #define DW_IC_CLR_ACTIVITY 0x5c | |
63 | #define DW_IC_CLR_STOP_DET 0x60 | |
64 | #define DW_IC_CLR_START_DET 0x64 | |
65 | #define DW_IC_CLR_GEN_CALL 0x68 | |
1ab52cf9 BS |
66 | #define DW_IC_ENABLE 0x6c |
67 | #define DW_IC_STATUS 0x70 | |
68 | #define DW_IC_TXFLR 0x74 | |
69 | #define DW_IC_RXFLR 0x78 | |
70 | #define DW_IC_COMP_PARAM_1 0xf4 | |
71 | #define DW_IC_TX_ABRT_SOURCE 0x80 | |
72 | ||
73 | #define DW_IC_CON_MASTER 0x1 | |
74 | #define DW_IC_CON_SPEED_STD 0x2 | |
75 | #define DW_IC_CON_SPEED_FAST 0x4 | |
76 | #define DW_IC_CON_10BITADDR_MASTER 0x10 | |
77 | #define DW_IC_CON_RESTART_EN 0x20 | |
78 | #define DW_IC_CON_SLAVE_DISABLE 0x40 | |
79 | ||
e28000a3 SK |
80 | #define DW_IC_INTR_RX_UNDER 0x001 |
81 | #define DW_IC_INTR_RX_OVER 0x002 | |
82 | #define DW_IC_INTR_RX_FULL 0x004 | |
83 | #define DW_IC_INTR_TX_OVER 0x008 | |
84 | #define DW_IC_INTR_TX_EMPTY 0x010 | |
85 | #define DW_IC_INTR_RD_REQ 0x020 | |
86 | #define DW_IC_INTR_TX_ABRT 0x040 | |
87 | #define DW_IC_INTR_RX_DONE 0x080 | |
88 | #define DW_IC_INTR_ACTIVITY 0x100 | |
1ab52cf9 | 89 | #define DW_IC_INTR_STOP_DET 0x200 |
e28000a3 SK |
90 | #define DW_IC_INTR_START_DET 0x400 |
91 | #define DW_IC_INTR_GEN_CALL 0x800 | |
1ab52cf9 | 92 | |
201d6a70 SK |
93 | #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ |
94 | DW_IC_INTR_TX_EMPTY | \ | |
95 | DW_IC_INTR_TX_ABRT | \ | |
96 | DW_IC_INTR_STOP_DET) | |
97 | ||
1ab52cf9 BS |
98 | #define DW_IC_STATUS_ACTIVITY 0x1 |
99 | ||
100 | #define DW_IC_ERR_TX_ABRT 0x1 | |
101 | ||
102 | /* | |
103 | * status codes | |
104 | */ | |
105 | #define STATUS_IDLE 0x0 | |
106 | #define STATUS_WRITE_IN_PROGRESS 0x1 | |
107 | #define STATUS_READ_IN_PROGRESS 0x2 | |
108 | ||
109 | #define TIMEOUT 20 /* ms */ | |
110 | ||
111 | /* | |
112 | * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register | |
113 | * | |
114 | * only expected abort codes are listed here | |
115 | * refer to the datasheet for the full list | |
116 | */ | |
117 | #define ABRT_7B_ADDR_NOACK 0 | |
118 | #define ABRT_10ADDR1_NOACK 1 | |
119 | #define ABRT_10ADDR2_NOACK 2 | |
120 | #define ABRT_TXDATA_NOACK 3 | |
121 | #define ABRT_GCALL_NOACK 4 | |
122 | #define ABRT_GCALL_READ 5 | |
123 | #define ABRT_SBYTE_ACKDET 7 | |
124 | #define ABRT_SBYTE_NORSTRT 9 | |
125 | #define ABRT_10B_RD_NORSTRT 10 | |
ce6eb574 | 126 | #define ABRT_MASTER_DIS 11 |
1ab52cf9 BS |
127 | #define ARB_LOST 12 |
128 | ||
ce6eb574 SK |
129 | #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) |
130 | #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) | |
131 | #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) | |
132 | #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) | |
133 | #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) | |
134 | #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) | |
135 | #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) | |
136 | #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) | |
137 | #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) | |
138 | #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) | |
139 | #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) | |
140 | ||
141 | #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ | |
142 | DW_IC_TX_ABRT_10ADDR1_NOACK | \ | |
143 | DW_IC_TX_ABRT_10ADDR2_NOACK | \ | |
144 | DW_IC_TX_ABRT_TXDATA_NOACK | \ | |
145 | DW_IC_TX_ABRT_GCALL_NOACK) | |
146 | ||
1ab52cf9 | 147 | static char *abort_sources[] = { |
a0e06ea6 | 148 | [ABRT_7B_ADDR_NOACK] = |
1ab52cf9 | 149 | "slave address not acknowledged (7bit mode)", |
a0e06ea6 | 150 | [ABRT_10ADDR1_NOACK] = |
1ab52cf9 | 151 | "first address byte not acknowledged (10bit mode)", |
a0e06ea6 | 152 | [ABRT_10ADDR2_NOACK] = |
1ab52cf9 | 153 | "second address byte not acknowledged (10bit mode)", |
a0e06ea6 | 154 | [ABRT_TXDATA_NOACK] = |
1ab52cf9 | 155 | "data not acknowledged", |
a0e06ea6 | 156 | [ABRT_GCALL_NOACK] = |
1ab52cf9 | 157 | "no acknowledgement for a general call", |
a0e06ea6 | 158 | [ABRT_GCALL_READ] = |
1ab52cf9 | 159 | "read after general call", |
a0e06ea6 | 160 | [ABRT_SBYTE_ACKDET] = |
1ab52cf9 | 161 | "start byte acknowledged", |
a0e06ea6 | 162 | [ABRT_SBYTE_NORSTRT] = |
1ab52cf9 | 163 | "trying to send start byte when restart is disabled", |
a0e06ea6 | 164 | [ABRT_10B_RD_NORSTRT] = |
1ab52cf9 | 165 | "trying to read when restart is disabled (10bit mode)", |
a0e06ea6 | 166 | [ABRT_MASTER_DIS] = |
1ab52cf9 | 167 | "trying to use disabled adapter", |
a0e06ea6 | 168 | [ARB_LOST] = |
1ab52cf9 BS |
169 | "lost arbitration", |
170 | }; | |
171 | ||
172 | /** | |
173 | * struct dw_i2c_dev - private i2c-designware data | |
174 | * @dev: driver model device node | |
175 | * @base: IO registers pointer | |
176 | * @cmd_complete: tx completion indicator | |
1ab52cf9 BS |
177 | * @lock: protect this struct and IO registers |
178 | * @clk: input reference clock | |
179 | * @cmd_err: run time hadware error code | |
180 | * @msgs: points to an array of messages currently being transfered | |
181 | * @msgs_num: the number of elements in msgs | |
182 | * @msg_write_idx: the element index of the current tx message in the msgs | |
183 | * array | |
184 | * @tx_buf_len: the length of the current tx buffer | |
185 | * @tx_buf: the current tx buffer | |
186 | * @msg_read_idx: the element index of the current rx message in the msgs | |
187 | * array | |
188 | * @rx_buf_len: the length of the current rx buffer | |
189 | * @rx_buf: the current rx buffer | |
190 | * @msg_err: error status of the current transfer | |
191 | * @status: i2c master status, one of STATUS_* | |
192 | * @abort_source: copy of the TX_ABRT_SOURCE register | |
193 | * @irq: interrupt number for the i2c master | |
194 | * @adapter: i2c subsystem adapter node | |
195 | * @tx_fifo_depth: depth of the hardware tx fifo | |
196 | * @rx_fifo_depth: depth of the hardware rx fifo | |
197 | */ | |
198 | struct dw_i2c_dev { | |
199 | struct device *dev; | |
200 | void __iomem *base; | |
201 | struct completion cmd_complete; | |
1ab52cf9 BS |
202 | struct mutex lock; |
203 | struct clk *clk; | |
204 | int cmd_err; | |
205 | struct i2c_msg *msgs; | |
206 | int msgs_num; | |
207 | int msg_write_idx; | |
ed5e1dd5 | 208 | u32 tx_buf_len; |
1ab52cf9 BS |
209 | u8 *tx_buf; |
210 | int msg_read_idx; | |
ed5e1dd5 | 211 | u32 rx_buf_len; |
1ab52cf9 BS |
212 | u8 *rx_buf; |
213 | int msg_err; | |
214 | unsigned int status; | |
ed5e1dd5 | 215 | u32 abort_source; |
1ab52cf9 BS |
216 | int irq; |
217 | struct i2c_adapter adapter; | |
218 | unsigned int tx_fifo_depth; | |
219 | unsigned int rx_fifo_depth; | |
220 | }; | |
221 | ||
d60c7e81 SK |
222 | static u32 |
223 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) | |
224 | { | |
225 | /* | |
226 | * DesignWare I2C core doesn't seem to have solid strategy to meet | |
227 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec | |
228 | * will result in violation of the tHD;STA spec. | |
229 | */ | |
230 | if (cond) | |
231 | /* | |
232 | * Conditional expression: | |
233 | * | |
234 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH | |
235 | * | |
236 | * This is based on the DW manuals, and represents an ideal | |
237 | * configuration. The resulting I2C bus speed will be | |
238 | * faster than any of the others. | |
239 | * | |
240 | * If your hardware is free from tHD;STA issue, try this one. | |
241 | */ | |
242 | return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset; | |
243 | else | |
244 | /* | |
245 | * Conditional expression: | |
246 | * | |
247 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) | |
248 | * | |
249 | * This is just experimental rule; the tHD;STA period turned | |
250 | * out to be proportinal to (_HCNT + 3). With this setting, | |
251 | * we could meet both tHIGH and tHD;STA timing specs. | |
252 | * | |
253 | * If unsure, you'd better to take this alternative. | |
254 | * | |
255 | * The reason why we need to take into account "tf" here, | |
256 | * is the same as described in i2c_dw_scl_lcnt(). | |
257 | */ | |
258 | return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset; | |
259 | } | |
260 | ||
261 | static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) | |
262 | { | |
263 | /* | |
264 | * Conditional expression: | |
265 | * | |
266 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) | |
267 | * | |
268 | * DW I2C core starts counting the SCL CNTs for the LOW period | |
269 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. | |
270 | * In order to meet the tLOW timing spec, we need to take into | |
271 | * account the fall time of SCL signal (tf). Default tf value | |
272 | * should be 0.3 us, for safety. | |
273 | */ | |
274 | return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset; | |
275 | } | |
276 | ||
1ab52cf9 BS |
277 | /** |
278 | * i2c_dw_init() - initialize the designware i2c master hardware | |
279 | * @dev: device private data | |
280 | * | |
281 | * This functions configures and enables the I2C master. | |
282 | * This function is called during I2C init function, and in case of timeout at | |
283 | * run time. | |
284 | */ | |
285 | static void i2c_dw_init(struct dw_i2c_dev *dev) | |
286 | { | |
287 | u32 input_clock_khz = clk_get_rate(dev->clk) / 1000; | |
d60c7e81 | 288 | u32 ic_con, hcnt, lcnt; |
1ab52cf9 BS |
289 | |
290 | /* Disable the adapter */ | |
ed5e1dd5 | 291 | writel(0, dev->base + DW_IC_ENABLE); |
1ab52cf9 BS |
292 | |
293 | /* set standard and fast speed deviders for high/low periods */ | |
d60c7e81 SK |
294 | |
295 | /* Standard-mode */ | |
296 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
297 | 40, /* tHD;STA = tHIGH = 4.0 us */ | |
298 | 3, /* tf = 0.3 us */ | |
299 | 0, /* 0: DW default, 1: Ideal */ | |
300 | 0); /* No offset */ | |
301 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
302 | 47, /* tLOW = 4.7 us */ | |
303 | 3, /* tf = 0.3 us */ | |
304 | 0); /* No offset */ | |
305 | writel(hcnt, dev->base + DW_IC_SS_SCL_HCNT); | |
306 | writel(lcnt, dev->base + DW_IC_SS_SCL_LCNT); | |
307 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); | |
308 | ||
309 | /* Fast-mode */ | |
310 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
311 | 6, /* tHD;STA = tHIGH = 0.6 us */ | |
312 | 3, /* tf = 0.3 us */ | |
313 | 0, /* 0: DW default, 1: Ideal */ | |
314 | 0); /* No offset */ | |
315 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
316 | 13, /* tLOW = 1.3 us */ | |
317 | 3, /* tf = 0.3 us */ | |
318 | 0); /* No offset */ | |
319 | writel(hcnt, dev->base + DW_IC_FS_SCL_HCNT); | |
320 | writel(lcnt, dev->base + DW_IC_FS_SCL_LCNT); | |
321 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); | |
1ab52cf9 | 322 | |
4cb6d1d6 SK |
323 | /* Configure Tx/Rx FIFO threshold levels */ |
324 | writel(dev->tx_fifo_depth - 1, dev->base + DW_IC_TX_TL); | |
325 | writel(0, dev->base + DW_IC_RX_TL); | |
326 | ||
1ab52cf9 BS |
327 | /* configure the i2c master */ |
328 | ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | | |
329 | DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST; | |
ed5e1dd5 | 330 | writel(ic_con, dev->base + DW_IC_CON); |
1ab52cf9 BS |
331 | } |
332 | ||
333 | /* | |
334 | * Waiting for bus not busy | |
335 | */ | |
336 | static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) | |
337 | { | |
338 | int timeout = TIMEOUT; | |
339 | ||
ed5e1dd5 | 340 | while (readl(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
1ab52cf9 BS |
341 | if (timeout <= 0) { |
342 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
343 | return -ETIMEDOUT; | |
344 | } | |
345 | timeout--; | |
346 | mdelay(1); | |
347 | } | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
81e798b7 SK |
352 | static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) |
353 | { | |
354 | struct i2c_msg *msgs = dev->msgs; | |
355 | u32 ic_con; | |
356 | ||
357 | /* Disable the adapter */ | |
358 | writel(0, dev->base + DW_IC_ENABLE); | |
359 | ||
360 | /* set the slave (target) address */ | |
361 | writel(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR); | |
362 | ||
363 | /* if the slave address is ten bit address, enable 10BITADDR */ | |
364 | ic_con = readl(dev->base + DW_IC_CON); | |
365 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) | |
366 | ic_con |= DW_IC_CON_10BITADDR_MASTER; | |
367 | else | |
368 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; | |
369 | writel(ic_con, dev->base + DW_IC_CON); | |
370 | ||
371 | /* Enable the adapter */ | |
372 | writel(1, dev->base + DW_IC_ENABLE); | |
201d6a70 SK |
373 | |
374 | /* Enable interrupts */ | |
375 | writel(DW_IC_INTR_DEFAULT_MASK, dev->base + DW_IC_INTR_MASK); | |
81e798b7 SK |
376 | } |
377 | ||
1ab52cf9 | 378 | /* |
201d6a70 SK |
379 | * Initiate (and continue) low level master read/write transaction. |
380 | * This function is only called from i2c_dw_isr, and pumping i2c_msg | |
381 | * messages into the tx buffer. Even if the size of i2c_msg data is | |
382 | * longer than the size of the tx buffer, it handles everything. | |
1ab52cf9 BS |
383 | */ |
384 | static void | |
e77cf232 | 385 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
1ab52cf9 | 386 | { |
1ab52cf9 | 387 | struct i2c_msg *msgs = dev->msgs; |
81e798b7 | 388 | u32 intr_mask; |
ae72222d | 389 | int tx_limit, rx_limit; |
ed5e1dd5 SK |
390 | u32 addr = msgs[dev->msg_write_idx].addr; |
391 | u32 buf_len = dev->tx_buf_len; | |
26ea15b1 | 392 | u8 *buf = dev->tx_buf;; |
1ab52cf9 | 393 | |
201d6a70 | 394 | intr_mask = DW_IC_INTR_DEFAULT_MASK; |
c70c5cd3 | 395 | |
6d2ea487 | 396 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
a0e06ea6 SK |
397 | /* |
398 | * if target address has changed, we need to | |
1ab52cf9 BS |
399 | * reprogram the target address in the i2c |
400 | * adapter when we are done with this transfer | |
401 | */ | |
8f588e40 SK |
402 | if (msgs[dev->msg_write_idx].addr != addr) { |
403 | dev_err(dev->dev, | |
404 | "%s: invalid target address\n", __func__); | |
405 | dev->msg_err = -EINVAL; | |
406 | break; | |
407 | } | |
1ab52cf9 BS |
408 | |
409 | if (msgs[dev->msg_write_idx].len == 0) { | |
410 | dev_err(dev->dev, | |
411 | "%s: invalid message length\n", __func__); | |
412 | dev->msg_err = -EINVAL; | |
8f588e40 | 413 | break; |
1ab52cf9 BS |
414 | } |
415 | ||
416 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { | |
417 | /* new i2c_msg */ | |
26ea15b1 | 418 | buf = msgs[dev->msg_write_idx].buf; |
1ab52cf9 BS |
419 | buf_len = msgs[dev->msg_write_idx].len; |
420 | } | |
421 | ||
ae72222d SK |
422 | tx_limit = dev->tx_fifo_depth - readl(dev->base + DW_IC_TXFLR); |
423 | rx_limit = dev->rx_fifo_depth - readl(dev->base + DW_IC_RXFLR); | |
424 | ||
1ab52cf9 BS |
425 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { |
426 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { | |
ed5e1dd5 | 427 | writel(0x100, dev->base + DW_IC_DATA_CMD); |
1ab52cf9 BS |
428 | rx_limit--; |
429 | } else | |
26ea15b1 | 430 | writel(*buf++, dev->base + DW_IC_DATA_CMD); |
1ab52cf9 BS |
431 | tx_limit--; buf_len--; |
432 | } | |
c70c5cd3 | 433 | |
26ea15b1 | 434 | dev->tx_buf = buf; |
c70c5cd3 SK |
435 | dev->tx_buf_len = buf_len; |
436 | ||
437 | if (buf_len > 0) { | |
438 | /* more bytes to be written */ | |
c70c5cd3 SK |
439 | dev->status |= STATUS_WRITE_IN_PROGRESS; |
440 | break; | |
69151e53 | 441 | } else |
c70c5cd3 | 442 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; |
1ab52cf9 BS |
443 | } |
444 | ||
69151e53 SK |
445 | /* |
446 | * If i2c_msg index search is completed, we don't need TX_EMPTY | |
447 | * interrupt any more. | |
448 | */ | |
449 | if (dev->msg_write_idx == dev->msgs_num) | |
450 | intr_mask &= ~DW_IC_INTR_TX_EMPTY; | |
451 | ||
8f588e40 SK |
452 | if (dev->msg_err) |
453 | intr_mask = 0; | |
454 | ||
ed5e1dd5 | 455 | writel(intr_mask, dev->base + DW_IC_INTR_MASK); |
1ab52cf9 BS |
456 | } |
457 | ||
458 | static void | |
78839bd0 | 459 | i2c_dw_read(struct dw_i2c_dev *dev) |
1ab52cf9 | 460 | { |
1ab52cf9 | 461 | struct i2c_msg *msgs = dev->msgs; |
ae72222d | 462 | int rx_valid; |
1ab52cf9 | 463 | |
6d2ea487 | 464 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
ed5e1dd5 | 465 | u32 len; |
1ab52cf9 BS |
466 | u8 *buf; |
467 | ||
468 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) | |
469 | continue; | |
470 | ||
1ab52cf9 BS |
471 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { |
472 | len = msgs[dev->msg_read_idx].len; | |
473 | buf = msgs[dev->msg_read_idx].buf; | |
474 | } else { | |
475 | len = dev->rx_buf_len; | |
476 | buf = dev->rx_buf; | |
477 | } | |
478 | ||
ae72222d SK |
479 | rx_valid = readl(dev->base + DW_IC_RXFLR); |
480 | ||
1ab52cf9 | 481 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) |
ed5e1dd5 | 482 | *buf++ = readl(dev->base + DW_IC_DATA_CMD); |
1ab52cf9 BS |
483 | |
484 | if (len > 0) { | |
485 | dev->status |= STATUS_READ_IN_PROGRESS; | |
486 | dev->rx_buf_len = len; | |
487 | dev->rx_buf = buf; | |
488 | return; | |
489 | } else | |
490 | dev->status &= ~STATUS_READ_IN_PROGRESS; | |
491 | } | |
492 | } | |
493 | ||
ce6eb574 SK |
494 | static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) |
495 | { | |
496 | unsigned long abort_source = dev->abort_source; | |
497 | int i; | |
498 | ||
6d1ea0f6 | 499 | if (abort_source & DW_IC_TX_ABRT_NOACK) { |
984b3f57 | 500 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
6d1ea0f6 SK |
501 | dev_dbg(dev->dev, |
502 | "%s: %s\n", __func__, abort_sources[i]); | |
503 | return -EREMOTEIO; | |
504 | } | |
505 | ||
984b3f57 | 506 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
ce6eb574 SK |
507 | dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); |
508 | ||
509 | if (abort_source & DW_IC_TX_ARB_LOST) | |
510 | return -EAGAIN; | |
ce6eb574 SK |
511 | else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) |
512 | return -EINVAL; /* wrong msgs[] data */ | |
513 | else | |
514 | return -EIO; | |
515 | } | |
516 | ||
1ab52cf9 BS |
517 | /* |
518 | * Prepare controller for a transaction and call i2c_dw_xfer_msg | |
519 | */ | |
520 | static int | |
521 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
522 | { | |
523 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); | |
524 | int ret; | |
525 | ||
526 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); | |
527 | ||
528 | mutex_lock(&dev->lock); | |
529 | ||
530 | INIT_COMPLETION(dev->cmd_complete); | |
531 | dev->msgs = msgs; | |
532 | dev->msgs_num = num; | |
533 | dev->cmd_err = 0; | |
534 | dev->msg_write_idx = 0; | |
535 | dev->msg_read_idx = 0; | |
536 | dev->msg_err = 0; | |
537 | dev->status = STATUS_IDLE; | |
ce6eb574 | 538 | dev->abort_source = 0; |
1ab52cf9 BS |
539 | |
540 | ret = i2c_dw_wait_bus_not_busy(dev); | |
541 | if (ret < 0) | |
542 | goto done; | |
543 | ||
544 | /* start the transfers */ | |
81e798b7 | 545 | i2c_dw_xfer_init(dev); |
1ab52cf9 BS |
546 | |
547 | /* wait for tx to complete */ | |
548 | ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ); | |
549 | if (ret == 0) { | |
550 | dev_err(dev->dev, "controller timed out\n"); | |
551 | i2c_dw_init(dev); | |
552 | ret = -ETIMEDOUT; | |
553 | goto done; | |
554 | } else if (ret < 0) | |
555 | goto done; | |
556 | ||
557 | if (dev->msg_err) { | |
558 | ret = dev->msg_err; | |
559 | goto done; | |
560 | } | |
561 | ||
562 | /* no error */ | |
563 | if (likely(!dev->cmd_err)) { | |
07745399 | 564 | /* Disable the adapter */ |
ed5e1dd5 | 565 | writel(0, dev->base + DW_IC_ENABLE); |
1ab52cf9 BS |
566 | ret = num; |
567 | goto done; | |
568 | } | |
569 | ||
570 | /* We have an error */ | |
571 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { | |
ce6eb574 SK |
572 | ret = i2c_dw_handle_tx_abort(dev); |
573 | goto done; | |
1ab52cf9 BS |
574 | } |
575 | ret = -EIO; | |
576 | ||
577 | done: | |
578 | mutex_unlock(&dev->lock); | |
579 | ||
580 | return ret; | |
581 | } | |
582 | ||
583 | static u32 i2c_dw_func(struct i2c_adapter *adap) | |
584 | { | |
52d7e430 SK |
585 | return I2C_FUNC_I2C | |
586 | I2C_FUNC_10BIT_ADDR | | |
587 | I2C_FUNC_SMBUS_BYTE | | |
588 | I2C_FUNC_SMBUS_BYTE_DATA | | |
589 | I2C_FUNC_SMBUS_WORD_DATA | | |
590 | I2C_FUNC_SMBUS_I2C_BLOCK; | |
1ab52cf9 BS |
591 | } |
592 | ||
e28000a3 SK |
593 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
594 | { | |
595 | u32 stat; | |
596 | ||
597 | /* | |
598 | * The IC_INTR_STAT register just indicates "enabled" interrupts. | |
599 | * Ths unmasked raw version of interrupt status bits are available | |
600 | * in the IC_RAW_INTR_STAT register. | |
601 | * | |
602 | * That is, | |
603 | * stat = readl(IC_INTR_STAT); | |
604 | * equals to, | |
605 | * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK); | |
606 | * | |
607 | * The raw version might be useful for debugging purposes. | |
608 | */ | |
609 | stat = readl(dev->base + DW_IC_INTR_STAT); | |
610 | ||
611 | /* | |
612 | * Do not use the IC_CLR_INTR register to clear interrupts, or | |
613 | * you'll miss some interrupts, triggered during the period from | |
614 | * readl(IC_INTR_STAT) to readl(IC_CLR_INTR). | |
615 | * | |
616 | * Instead, use the separately-prepared IC_CLR_* registers. | |
617 | */ | |
618 | if (stat & DW_IC_INTR_RX_UNDER) | |
619 | readl(dev->base + DW_IC_CLR_RX_UNDER); | |
620 | if (stat & DW_IC_INTR_RX_OVER) | |
621 | readl(dev->base + DW_IC_CLR_RX_OVER); | |
622 | if (stat & DW_IC_INTR_TX_OVER) | |
623 | readl(dev->base + DW_IC_CLR_TX_OVER); | |
624 | if (stat & DW_IC_INTR_RD_REQ) | |
625 | readl(dev->base + DW_IC_CLR_RD_REQ); | |
626 | if (stat & DW_IC_INTR_TX_ABRT) { | |
627 | /* | |
628 | * The IC_TX_ABRT_SOURCE register is cleared whenever | |
629 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. | |
630 | */ | |
631 | dev->abort_source = readl(dev->base + DW_IC_TX_ABRT_SOURCE); | |
632 | readl(dev->base + DW_IC_CLR_TX_ABRT); | |
633 | } | |
634 | if (stat & DW_IC_INTR_RX_DONE) | |
635 | readl(dev->base + DW_IC_CLR_RX_DONE); | |
636 | if (stat & DW_IC_INTR_ACTIVITY) | |
637 | readl(dev->base + DW_IC_CLR_ACTIVITY); | |
638 | if (stat & DW_IC_INTR_STOP_DET) | |
639 | readl(dev->base + DW_IC_CLR_STOP_DET); | |
640 | if (stat & DW_IC_INTR_START_DET) | |
641 | readl(dev->base + DW_IC_CLR_START_DET); | |
642 | if (stat & DW_IC_INTR_GEN_CALL) | |
643 | readl(dev->base + DW_IC_CLR_GEN_CALL); | |
644 | ||
645 | return stat; | |
646 | } | |
647 | ||
1ab52cf9 BS |
648 | /* |
649 | * Interrupt service routine. This gets called whenever an I2C interrupt | |
650 | * occurs. | |
651 | */ | |
652 | static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) | |
653 | { | |
654 | struct dw_i2c_dev *dev = dev_id; | |
ed5e1dd5 | 655 | u32 stat; |
1ab52cf9 | 656 | |
e28000a3 | 657 | stat = i2c_dw_read_clear_intrbits(dev); |
1ab52cf9 | 658 | dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat); |
e28000a3 | 659 | |
1ab52cf9 | 660 | if (stat & DW_IC_INTR_TX_ABRT) { |
1ab52cf9 BS |
661 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
662 | dev->status = STATUS_IDLE; | |
597fe310 SK |
663 | |
664 | /* | |
665 | * Anytime TX_ABRT is set, the contents of the tx/rx | |
666 | * buffers are flushed. Make sure to skip them. | |
667 | */ | |
668 | writel(0, dev->base + DW_IC_INTR_MASK); | |
669 | goto tx_aborted; | |
07745399 SK |
670 | } |
671 | ||
21a89d41 | 672 | if (stat & DW_IC_INTR_RX_FULL) |
07745399 | 673 | i2c_dw_read(dev); |
21a89d41 SK |
674 | |
675 | if (stat & DW_IC_INTR_TX_EMPTY) | |
07745399 | 676 | i2c_dw_xfer_msg(dev); |
07745399 SK |
677 | |
678 | /* | |
679 | * No need to modify or disable the interrupt mask here. | |
680 | * i2c_dw_xfer_msg() will take care of it according to | |
681 | * the current transmit status. | |
682 | */ | |
1ab52cf9 | 683 | |
597fe310 | 684 | tx_aborted: |
8f588e40 | 685 | if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) |
1ab52cf9 BS |
686 | complete(&dev->cmd_complete); |
687 | ||
688 | return IRQ_HANDLED; | |
689 | } | |
690 | ||
691 | static struct i2c_algorithm i2c_dw_algo = { | |
692 | .master_xfer = i2c_dw_xfer, | |
693 | .functionality = i2c_dw_func, | |
694 | }; | |
695 | ||
696 | static int __devinit dw_i2c_probe(struct platform_device *pdev) | |
697 | { | |
698 | struct dw_i2c_dev *dev; | |
699 | struct i2c_adapter *adap; | |
91b52cae SK |
700 | struct resource *mem, *ioarea; |
701 | int irq, r; | |
1ab52cf9 BS |
702 | |
703 | /* NOTE: driver uses the static register mapping */ | |
704 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
705 | if (!mem) { | |
706 | dev_err(&pdev->dev, "no mem resource?\n"); | |
707 | return -EINVAL; | |
708 | } | |
709 | ||
91b52cae SK |
710 | irq = platform_get_irq(pdev, 0); |
711 | if (irq < 0) { | |
1ab52cf9 | 712 | dev_err(&pdev->dev, "no irq resource?\n"); |
91b52cae | 713 | return irq; /* -ENXIO */ |
1ab52cf9 BS |
714 | } |
715 | ||
716 | ioarea = request_mem_region(mem->start, resource_size(mem), | |
717 | pdev->name); | |
718 | if (!ioarea) { | |
719 | dev_err(&pdev->dev, "I2C region already claimed\n"); | |
720 | return -EBUSY; | |
721 | } | |
722 | ||
723 | dev = kzalloc(sizeof(struct dw_i2c_dev), GFP_KERNEL); | |
724 | if (!dev) { | |
725 | r = -ENOMEM; | |
726 | goto err_release_region; | |
727 | } | |
728 | ||
729 | init_completion(&dev->cmd_complete); | |
1ab52cf9 BS |
730 | mutex_init(&dev->lock); |
731 | dev->dev = get_device(&pdev->dev); | |
91b52cae | 732 | dev->irq = irq; |
1ab52cf9 BS |
733 | platform_set_drvdata(pdev, dev); |
734 | ||
735 | dev->clk = clk_get(&pdev->dev, NULL); | |
736 | if (IS_ERR(dev->clk)) { | |
737 | r = -ENODEV; | |
738 | goto err_free_mem; | |
739 | } | |
740 | clk_enable(dev->clk); | |
741 | ||
742 | dev->base = ioremap(mem->start, resource_size(mem)); | |
743 | if (dev->base == NULL) { | |
744 | dev_err(&pdev->dev, "failure mapping io resources\n"); | |
745 | r = -EBUSY; | |
746 | goto err_unuse_clocks; | |
747 | } | |
748 | { | |
749 | u32 param1 = readl(dev->base + DW_IC_COMP_PARAM_1); | |
750 | ||
751 | dev->tx_fifo_depth = ((param1 >> 16) & 0xff) + 1; | |
752 | dev->rx_fifo_depth = ((param1 >> 8) & 0xff) + 1; | |
753 | } | |
754 | i2c_dw_init(dev); | |
755 | ||
ed5e1dd5 | 756 | writel(0, dev->base + DW_IC_INTR_MASK); /* disable IRQ */ |
201d6a70 | 757 | r = request_irq(dev->irq, i2c_dw_isr, IRQF_DISABLED, pdev->name, dev); |
1ab52cf9 BS |
758 | if (r) { |
759 | dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); | |
760 | goto err_iounmap; | |
761 | } | |
762 | ||
763 | adap = &dev->adapter; | |
764 | i2c_set_adapdata(adap, dev); | |
765 | adap->owner = THIS_MODULE; | |
766 | adap->class = I2C_CLASS_HWMON; | |
767 | strlcpy(adap->name, "Synopsys DesignWare I2C adapter", | |
768 | sizeof(adap->name)); | |
769 | adap->algo = &i2c_dw_algo; | |
770 | adap->dev.parent = &pdev->dev; | |
771 | ||
772 | adap->nr = pdev->id; | |
773 | r = i2c_add_numbered_adapter(adap); | |
774 | if (r) { | |
775 | dev_err(&pdev->dev, "failure adding adapter\n"); | |
776 | goto err_free_irq; | |
777 | } | |
778 | ||
779 | return 0; | |
780 | ||
781 | err_free_irq: | |
782 | free_irq(dev->irq, dev); | |
783 | err_iounmap: | |
784 | iounmap(dev->base); | |
785 | err_unuse_clocks: | |
786 | clk_disable(dev->clk); | |
787 | clk_put(dev->clk); | |
788 | dev->clk = NULL; | |
789 | err_free_mem: | |
790 | platform_set_drvdata(pdev, NULL); | |
791 | put_device(&pdev->dev); | |
792 | kfree(dev); | |
793 | err_release_region: | |
794 | release_mem_region(mem->start, resource_size(mem)); | |
795 | ||
796 | return r; | |
797 | } | |
798 | ||
799 | static int __devexit dw_i2c_remove(struct platform_device *pdev) | |
800 | { | |
801 | struct dw_i2c_dev *dev = platform_get_drvdata(pdev); | |
802 | struct resource *mem; | |
803 | ||
804 | platform_set_drvdata(pdev, NULL); | |
805 | i2c_del_adapter(&dev->adapter); | |
806 | put_device(&pdev->dev); | |
807 | ||
808 | clk_disable(dev->clk); | |
809 | clk_put(dev->clk); | |
810 | dev->clk = NULL; | |
811 | ||
ed5e1dd5 | 812 | writel(0, dev->base + DW_IC_ENABLE); |
1ab52cf9 BS |
813 | free_irq(dev->irq, dev); |
814 | kfree(dev); | |
815 | ||
816 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
817 | release_mem_region(mem->start, resource_size(mem)); | |
818 | return 0; | |
819 | } | |
820 | ||
821 | /* work with hotplug and coldplug */ | |
822 | MODULE_ALIAS("platform:i2c_designware"); | |
823 | ||
824 | static struct platform_driver dw_i2c_driver = { | |
825 | .remove = __devexit_p(dw_i2c_remove), | |
826 | .driver = { | |
827 | .name = "i2c_designware", | |
828 | .owner = THIS_MODULE, | |
829 | }, | |
830 | }; | |
831 | ||
832 | static int __init dw_i2c_init_driver(void) | |
833 | { | |
834 | return platform_driver_probe(&dw_i2c_driver, dw_i2c_probe); | |
835 | } | |
836 | module_init(dw_i2c_init_driver); | |
837 | ||
838 | static void __exit dw_i2c_exit_driver(void) | |
839 | { | |
840 | platform_driver_unregister(&dw_i2c_driver); | |
841 | } | |
842 | module_exit(dw_i2c_exit_driver); | |
843 | ||
844 | MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>"); | |
845 | MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter"); | |
846 | MODULE_LICENSE("GPL"); |