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e9bc8fa5 | 1 | /* |
8956dc10 | 2 | * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. |
e9bc8fa5 TM |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; version 2 of the License. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/delay.h> | |
e9bc8fa5 TM |
21 | #include <linux/errno.h> |
22 | #include <linux/i2c.h> | |
23 | #include <linux/fs.h> | |
24 | #include <linux/io.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/jiffies.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/mutex.h> | |
30 | #include <linux/ktime.h> | |
6dbc2f35 | 31 | #include <linux/slab.h> |
e9bc8fa5 TM |
32 | |
33 | #define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */ | |
34 | #define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */ | |
35 | #define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */ | |
36 | #define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */ | |
37 | #define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */ | |
38 | ||
39 | #define PCH_I2CSADR 0x00 /* I2C slave address register */ | |
40 | #define PCH_I2CCTL 0x04 /* I2C control register */ | |
41 | #define PCH_I2CSR 0x08 /* I2C status register */ | |
42 | #define PCH_I2CDR 0x0C /* I2C data register */ | |
43 | #define PCH_I2CMON 0x10 /* I2C bus monitor register */ | |
44 | #define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */ | |
45 | #define PCH_I2CMOD 0x18 /* I2C mode register */ | |
46 | #define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */ | |
47 | #define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */ | |
48 | #define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */ | |
49 | #define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */ | |
50 | #define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */ | |
51 | #define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */ | |
52 | #define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */ | |
53 | #define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */ | |
54 | #define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */ | |
55 | #define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */ | |
56 | #define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */ | |
57 | #define PCH_I2CTMR 0x48 /* I2C timer register */ | |
58 | #define PCH_I2CSRST 0xFC /* I2C reset register */ | |
59 | #define PCH_I2CNF 0xF8 /* I2C noise filter register */ | |
60 | ||
61 | #define BUS_IDLE_TIMEOUT 20 | |
62 | #define PCH_I2CCTL_I2CMEN 0x0080 | |
63 | #define TEN_BIT_ADDR_DEFAULT 0xF000 | |
64 | #define TEN_BIT_ADDR_MASK 0xF0 | |
65 | #define PCH_START 0x0020 | |
c249ac20 | 66 | #define PCH_RESTART 0x0004 |
e9bc8fa5 TM |
67 | #define PCH_ESR_START 0x0001 |
68 | #define PCH_BUFF_START 0x1 | |
69 | #define PCH_REPSTART 0x0004 | |
70 | #define PCH_ACK 0x0008 | |
71 | #define PCH_GETACK 0x0001 | |
72 | #define CLR_REG 0x0 | |
73 | #define I2C_RD 0x1 | |
74 | #define I2CMCF_BIT 0x0080 | |
75 | #define I2CMIF_BIT 0x0002 | |
76 | #define I2CMAL_BIT 0x0010 | |
77 | #define I2CBMFI_BIT 0x0001 | |
78 | #define I2CBMAL_BIT 0x0002 | |
79 | #define I2CBMNA_BIT 0x0004 | |
80 | #define I2CBMTO_BIT 0x0008 | |
81 | #define I2CBMIS_BIT 0x0010 | |
82 | #define I2CESRFI_BIT 0X0001 | |
83 | #define I2CESRTO_BIT 0x0002 | |
84 | #define I2CESRFIIE_BIT 0x1 | |
85 | #define I2CESRTOIE_BIT 0x2 | |
86 | #define I2CBMDZ_BIT 0x0040 | |
87 | #define I2CBMAG_BIT 0x0020 | |
88 | #define I2CMBB_BIT 0x0020 | |
89 | #define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \ | |
90 | I2CBMTO_BIT | I2CBMIS_BIT) | |
91 | #define I2C_ADDR_MSK 0xFF | |
92 | #define I2C_MSB_2B_MSK 0x300 | |
93 | #define FAST_MODE_CLK 400 | |
94 | #define FAST_MODE_EN 0x0001 | |
95 | #define SUB_ADDR_LEN_MAX 4 | |
96 | #define BUF_LEN_MAX 32 | |
97 | #define PCH_BUFFER_MODE 0x1 | |
98 | #define EEPROM_SW_RST_MODE 0x0002 | |
99 | #define NORMAL_INTR_ENBL 0x0300 | |
100 | #define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT) | |
101 | #define EEPROM_RST_INTR_DISBL 0x0 | |
102 | #define BUFFER_MODE_INTR_ENBL 0x001F | |
103 | #define BUFFER_MODE_INTR_DISBL 0x0 | |
104 | #define NORMAL_MODE 0x0 | |
105 | #define BUFFER_MODE 0x1 | |
106 | #define EEPROM_SR_MODE 0x2 | |
107 | #define I2C_TX_MODE 0x0010 | |
108 | #define PCH_BUF_TX 0xFFF7 | |
109 | #define PCH_BUF_RD 0x0008 | |
110 | #define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \ | |
111 | I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT) | |
112 | #define I2CMAL_EVENT 0x0001 | |
113 | #define I2CMCF_EVENT 0x0002 | |
114 | #define I2CBMFI_EVENT 0x0004 | |
115 | #define I2CBMAL_EVENT 0x0008 | |
116 | #define I2CBMNA_EVENT 0x0010 | |
117 | #define I2CBMTO_EVENT 0x0020 | |
118 | #define I2CBMIS_EVENT 0x0040 | |
119 | #define I2CESRFI_EVENT 0x0080 | |
120 | #define I2CESRTO_EVENT 0x0100 | |
121 | #define PCI_DEVICE_ID_PCH_I2C 0x8817 | |
122 | ||
123 | #define pch_dbg(adap, fmt, arg...) \ | |
124 | dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg) | |
125 | ||
126 | #define pch_err(adap, fmt, arg...) \ | |
127 | dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg) | |
128 | ||
129 | #define pch_pci_err(pdev, fmt, arg...) \ | |
130 | dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg) | |
131 | ||
132 | #define pch_pci_dbg(pdev, fmt, arg...) \ | |
133 | dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg) | |
134 | ||
173442f2 TM |
135 | /* |
136 | Set the number of I2C instance max | |
137 | Intel EG20T PCH : 1ch | |
8956dc10 TM |
138 | LAPIS Semiconductor ML7213 IOH : 2ch |
139 | LAPIS Semiconductor ML7831 IOH : 1ch | |
173442f2 TM |
140 | */ |
141 | #define PCH_I2C_MAX_DEV 2 | |
142 | ||
e9bc8fa5 TM |
143 | /** |
144 | * struct i2c_algo_pch_data - for I2C driver functionalities | |
145 | * @pch_adapter: stores the reference to i2c_adapter structure | |
146 | * @p_adapter_info: stores the reference to adapter_info structure | |
147 | * @pch_base_address: specifies the remapped base address | |
148 | * @pch_buff_mode_en: specifies if buffer mode is enabled | |
149 | * @pch_event_flag: specifies occurrence of interrupt events | |
150 | * @pch_i2c_xfer_in_progress: specifies whether the transfer is completed | |
151 | */ | |
152 | struct i2c_algo_pch_data { | |
153 | struct i2c_adapter pch_adapter; | |
154 | struct adapter_info *p_adapter_info; | |
155 | void __iomem *pch_base_address; | |
156 | int pch_buff_mode_en; | |
157 | u32 pch_event_flag; | |
158 | bool pch_i2c_xfer_in_progress; | |
159 | }; | |
160 | ||
161 | /** | |
162 | * struct adapter_info - This structure holds the adapter information for the | |
163 | PCH i2c controller | |
164 | * @pch_data: stores a list of i2c_algo_pch_data | |
165 | * @pch_i2c_suspended: specifies whether the system is suspended or not | |
166 | * perhaps with more lines and words. | |
173442f2 | 167 | * @ch_num: specifies the number of i2c instance |
e9bc8fa5 TM |
168 | * |
169 | * pch_data has as many elements as maximum I2C channels | |
170 | */ | |
171 | struct adapter_info { | |
173442f2 | 172 | struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV]; |
e9bc8fa5 | 173 | bool pch_i2c_suspended; |
173442f2 | 174 | int ch_num; |
e9bc8fa5 TM |
175 | }; |
176 | ||
177 | ||
178 | static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */ | |
179 | static int pch_clk = 50000; /* specifies I2C clock speed in KHz */ | |
180 | static wait_queue_head_t pch_event; | |
181 | static DEFINE_MUTEX(pch_mutex); | |
182 | ||
8956dc10 | 183 | /* Definition for ML7213 by LAPIS Semiconductor */ |
173442f2 TM |
184 | #define PCI_VENDOR_ID_ROHM 0x10DB |
185 | #define PCI_DEVICE_ID_ML7213_I2C 0x802D | |
efbe0f27 | 186 | #define PCI_DEVICE_ID_ML7223_I2C 0x8010 |
c3f4661f | 187 | #define PCI_DEVICE_ID_ML7831_I2C 0x8817 |
173442f2 | 188 | |
392debf1 | 189 | static const struct pci_device_id pch_pcidev_id[] = { |
173442f2 TM |
190 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C), 1, }, |
191 | { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, }, | |
efbe0f27 | 192 | { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, }, |
c3f4661f | 193 | { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, }, |
e9bc8fa5 TM |
194 | {0,} |
195 | }; | |
196 | ||
197 | static irqreturn_t pch_i2c_handler(int irq, void *pData); | |
198 | ||
199 | static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask) | |
200 | { | |
201 | u32 val; | |
202 | val = ioread32(addr + offset); | |
203 | val |= bitmask; | |
204 | iowrite32(val, addr + offset); | |
205 | } | |
206 | ||
207 | static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask) | |
208 | { | |
209 | u32 val; | |
210 | val = ioread32(addr + offset); | |
211 | val &= (~bitmask); | |
212 | iowrite32(val, addr + offset); | |
213 | } | |
214 | ||
215 | /** | |
216 | * pch_i2c_init() - hardware initialization of I2C module | |
217 | * @adap: Pointer to struct i2c_algo_pch_data. | |
218 | */ | |
219 | static void pch_i2c_init(struct i2c_algo_pch_data *adap) | |
220 | { | |
221 | void __iomem *p = adap->pch_base_address; | |
222 | u32 pch_i2cbc; | |
223 | u32 pch_i2ctmr; | |
224 | u32 reg_value; | |
225 | ||
226 | /* reset I2C controller */ | |
227 | iowrite32(0x01, p + PCH_I2CSRST); | |
228 | msleep(20); | |
229 | iowrite32(0x0, p + PCH_I2CSRST); | |
230 | ||
231 | /* Initialize I2C registers */ | |
232 | iowrite32(0x21, p + PCH_I2CNF); | |
233 | ||
173442f2 | 234 | pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN); |
e9bc8fa5 TM |
235 | |
236 | if (pch_i2c_speed != 400) | |
237 | pch_i2c_speed = 100; | |
238 | ||
239 | reg_value = PCH_I2CCTL_I2CMEN; | |
240 | if (pch_i2c_speed == FAST_MODE_CLK) { | |
241 | reg_value |= FAST_MODE_EN; | |
242 | pch_dbg(adap, "Fast mode enabled\n"); | |
243 | } | |
244 | ||
245 | if (pch_clk > PCH_MAX_CLK) | |
246 | pch_clk = 62500; | |
247 | ||
ff35e8b1 | 248 | pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8); |
e9bc8fa5 TM |
249 | /* Set transfer speed in I2CBC */ |
250 | iowrite32(pch_i2cbc, p + PCH_I2CBC); | |
251 | ||
252 | pch_i2ctmr = (pch_clk) / 8; | |
253 | iowrite32(pch_i2ctmr, p + PCH_I2CTMR); | |
254 | ||
255 | reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */ | |
256 | iowrite32(reg_value, p + PCH_I2CCTL); | |
257 | ||
258 | pch_dbg(adap, | |
259 | "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n", | |
260 | ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr); | |
261 | ||
262 | init_waitqueue_head(&pch_event); | |
263 | } | |
264 | ||
e9bc8fa5 TM |
265 | /** |
266 | * pch_i2c_wait_for_bus_idle() - check the status of bus. | |
267 | * @adap: Pointer to struct i2c_algo_pch_data. | |
0836c809 | 268 | * @timeout: waiting time counter (ms). |
e9bc8fa5 TM |
269 | */ |
270 | static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap, | |
173442f2 | 271 | s32 timeout) |
e9bc8fa5 TM |
272 | { |
273 | void __iomem *p = adap->pch_base_address; | |
0836c809 AS |
274 | int schedule = 0; |
275 | unsigned long end = jiffies + msecs_to_jiffies(timeout); | |
276 | ||
277 | while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) { | |
278 | if (time_after(jiffies, end)) { | |
279 | pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR)); | |
280 | pch_err(adap, "%s: Timeout Error.return%d\n", | |
281 | __func__, -ETIME); | |
282 | pch_i2c_init(adap); | |
283 | ||
284 | return -ETIME; | |
285 | } | |
286 | ||
287 | if (!schedule) | |
288 | /* Retry after some usecs */ | |
289 | udelay(5); | |
290 | else | |
291 | /* Wait a bit more without consuming CPU */ | |
292 | usleep_range(20, 1000); | |
293 | ||
294 | schedule = 1; | |
295 | } | |
e9bc8fa5 | 296 | |
0836c809 | 297 | return 0; |
e9bc8fa5 TM |
298 | } |
299 | ||
300 | /** | |
301 | * pch_i2c_start() - Generate I2C start condition in normal mode. | |
302 | * @adap: Pointer to struct i2c_algo_pch_data. | |
303 | * | |
304 | * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1. | |
305 | */ | |
306 | static void pch_i2c_start(struct i2c_algo_pch_data *adap) | |
307 | { | |
308 | void __iomem *p = adap->pch_base_address; | |
309 | pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); | |
310 | pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START); | |
311 | } | |
312 | ||
e9bc8fa5 TM |
313 | /** |
314 | * pch_i2c_stop() - generate stop condition in normal mode. | |
315 | * @adap: Pointer to struct i2c_algo_pch_data. | |
316 | */ | |
317 | static void pch_i2c_stop(struct i2c_algo_pch_data *adap) | |
318 | { | |
319 | void __iomem *p = adap->pch_base_address; | |
320 | pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); | |
321 | /* clear the start bit */ | |
322 | pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START); | |
323 | } | |
324 | ||
5cc05632 TM |
325 | static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap) |
326 | { | |
199bca2a | 327 | long ret; |
5e47eec0 | 328 | void __iomem *p = adap->pch_base_address; |
199bca2a TM |
329 | |
330 | ret = wait_event_timeout(pch_event, | |
331 | (adap->pch_event_flag != 0), msecs_to_jiffies(1000)); | |
332 | if (!ret) { | |
333 | pch_err(adap, "%s:wait-event timeout\n", __func__); | |
334 | adap->pch_event_flag = 0; | |
335 | pch_i2c_stop(adap); | |
336 | pch_i2c_init(adap); | |
337 | return -ETIMEDOUT; | |
338 | } | |
339 | ||
340 | if (adap->pch_event_flag & I2C_ERROR_MASK) { | |
5cc05632 | 341 | pch_err(adap, "Lost Arbitration\n"); |
199bca2a | 342 | adap->pch_event_flag = 0; |
5cc05632 TM |
343 | pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT); |
344 | pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT); | |
345 | pch_i2c_init(adap); | |
346 | return -EAGAIN; | |
199bca2a TM |
347 | } |
348 | ||
349 | adap->pch_event_flag = 0; | |
350 | ||
5e47eec0 AW |
351 | if (ioread32(p + PCH_I2CSR) & PCH_GETACK) { |
352 | pch_dbg(adap, "Receive NACK for slave address setting\n"); | |
353 | return -ENXIO; | |
5cc05632 TM |
354 | } |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
e9bc8fa5 TM |
359 | /** |
360 | * pch_i2c_repstart() - generate repeated start condition in normal mode | |
361 | * @adap: Pointer to struct i2c_algo_pch_data. | |
362 | */ | |
363 | static void pch_i2c_repstart(struct i2c_algo_pch_data *adap) | |
364 | { | |
365 | void __iomem *p = adap->pch_base_address; | |
366 | pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); | |
367 | pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART); | |
368 | } | |
369 | ||
370 | /** | |
371 | * pch_i2c_writebytes() - write data to I2C bus in normal mode | |
372 | * @i2c_adap: Pointer to the struct i2c_adapter. | |
373 | * @last: specifies whether last message or not. | |
374 | * In the case of compound mode it will be 1 for last message, | |
375 | * otherwise 0. | |
376 | * @first: specifies whether first message or not. | |
377 | * 1 for first message otherwise 0. | |
378 | */ | |
379 | static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap, | |
380 | struct i2c_msg *msgs, u32 last, u32 first) | |
381 | { | |
382 | struct i2c_algo_pch_data *adap = i2c_adap->algo_data; | |
383 | u8 *buf; | |
384 | u32 length; | |
385 | u32 addr; | |
386 | u32 addr_2_msb; | |
387 | u32 addr_8_lsb; | |
388 | s32 wrcount; | |
12bd3146 | 389 | s32 rtn; |
e9bc8fa5 TM |
390 | void __iomem *p = adap->pch_base_address; |
391 | ||
392 | length = msgs->len; | |
393 | buf = msgs->buf; | |
394 | addr = msgs->addr; | |
395 | ||
396 | /* enable master tx */ | |
397 | pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE); | |
398 | ||
399 | pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL), | |
400 | length); | |
401 | ||
402 | if (first) { | |
403 | if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME) | |
404 | return -ETIME; | |
405 | } | |
406 | ||
407 | if (msgs->flags & I2C_M_TEN) { | |
c249ac20 | 408 | addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06; |
e9bc8fa5 TM |
409 | iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR); |
410 | if (first) | |
411 | pch_i2c_start(adap); | |
12bd3146 | 412 | |
5cc05632 TM |
413 | rtn = pch_i2c_wait_for_check_xfer(adap); |
414 | if (rtn) | |
415 | return rtn; | |
416 | ||
417 | addr_8_lsb = (addr & I2C_ADDR_MSK); | |
418 | iowrite32(addr_8_lsb, p + PCH_I2CDR); | |
e9bc8fa5 TM |
419 | } else { |
420 | /* set 7 bit slave address and R/W bit as 0 */ | |
421 | iowrite32(addr << 1, p + PCH_I2CDR); | |
422 | if (first) | |
423 | pch_i2c_start(adap); | |
424 | } | |
425 | ||
5cc05632 TM |
426 | rtn = pch_i2c_wait_for_check_xfer(adap); |
427 | if (rtn) | |
428 | return rtn; | |
e9bc8fa5 | 429 | |
12bd3146 TM |
430 | for (wrcount = 0; wrcount < length; ++wrcount) { |
431 | /* write buffer value to I2C data register */ | |
432 | iowrite32(buf[wrcount], p + PCH_I2CDR); | |
433 | pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]); | |
e9bc8fa5 | 434 | |
5cc05632 TM |
435 | rtn = pch_i2c_wait_for_check_xfer(adap); |
436 | if (rtn) | |
437 | return rtn; | |
438 | ||
439 | pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMCF_BIT); | |
440 | pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT); | |
12bd3146 | 441 | } |
e9bc8fa5 | 442 | |
12bd3146 TM |
443 | /* check if this is the last message */ |
444 | if (last) | |
e9bc8fa5 | 445 | pch_i2c_stop(adap); |
12bd3146 TM |
446 | else |
447 | pch_i2c_repstart(adap); | |
e9bc8fa5 TM |
448 | |
449 | pch_dbg(adap, "return=%d\n", wrcount); | |
450 | ||
451 | return wrcount; | |
452 | } | |
453 | ||
454 | /** | |
455 | * pch_i2c_sendack() - send ACK | |
456 | * @adap: Pointer to struct i2c_algo_pch_data. | |
457 | */ | |
458 | static void pch_i2c_sendack(struct i2c_algo_pch_data *adap) | |
459 | { | |
460 | void __iomem *p = adap->pch_base_address; | |
461 | pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); | |
462 | pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK); | |
463 | } | |
464 | ||
465 | /** | |
466 | * pch_i2c_sendnack() - send NACK | |
467 | * @adap: Pointer to struct i2c_algo_pch_data. | |
468 | */ | |
469 | static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap) | |
470 | { | |
471 | void __iomem *p = adap->pch_base_address; | |
472 | pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); | |
473 | pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK); | |
474 | } | |
475 | ||
c249ac20 TM |
476 | /** |
477 | * pch_i2c_restart() - Generate I2C restart condition in normal mode. | |
478 | * @adap: Pointer to struct i2c_algo_pch_data. | |
479 | * | |
480 | * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA. | |
481 | */ | |
482 | static void pch_i2c_restart(struct i2c_algo_pch_data *adap) | |
483 | { | |
484 | void __iomem *p = adap->pch_base_address; | |
485 | pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); | |
486 | pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART); | |
487 | } | |
488 | ||
e9bc8fa5 TM |
489 | /** |
490 | * pch_i2c_readbytes() - read data from I2C bus in normal mode. | |
491 | * @i2c_adap: Pointer to the struct i2c_adapter. | |
492 | * @msgs: Pointer to i2c_msg structure. | |
493 | * @last: specifies whether last message or not. | |
494 | * @first: specifies whether first message or not. | |
495 | */ | |
173442f2 TM |
496 | static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, |
497 | u32 last, u32 first) | |
e9bc8fa5 TM |
498 | { |
499 | struct i2c_algo_pch_data *adap = i2c_adap->algo_data; | |
500 | ||
501 | u8 *buf; | |
502 | u32 count; | |
503 | u32 length; | |
504 | u32 addr; | |
505 | u32 addr_2_msb; | |
c249ac20 | 506 | u32 addr_8_lsb; |
e9bc8fa5 | 507 | void __iomem *p = adap->pch_base_address; |
12bd3146 | 508 | s32 rtn; |
e9bc8fa5 TM |
509 | |
510 | length = msgs->len; | |
511 | buf = msgs->buf; | |
512 | addr = msgs->addr; | |
513 | ||
514 | /* enable master reception */ | |
515 | pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE); | |
516 | ||
517 | if (first) { | |
518 | if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME) | |
519 | return -ETIME; | |
520 | } | |
521 | ||
522 | if (msgs->flags & I2C_M_TEN) { | |
c249ac20 | 523 | addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7); |
e9bc8fa5 | 524 | iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR); |
c249ac20 TM |
525 | if (first) |
526 | pch_i2c_start(adap); | |
e9bc8fa5 | 527 | |
5cc05632 TM |
528 | rtn = pch_i2c_wait_for_check_xfer(adap); |
529 | if (rtn) | |
530 | return rtn; | |
531 | ||
532 | addr_8_lsb = (addr & I2C_ADDR_MSK); | |
533 | iowrite32(addr_8_lsb, p + PCH_I2CDR); | |
534 | ||
c249ac20 | 535 | pch_i2c_restart(adap); |
5cc05632 TM |
536 | |
537 | rtn = pch_i2c_wait_for_check_xfer(adap); | |
538 | if (rtn) | |
539 | return rtn; | |
540 | ||
541 | addr_2_msb |= I2C_RD; | |
542 | iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR); | |
e9bc8fa5 TM |
543 | } else { |
544 | /* 7 address bits + R/W bit */ | |
545 | addr = (((addr) << 1) | (I2C_RD)); | |
546 | iowrite32(addr, p + PCH_I2CDR); | |
547 | } | |
548 | ||
549 | /* check if it is the first message */ | |
550 | if (first) | |
551 | pch_i2c_start(adap); | |
552 | ||
5cc05632 TM |
553 | rtn = pch_i2c_wait_for_check_xfer(adap); |
554 | if (rtn) | |
555 | return rtn; | |
e9bc8fa5 | 556 | |
12bd3146 TM |
557 | if (length == 0) { |
558 | pch_i2c_stop(adap); | |
559 | ioread32(p + PCH_I2CDR); /* Dummy read needs */ | |
e9bc8fa5 | 560 | |
12bd3146 TM |
561 | count = length; |
562 | } else { | |
563 | int read_index; | |
564 | int loop; | |
565 | pch_i2c_sendack(adap); | |
e9bc8fa5 | 566 | |
12bd3146 TM |
567 | /* Dummy read */ |
568 | for (loop = 1, read_index = 0; loop < length; loop++) { | |
569 | buf[read_index] = ioread32(p + PCH_I2CDR); | |
e9bc8fa5 | 570 | |
12bd3146 TM |
571 | if (loop != 1) |
572 | read_index++; | |
e9bc8fa5 | 573 | |
5cc05632 TM |
574 | rtn = pch_i2c_wait_for_check_xfer(adap); |
575 | if (rtn) | |
576 | return rtn; | |
12bd3146 | 577 | } /* end for */ |
e9bc8fa5 | 578 | |
12bd3146 | 579 | pch_i2c_sendnack(adap); |
e9bc8fa5 | 580 | |
12bd3146 | 581 | buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */ |
e9bc8fa5 | 582 | |
12bd3146 TM |
583 | if (length != 1) |
584 | read_index++; | |
e9bc8fa5 | 585 | |
5cc05632 TM |
586 | rtn = pch_i2c_wait_for_check_xfer(adap); |
587 | if (rtn) | |
588 | return rtn; | |
12bd3146 TM |
589 | |
590 | if (last) | |
591 | pch_i2c_stop(adap); | |
592 | else | |
593 | pch_i2c_repstart(adap); | |
594 | ||
595 | buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */ | |
596 | count = read_index; | |
e9bc8fa5 TM |
597 | } |
598 | ||
599 | return count; | |
600 | } | |
601 | ||
602 | /** | |
173442f2 | 603 | * pch_i2c_cb() - Interrupt handler Call back function |
e9bc8fa5 TM |
604 | * @adap: Pointer to struct i2c_algo_pch_data. |
605 | */ | |
173442f2 | 606 | static void pch_i2c_cb(struct i2c_algo_pch_data *adap) |
e9bc8fa5 TM |
607 | { |
608 | u32 sts; | |
609 | void __iomem *p = adap->pch_base_address; | |
610 | ||
611 | sts = ioread32(p + PCH_I2CSR); | |
612 | sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT); | |
613 | if (sts & I2CMAL_BIT) | |
614 | adap->pch_event_flag |= I2CMAL_EVENT; | |
615 | ||
616 | if (sts & I2CMCF_BIT) | |
617 | adap->pch_event_flag |= I2CMCF_EVENT; | |
618 | ||
619 | /* clear the applicable bits */ | |
620 | pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts); | |
621 | ||
622 | pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR)); | |
623 | ||
624 | wake_up(&pch_event); | |
625 | } | |
626 | ||
627 | /** | |
628 | * pch_i2c_handler() - interrupt handler for the PCH I2C controller | |
629 | * @irq: irq number. | |
630 | * @pData: cookie passed back to the handler function. | |
631 | */ | |
632 | static irqreturn_t pch_i2c_handler(int irq, void *pData) | |
633 | { | |
173442f2 TM |
634 | u32 reg_val; |
635 | int flag; | |
636 | int i; | |
637 | struct adapter_info *adap_info = pData; | |
638 | void __iomem *p; | |
639 | u32 mode; | |
640 | ||
641 | for (i = 0, flag = 0; i < adap_info->ch_num; i++) { | |
642 | p = adap_info->pch_data[i].pch_base_address; | |
643 | mode = ioread32(p + PCH_I2CMOD); | |
644 | mode &= BUFFER_MODE | EEPROM_SR_MODE; | |
645 | if (mode != NORMAL_MODE) { | |
646 | pch_err(adap_info->pch_data, | |
647 | "I2C-%d mode(%d) is not supported\n", mode, i); | |
648 | continue; | |
649 | } | |
650 | reg_val = ioread32(p + PCH_I2CSR); | |
651 | if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) { | |
652 | pch_i2c_cb(&adap_info->pch_data[i]); | |
653 | flag = 1; | |
654 | } | |
e9bc8fa5 TM |
655 | } |
656 | ||
173442f2 | 657 | return flag ? IRQ_HANDLED : IRQ_NONE; |
e9bc8fa5 TM |
658 | } |
659 | ||
660 | /** | |
661 | * pch_i2c_xfer() - Reading adnd writing data through I2C bus | |
662 | * @i2c_adap: Pointer to the struct i2c_adapter. | |
663 | * @msgs: Pointer to i2c_msg structure. | |
664 | * @num: number of messages. | |
665 | */ | |
666 | static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap, | |
173442f2 | 667 | struct i2c_msg *msgs, s32 num) |
e9bc8fa5 TM |
668 | { |
669 | struct i2c_msg *pmsg; | |
670 | u32 i = 0; | |
671 | u32 status; | |
e9bc8fa5 TM |
672 | s32 ret; |
673 | ||
674 | struct i2c_algo_pch_data *adap = i2c_adap->algo_data; | |
675 | ||
676 | ret = mutex_lock_interruptible(&pch_mutex); | |
677 | if (ret) | |
772ae99c | 678 | return ret; |
e9bc8fa5 TM |
679 | |
680 | if (adap->p_adapter_info->pch_i2c_suspended) { | |
681 | mutex_unlock(&pch_mutex); | |
682 | return -EBUSY; | |
683 | } | |
684 | ||
685 | pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n", | |
686 | adap->p_adapter_info->pch_i2c_suspended); | |
687 | /* transfer not completed */ | |
688 | adap->pch_i2c_xfer_in_progress = true; | |
689 | ||
07e729ce | 690 | for (i = 0; i < num && ret >= 0; i++) { |
7a9c42cc TM |
691 | pmsg = &msgs[i]; |
692 | pmsg->flags |= adap->pch_buff_mode_en; | |
693 | status = pmsg->flags; | |
694 | pch_dbg(adap, | |
695 | "After invoking I2C_MODE_SEL :flag= 0x%x\n", status); | |
7a9c42cc TM |
696 | |
697 | if ((status & (I2C_M_RD)) != false) { | |
698 | ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num), | |
699 | (i == 0)); | |
700 | } else { | |
701 | ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num), | |
702 | (i == 0)); | |
703 | } | |
e9bc8fa5 TM |
704 | } |
705 | ||
706 | adap->pch_i2c_xfer_in_progress = false; /* transfer completed */ | |
707 | ||
708 | mutex_unlock(&pch_mutex); | |
709 | ||
07e729ce | 710 | return (ret < 0) ? ret : num; |
e9bc8fa5 TM |
711 | } |
712 | ||
713 | /** | |
714 | * pch_i2c_func() - return the functionality of the I2C driver | |
715 | * @adap: Pointer to struct i2c_algo_pch_data. | |
716 | */ | |
717 | static u32 pch_i2c_func(struct i2c_adapter *adap) | |
718 | { | |
719 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; | |
720 | } | |
721 | ||
722 | static struct i2c_algorithm pch_algorithm = { | |
723 | .master_xfer = pch_i2c_xfer, | |
724 | .functionality = pch_i2c_func | |
725 | }; | |
726 | ||
727 | /** | |
728 | * pch_i2c_disbl_int() - Disable PCH I2C interrupts | |
729 | * @adap: Pointer to struct i2c_algo_pch_data. | |
730 | */ | |
731 | static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap) | |
732 | { | |
733 | void __iomem *p = adap->pch_base_address; | |
734 | ||
735 | pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL); | |
736 | ||
737 | iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK); | |
738 | ||
739 | iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK); | |
740 | } | |
741 | ||
0b255e92 | 742 | static int pch_i2c_probe(struct pci_dev *pdev, |
173442f2 | 743 | const struct pci_device_id *id) |
e9bc8fa5 TM |
744 | { |
745 | void __iomem *base_addr; | |
173442f2 TM |
746 | int ret; |
747 | int i, j; | |
e9bc8fa5 | 748 | struct adapter_info *adap_info; |
173442f2 | 749 | struct i2c_adapter *pch_adap; |
e9bc8fa5 TM |
750 | |
751 | pch_pci_dbg(pdev, "Entered.\n"); | |
752 | ||
753 | adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL); | |
754 | if (adap_info == NULL) { | |
755 | pch_pci_err(pdev, "Memory allocation FAILED\n"); | |
756 | return -ENOMEM; | |
757 | } | |
758 | ||
759 | ret = pci_enable_device(pdev); | |
760 | if (ret) { | |
761 | pch_pci_err(pdev, "pci_enable_device FAILED\n"); | |
762 | goto err_pci_enable; | |
763 | } | |
764 | ||
765 | ret = pci_request_regions(pdev, KBUILD_MODNAME); | |
766 | if (ret) { | |
767 | pch_pci_err(pdev, "pci_request_regions FAILED\n"); | |
768 | goto err_pci_req; | |
769 | } | |
770 | ||
771 | base_addr = pci_iomap(pdev, 1, 0); | |
772 | ||
773 | if (base_addr == NULL) { | |
774 | pch_pci_err(pdev, "pci_iomap FAILED\n"); | |
775 | ret = -ENOMEM; | |
776 | goto err_pci_iomap; | |
777 | } | |
778 | ||
173442f2 TM |
779 | /* Set the number of I2C channel instance */ |
780 | adap_info->ch_num = id->driver_data; | |
e9bc8fa5 | 781 | |
0d5fb5ea FT |
782 | ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED, |
783 | KBUILD_MODNAME, adap_info); | |
784 | if (ret) { | |
785 | pch_pci_err(pdev, "request_irq FAILED\n"); | |
786 | goto err_request_irq; | |
787 | } | |
788 | ||
173442f2 TM |
789 | for (i = 0; i < adap_info->ch_num; i++) { |
790 | pch_adap = &adap_info->pch_data[i].pch_adapter; | |
791 | adap_info->pch_i2c_suspended = false; | |
e9bc8fa5 | 792 | |
173442f2 | 793 | adap_info->pch_data[i].p_adapter_info = adap_info; |
e9bc8fa5 | 794 | |
173442f2 TM |
795 | pch_adap->owner = THIS_MODULE; |
796 | pch_adap->class = I2C_CLASS_HWMON; | |
6188a376 | 797 | strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name)); |
173442f2 TM |
798 | pch_adap->algo = &pch_algorithm; |
799 | pch_adap->algo_data = &adap_info->pch_data[i]; | |
e9bc8fa5 | 800 | |
173442f2 TM |
801 | /* base_addr + offset; */ |
802 | adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i; | |
e9bc8fa5 | 803 | |
173442f2 | 804 | pch_adap->dev.parent = &pdev->dev; |
e9bc8fa5 | 805 | |
0d5fb5ea | 806 | pch_i2c_init(&adap_info->pch_data[i]); |
07e8a51f FT |
807 | |
808 | pch_adap->nr = i; | |
809 | ret = i2c_add_numbered_adapter(pch_adap); | |
173442f2 TM |
810 | if (ret) { |
811 | pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i); | |
0d5fb5ea | 812 | goto err_add_adapter; |
173442f2 | 813 | } |
e9bc8fa5 TM |
814 | } |
815 | ||
816 | pci_set_drvdata(pdev, adap_info); | |
817 | pch_pci_dbg(pdev, "returns %d.\n", ret); | |
818 | return 0; | |
819 | ||
0d5fb5ea | 820 | err_add_adapter: |
173442f2 TM |
821 | for (j = 0; j < i; j++) |
822 | i2c_del_adapter(&adap_info->pch_data[j].pch_adapter); | |
0d5fb5ea FT |
823 | free_irq(pdev->irq, adap_info); |
824 | err_request_irq: | |
e9bc8fa5 TM |
825 | pci_iounmap(pdev, base_addr); |
826 | err_pci_iomap: | |
827 | pci_release_regions(pdev); | |
828 | err_pci_req: | |
829 | pci_disable_device(pdev); | |
830 | err_pci_enable: | |
831 | kfree(adap_info); | |
832 | return ret; | |
833 | } | |
834 | ||
0b255e92 | 835 | static void pch_i2c_remove(struct pci_dev *pdev) |
e9bc8fa5 | 836 | { |
173442f2 | 837 | int i; |
e9bc8fa5 TM |
838 | struct adapter_info *adap_info = pci_get_drvdata(pdev); |
839 | ||
173442f2 | 840 | free_irq(pdev->irq, adap_info); |
e9bc8fa5 | 841 | |
173442f2 TM |
842 | for (i = 0; i < adap_info->ch_num; i++) { |
843 | pch_i2c_disbl_int(&adap_info->pch_data[i]); | |
844 | i2c_del_adapter(&adap_info->pch_data[i].pch_adapter); | |
e9bc8fa5 TM |
845 | } |
846 | ||
173442f2 TM |
847 | if (adap_info->pch_data[0].pch_base_address) |
848 | pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address); | |
849 | ||
850 | for (i = 0; i < adap_info->ch_num; i++) | |
75fb1f25 | 851 | adap_info->pch_data[i].pch_base_address = NULL; |
173442f2 | 852 | |
e9bc8fa5 TM |
853 | pci_release_regions(pdev); |
854 | ||
855 | pci_disable_device(pdev); | |
856 | kfree(adap_info); | |
857 | } | |
858 | ||
859 | #ifdef CONFIG_PM | |
860 | static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state) | |
861 | { | |
862 | int ret; | |
173442f2 | 863 | int i; |
e9bc8fa5 | 864 | struct adapter_info *adap_info = pci_get_drvdata(pdev); |
173442f2 | 865 | void __iomem *p = adap_info->pch_data[0].pch_base_address; |
e9bc8fa5 TM |
866 | |
867 | adap_info->pch_i2c_suspended = true; | |
868 | ||
173442f2 TM |
869 | for (i = 0; i < adap_info->ch_num; i++) { |
870 | while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) { | |
871 | /* Wait until all channel transfers are completed */ | |
872 | msleep(20); | |
873 | } | |
e9bc8fa5 | 874 | } |
173442f2 | 875 | |
e9bc8fa5 | 876 | /* Disable the i2c interrupts */ |
173442f2 TM |
877 | for (i = 0; i < adap_info->ch_num; i++) |
878 | pch_i2c_disbl_int(&adap_info->pch_data[i]); | |
e9bc8fa5 TM |
879 | |
880 | pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x " | |
881 | "invoked function pch_i2c_disbl_int successfully\n", | |
882 | ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA), | |
883 | ioread32(p + PCH_I2CESRSTA)); | |
884 | ||
885 | ret = pci_save_state(pdev); | |
886 | ||
887 | if (ret) { | |
888 | pch_pci_err(pdev, "pci_save_state\n"); | |
889 | return ret; | |
890 | } | |
891 | ||
892 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
893 | pci_disable_device(pdev); | |
894 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
895 | ||
896 | return 0; | |
897 | } | |
898 | ||
899 | static int pch_i2c_resume(struct pci_dev *pdev) | |
900 | { | |
173442f2 | 901 | int i; |
e9bc8fa5 TM |
902 | struct adapter_info *adap_info = pci_get_drvdata(pdev); |
903 | ||
904 | pci_set_power_state(pdev, PCI_D0); | |
905 | pci_restore_state(pdev); | |
906 | ||
907 | if (pci_enable_device(pdev) < 0) { | |
908 | pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n"); | |
909 | return -EIO; | |
910 | } | |
911 | ||
912 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
913 | ||
173442f2 TM |
914 | for (i = 0; i < adap_info->ch_num; i++) |
915 | pch_i2c_init(&adap_info->pch_data[i]); | |
e9bc8fa5 TM |
916 | |
917 | adap_info->pch_i2c_suspended = false; | |
918 | ||
919 | return 0; | |
920 | } | |
921 | #else | |
922 | #define pch_i2c_suspend NULL | |
923 | #define pch_i2c_resume NULL | |
924 | #endif | |
925 | ||
926 | static struct pci_driver pch_pcidriver = { | |
927 | .name = KBUILD_MODNAME, | |
928 | .id_table = pch_pcidev_id, | |
929 | .probe = pch_i2c_probe, | |
0b255e92 | 930 | .remove = pch_i2c_remove, |
e9bc8fa5 TM |
931 | .suspend = pch_i2c_suspend, |
932 | .resume = pch_i2c_resume | |
933 | }; | |
934 | ||
56f21788 | 935 | module_pci_driver(pch_pcidriver); |
e9bc8fa5 | 936 | |
8956dc10 | 937 | MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C"); |
e9bc8fa5 | 938 | MODULE_LICENSE("GPL"); |
09640713 | 939 | MODULE_AUTHOR("Tomoya MORINAGA. <tomoya.rohm@gmail.com>"); |
e9bc8fa5 TM |
940 | module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR)); |
941 | module_param(pch_clk, int, (S_IRUSR | S_IWUSR)); |