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5faf6e1f WS |
1 | /* |
2 | * I2C driver for the Renesas EMEV2 SoC | |
3 | * | |
4 | * Copyright (C) 2015 Wolfram Sang <wsa@sang-engineering.com> | |
5 | * Copyright 2013 Codethink Ltd. | |
6 | * Copyright 2010-2015 Renesas Electronics Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 | |
10 | * as published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/completion.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/i2c.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/of_device.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/sched.h> | |
25 | ||
26 | /* I2C Registers */ | |
27 | #define I2C_OFS_IICACT0 0x00 /* start */ | |
28 | #define I2C_OFS_IIC0 0x04 /* shift */ | |
29 | #define I2C_OFS_IICC0 0x08 /* control */ | |
30 | #define I2C_OFS_SVA0 0x0c /* slave address */ | |
31 | #define I2C_OFS_IICCL0 0x10 /* clock select */ | |
32 | #define I2C_OFS_IICX0 0x14 /* extension */ | |
33 | #define I2C_OFS_IICS0 0x18 /* status */ | |
34 | #define I2C_OFS_IICSE0 0x1c /* status For emulation */ | |
35 | #define I2C_OFS_IICF0 0x20 /* IIC flag */ | |
36 | ||
37 | /* I2C IICACT0 Masks */ | |
38 | #define I2C_BIT_IICE0 0x0001 | |
39 | ||
40 | /* I2C IICC0 Masks */ | |
41 | #define I2C_BIT_LREL0 0x0040 | |
42 | #define I2C_BIT_WREL0 0x0020 | |
43 | #define I2C_BIT_SPIE0 0x0010 | |
44 | #define I2C_BIT_WTIM0 0x0008 | |
45 | #define I2C_BIT_ACKE0 0x0004 | |
46 | #define I2C_BIT_STT0 0x0002 | |
47 | #define I2C_BIT_SPT0 0x0001 | |
48 | ||
49 | /* I2C IICCL0 Masks */ | |
50 | #define I2C_BIT_SMC0 0x0008 | |
51 | #define I2C_BIT_DFC0 0x0004 | |
52 | ||
53 | /* I2C IICSE0 Masks */ | |
54 | #define I2C_BIT_MSTS0 0x0080 | |
55 | #define I2C_BIT_ALD0 0x0040 | |
56 | #define I2C_BIT_EXC0 0x0020 | |
57 | #define I2C_BIT_COI0 0x0010 | |
58 | #define I2C_BIT_TRC0 0x0008 | |
59 | #define I2C_BIT_ACKD0 0x0004 | |
60 | #define I2C_BIT_STD0 0x0002 | |
61 | #define I2C_BIT_SPD0 0x0001 | |
62 | ||
63 | /* I2C IICF0 Masks */ | |
64 | #define I2C_BIT_STCF 0x0080 | |
65 | #define I2C_BIT_IICBSY 0x0040 | |
66 | #define I2C_BIT_STCEN 0x0002 | |
67 | #define I2C_BIT_IICRSV 0x0001 | |
68 | ||
69 | struct em_i2c_device { | |
70 | void __iomem *base; | |
71 | struct i2c_adapter adap; | |
72 | struct completion msg_done; | |
73 | struct clk *sclk; | |
c31d0a00 | 74 | struct i2c_client *slave; |
5faf6e1f WS |
75 | }; |
76 | ||
77 | static inline void em_clear_set_bit(struct em_i2c_device *priv, u8 clear, u8 set, u8 reg) | |
78 | { | |
79 | writeb((readb(priv->base + reg) & ~clear) | set, priv->base + reg); | |
80 | } | |
81 | ||
82 | static int em_i2c_wait_for_event(struct em_i2c_device *priv) | |
83 | { | |
84 | unsigned long time_left; | |
85 | int status; | |
86 | ||
87 | reinit_completion(&priv->msg_done); | |
88 | ||
89 | time_left = wait_for_completion_timeout(&priv->msg_done, priv->adap.timeout); | |
90 | ||
91 | if (!time_left) | |
92 | return -ETIMEDOUT; | |
93 | ||
94 | status = readb(priv->base + I2C_OFS_IICSE0); | |
95 | return status & I2C_BIT_ALD0 ? -EAGAIN : status; | |
96 | } | |
97 | ||
98 | static void em_i2c_stop(struct em_i2c_device *priv) | |
99 | { | |
100 | /* Send Stop condition */ | |
101 | em_clear_set_bit(priv, 0, I2C_BIT_SPT0 | I2C_BIT_SPIE0, I2C_OFS_IICC0); | |
102 | ||
103 | /* Wait for stop condition */ | |
104 | em_i2c_wait_for_event(priv); | |
105 | } | |
106 | ||
107 | static void em_i2c_reset(struct i2c_adapter *adap) | |
108 | { | |
109 | struct em_i2c_device *priv = i2c_get_adapdata(adap); | |
110 | int retr; | |
111 | ||
112 | /* If I2C active */ | |
113 | if (readb(priv->base + I2C_OFS_IICACT0) & I2C_BIT_IICE0) { | |
114 | /* Disable I2C operation */ | |
115 | writeb(0, priv->base + I2C_OFS_IICACT0); | |
116 | ||
117 | retr = 1000; | |
118 | while (readb(priv->base + I2C_OFS_IICACT0) == 1 && retr) | |
119 | retr--; | |
120 | WARN_ON(retr == 0); | |
121 | } | |
122 | ||
123 | /* Transfer mode set */ | |
124 | writeb(I2C_BIT_DFC0, priv->base + I2C_OFS_IICCL0); | |
125 | ||
126 | /* Can Issue start without detecting a stop, Reservation disabled. */ | |
127 | writeb(I2C_BIT_STCEN | I2C_BIT_IICRSV, priv->base + I2C_OFS_IICF0); | |
128 | ||
129 | /* I2C enable, 9 bit interrupt mode */ | |
130 | writeb(I2C_BIT_WTIM0, priv->base + I2C_OFS_IICC0); | |
131 | ||
132 | /* Enable I2C operation */ | |
133 | writeb(I2C_BIT_IICE0, priv->base + I2C_OFS_IICACT0); | |
134 | ||
135 | retr = 1000; | |
136 | while (readb(priv->base + I2C_OFS_IICACT0) == 0 && retr) | |
137 | retr--; | |
138 | WARN_ON(retr == 0); | |
139 | } | |
140 | ||
141 | static int __em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, | |
142 | int stop) | |
143 | { | |
144 | struct em_i2c_device *priv = i2c_get_adapdata(adap); | |
145 | int count, status, read = !!(msg->flags & I2C_M_RD); | |
146 | ||
147 | /* Send start condition */ | |
148 | em_clear_set_bit(priv, 0, I2C_BIT_ACKE0 | I2C_BIT_WTIM0, I2C_OFS_IICC0); | |
149 | em_clear_set_bit(priv, 0, I2C_BIT_STT0, I2C_OFS_IICC0); | |
150 | ||
151 | /* Send slave address and R/W type */ | |
152 | writeb((msg->addr << 1) | read, priv->base + I2C_OFS_IIC0); | |
153 | ||
154 | /* Wait for transaction */ | |
155 | status = em_i2c_wait_for_event(priv); | |
156 | if (status < 0) | |
157 | goto out_reset; | |
158 | ||
159 | /* Received NACK (result of setting slave address and R/W) */ | |
160 | if (!(status & I2C_BIT_ACKD0)) { | |
161 | em_i2c_stop(priv); | |
162 | goto out; | |
163 | } | |
164 | ||
165 | /* Extra setup for read transactions */ | |
166 | if (read) { | |
167 | /* 8 bit interrupt mode */ | |
168 | em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0, I2C_OFS_IICC0); | |
169 | em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0, I2C_OFS_IICC0); | |
170 | ||
171 | /* Wait for transaction */ | |
172 | status = em_i2c_wait_for_event(priv); | |
173 | if (status < 0) | |
174 | goto out_reset; | |
175 | } | |
176 | ||
177 | /* Send / receive data */ | |
178 | for (count = 0; count < msg->len; count++) { | |
179 | if (read) { /* Read transaction */ | |
180 | msg->buf[count] = readb(priv->base + I2C_OFS_IIC0); | |
181 | em_clear_set_bit(priv, 0, I2C_BIT_WREL0, I2C_OFS_IICC0); | |
182 | ||
183 | } else { /* Write transaction */ | |
184 | /* Received NACK */ | |
185 | if (!(status & I2C_BIT_ACKD0)) { | |
186 | em_i2c_stop(priv); | |
187 | goto out; | |
188 | } | |
189 | ||
190 | /* Write data */ | |
191 | writeb(msg->buf[count], priv->base + I2C_OFS_IIC0); | |
192 | } | |
193 | ||
194 | /* Wait for R/W transaction */ | |
195 | status = em_i2c_wait_for_event(priv); | |
196 | if (status < 0) | |
197 | goto out_reset; | |
198 | } | |
199 | ||
200 | if (stop) | |
201 | em_i2c_stop(priv); | |
202 | ||
203 | return count; | |
204 | ||
205 | out_reset: | |
206 | em_i2c_reset(adap); | |
207 | out: | |
208 | return status < 0 ? status : -ENXIO; | |
209 | } | |
210 | ||
211 | static int em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, | |
212 | int num) | |
213 | { | |
214 | struct em_i2c_device *priv = i2c_get_adapdata(adap); | |
215 | int ret, i; | |
216 | ||
217 | if (readb(priv->base + I2C_OFS_IICF0) & I2C_BIT_IICBSY) | |
218 | return -EAGAIN; | |
219 | ||
220 | for (i = 0; i < num; i++) { | |
221 | ret = __em_i2c_xfer(adap, &msgs[i], (i == (num - 1))); | |
222 | if (ret < 0) | |
223 | return ret; | |
224 | } | |
225 | ||
226 | /* I2C transfer completed */ | |
227 | return num; | |
228 | } | |
229 | ||
c31d0a00 NS |
230 | static bool em_i2c_slave_irq(struct em_i2c_device *priv) |
231 | { | |
232 | u8 status, value; | |
233 | enum i2c_slave_event event; | |
234 | int ret; | |
235 | ||
236 | if (!priv->slave) | |
237 | return false; | |
238 | ||
239 | status = readb(priv->base + I2C_OFS_IICSE0); | |
240 | ||
241 | /* Extension code, do not participate */ | |
242 | if (status & I2C_BIT_EXC0) { | |
243 | em_clear_set_bit(priv, 0, I2C_BIT_LREL0, I2C_OFS_IICC0); | |
244 | return true; | |
245 | } | |
246 | ||
247 | /* Stop detected, we don't know if it's for slave or master */ | |
248 | if (status & I2C_BIT_SPD0) { | |
249 | /* Notify slave device */ | |
250 | i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); | |
251 | /* Pretend we did not handle the interrupt */ | |
252 | return false; | |
253 | } | |
254 | ||
255 | /* Only handle interrupts addressed to us */ | |
256 | if (!(status & I2C_BIT_COI0)) | |
257 | return false; | |
258 | ||
259 | /* Enable stop interrupts */ | |
260 | em_clear_set_bit(priv, 0, I2C_BIT_SPIE0, I2C_OFS_IICC0); | |
261 | ||
262 | /* Transmission or Reception */ | |
263 | if (status & I2C_BIT_TRC0) { | |
264 | if (status & I2C_BIT_ACKD0) { | |
265 | /* 9 bit interrupt mode */ | |
266 | em_clear_set_bit(priv, 0, I2C_BIT_WTIM0, I2C_OFS_IICC0); | |
267 | ||
268 | /* Send data */ | |
269 | event = status & I2C_BIT_STD0 ? | |
270 | I2C_SLAVE_READ_REQUESTED : | |
271 | I2C_SLAVE_READ_PROCESSED; | |
272 | i2c_slave_event(priv->slave, event, &value); | |
273 | writeb(value, priv->base + I2C_OFS_IIC0); | |
274 | } else { | |
275 | /* NACK, stop transmitting */ | |
276 | em_clear_set_bit(priv, 0, I2C_BIT_LREL0, I2C_OFS_IICC0); | |
277 | } | |
278 | } else { | |
279 | /* 8 bit interrupt mode */ | |
280 | em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0, | |
281 | I2C_OFS_IICC0); | |
282 | em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0, | |
283 | I2C_OFS_IICC0); | |
284 | ||
285 | if (status & I2C_BIT_STD0) { | |
286 | i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, | |
287 | &value); | |
288 | } else { | |
289 | /* Recv data */ | |
290 | value = readb(priv->base + I2C_OFS_IIC0); | |
291 | ret = i2c_slave_event(priv->slave, | |
292 | I2C_SLAVE_WRITE_RECEIVED, &value); | |
293 | if (ret < 0) | |
294 | em_clear_set_bit(priv, I2C_BIT_ACKE0, 0, | |
295 | I2C_OFS_IICC0); | |
296 | } | |
297 | } | |
298 | ||
299 | return true; | |
300 | } | |
301 | ||
5faf6e1f WS |
302 | static irqreturn_t em_i2c_irq_handler(int this_irq, void *dev_id) |
303 | { | |
304 | struct em_i2c_device *priv = dev_id; | |
305 | ||
c31d0a00 NS |
306 | if (em_i2c_slave_irq(priv)) |
307 | return IRQ_HANDLED; | |
308 | ||
5faf6e1f | 309 | complete(&priv->msg_done); |
c31d0a00 | 310 | |
5faf6e1f WS |
311 | return IRQ_HANDLED; |
312 | } | |
313 | ||
314 | static u32 em_i2c_func(struct i2c_adapter *adap) | |
315 | { | |
c31d0a00 NS |
316 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SLAVE; |
317 | } | |
318 | ||
319 | static int em_i2c_reg_slave(struct i2c_client *slave) | |
320 | { | |
321 | struct em_i2c_device *priv = i2c_get_adapdata(slave->adapter); | |
322 | ||
323 | if (priv->slave) | |
324 | return -EBUSY; | |
325 | ||
326 | if (slave->flags & I2C_CLIENT_TEN) | |
327 | return -EAFNOSUPPORT; | |
328 | ||
329 | priv->slave = slave; | |
330 | ||
331 | /* Set slave address */ | |
332 | writeb(slave->addr << 1, priv->base + I2C_OFS_SVA0); | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
337 | static int em_i2c_unreg_slave(struct i2c_client *slave) | |
338 | { | |
339 | struct em_i2c_device *priv = i2c_get_adapdata(slave->adapter); | |
340 | ||
341 | WARN_ON(!priv->slave); | |
342 | ||
343 | writeb(0, priv->base + I2C_OFS_SVA0); | |
344 | ||
345 | priv->slave = NULL; | |
346 | ||
347 | return 0; | |
5faf6e1f WS |
348 | } |
349 | ||
350 | static struct i2c_algorithm em_i2c_algo = { | |
351 | .master_xfer = em_i2c_xfer, | |
352 | .functionality = em_i2c_func, | |
c31d0a00 NS |
353 | .reg_slave = em_i2c_reg_slave, |
354 | .unreg_slave = em_i2c_unreg_slave, | |
5faf6e1f WS |
355 | }; |
356 | ||
357 | static int em_i2c_probe(struct platform_device *pdev) | |
358 | { | |
359 | struct em_i2c_device *priv; | |
360 | struct resource *r; | |
361 | int irq, ret; | |
362 | ||
363 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); | |
364 | if (!priv) | |
365 | return -ENOMEM; | |
366 | ||
367 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
368 | priv->base = devm_ioremap_resource(&pdev->dev, r); | |
369 | if (IS_ERR(priv->base)) | |
370 | return PTR_ERR(priv->base); | |
371 | ||
372 | strlcpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name)); | |
373 | ||
374 | priv->sclk = devm_clk_get(&pdev->dev, "sclk"); | |
375 | if (IS_ERR(priv->sclk)) | |
376 | return PTR_ERR(priv->sclk); | |
377 | ||
378 | clk_prepare_enable(priv->sclk); | |
379 | ||
380 | priv->adap.timeout = msecs_to_jiffies(100); | |
381 | priv->adap.retries = 5; | |
382 | priv->adap.dev.parent = &pdev->dev; | |
383 | priv->adap.algo = &em_i2c_algo; | |
384 | priv->adap.owner = THIS_MODULE; | |
385 | priv->adap.dev.of_node = pdev->dev.of_node; | |
386 | ||
387 | init_completion(&priv->msg_done); | |
388 | ||
389 | platform_set_drvdata(pdev, priv); | |
390 | i2c_set_adapdata(&priv->adap, priv); | |
391 | ||
392 | em_i2c_reset(&priv->adap); | |
393 | ||
394 | irq = platform_get_irq(pdev, 0); | |
395 | ret = devm_request_irq(&pdev->dev, irq, em_i2c_irq_handler, 0, | |
396 | "em_i2c", priv); | |
397 | if (ret) | |
398 | goto err_clk; | |
399 | ||
400 | ret = i2c_add_adapter(&priv->adap); | |
401 | ||
402 | if (ret) | |
403 | goto err_clk; | |
404 | ||
405 | dev_info(&pdev->dev, "Added i2c controller %d, irq %d\n", priv->adap.nr, irq); | |
406 | ||
407 | return 0; | |
408 | ||
409 | err_clk: | |
410 | clk_disable_unprepare(priv->sclk); | |
411 | return ret; | |
412 | } | |
413 | ||
414 | static int em_i2c_remove(struct platform_device *dev) | |
415 | { | |
416 | struct em_i2c_device *priv = platform_get_drvdata(dev); | |
417 | ||
418 | i2c_del_adapter(&priv->adap); | |
419 | clk_disable_unprepare(priv->sclk); | |
420 | ||
421 | return 0; | |
422 | } | |
423 | ||
424 | static const struct of_device_id em_i2c_ids[] = { | |
425 | { .compatible = "renesas,iic-emev2", }, | |
426 | { } | |
427 | }; | |
428 | ||
429 | static struct platform_driver em_i2c_driver = { | |
430 | .probe = em_i2c_probe, | |
431 | .remove = em_i2c_remove, | |
432 | .driver = { | |
433 | .name = "em-i2c", | |
434 | .of_match_table = em_i2c_ids, | |
435 | } | |
436 | }; | |
437 | module_platform_driver(em_i2c_driver); | |
438 | ||
439 | MODULE_DESCRIPTION("EMEV2 I2C bus driver"); | |
440 | MODULE_AUTHOR("Ian Molton and Wolfram Sang <wsa@sang-engineering.com>"); | |
441 | MODULE_LICENSE("GPL v2"); | |
442 | MODULE_DEVICE_TABLE(of, em_i2c_ids); |