Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, |
3 | Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker | |
4 | <mdsxyz123@yahoo.com> | |
b3b8df97 | 5 | Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> |
0cd96eb0 DW |
6 | Copyright (C) 2010 Intel Corporation, |
7 | David Woodhouse <dwmw2@infradead.org> | |
1da177e4 LT |
8 | |
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
1da177e4 LT |
18 | */ |
19 | ||
20 | /* | |
ce316110 JD |
21 | * Supports the following Intel I/O Controller Hubs (ICH): |
22 | * | |
23 | * I/O Block I2C | |
24 | * region SMBus Block proc. block | |
25 | * Chip name PCI ID size PEC buffer call read | |
26 | * --------------------------------------------------------------------------- | |
27 | * 82801AA (ICH) 0x2413 16 no no no no | |
28 | * 82801AB (ICH0) 0x2423 16 no no no no | |
29 | * 82801BA (ICH2) 0x2443 16 no no no no | |
30 | * 82801CA (ICH3) 0x2483 32 soft no no no | |
31 | * 82801DB (ICH4) 0x24c3 32 hard yes no no | |
32 | * 82801E (ICH5) 0x24d3 32 hard yes yes yes | |
33 | * 6300ESB 0x25a4 32 hard yes yes yes | |
34 | * 82801F (ICH6) 0x266a 32 hard yes yes yes | |
35 | * 6310ESB/6320ESB 0x269b 32 hard yes yes yes | |
36 | * 82801G (ICH7) 0x27da 32 hard yes yes yes | |
37 | * 82801H (ICH8) 0x283e 32 hard yes yes yes | |
38 | * 82801I (ICH9) 0x2930 32 hard yes yes yes | |
39 | * EP80579 (Tolapai) 0x5032 32 hard yes yes yes | |
40 | * ICH10 0x3a30 32 hard yes yes yes | |
41 | * ICH10 0x3a60 32 hard yes yes yes | |
42 | * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes | |
43 | * 6 Series (PCH) 0x1c22 32 hard yes yes yes | |
44 | * Patsburg (PCH) 0x1d22 32 hard yes yes yes | |
45 | * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes | |
46 | * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes | |
47 | * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes | |
48 | * DH89xxCC (PCH) 0x2330 32 hard yes yes yes | |
49 | * Panther Point (PCH) 0x1e22 32 hard yes yes yes | |
50 | * Lynx Point (PCH) 0x8c22 32 hard yes yes yes | |
51 | * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes | |
52 | * Avoton (SOC) 0x1f3c 32 hard yes yes yes | |
53 | * Wellsburg (PCH) 0x8d22 32 hard yes yes yes | |
54 | * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes | |
55 | * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes | |
56 | * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes | |
57 | * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes | |
b299de83 | 58 | * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes |
ce316110 JD |
59 | * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes |
60 | * BayTrail (SOC) 0x0f12 32 hard yes yes yes | |
3e27a844 | 61 | * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes |
3eee1799 | 62 | * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes |
84d7f2eb | 63 | * DNV (SOC) 0x19df 32 hard yes yes yes |
dd77f423 | 64 | * Broxton (SOC) 0x5ad4 32 hard yes yes yes |
cdc5a311 AY |
65 | * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes |
66 | * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes | |
ce316110 JD |
67 | * |
68 | * Features supported by this driver: | |
69 | * Software PEC no | |
70 | * Hardware PEC yes | |
71 | * Block buffer yes | |
72 | * Block process call transaction no | |
73 | * I2C block read transaction yes (doesn't use the block buffer) | |
74 | * Slave mode no | |
75 | * Interrupt processing yes | |
76 | * | |
77 | * See the file Documentation/i2c/busses/i2c-i801 for details. | |
78 | */ | |
1da177e4 | 79 | |
636752bc | 80 | #include <linux/interrupt.h> |
1da177e4 LT |
81 | #include <linux/module.h> |
82 | #include <linux/pci.h> | |
83 | #include <linux/kernel.h> | |
84 | #include <linux/stddef.h> | |
85 | #include <linux/delay.h> | |
1da177e4 LT |
86 | #include <linux/ioport.h> |
87 | #include <linux/init.h> | |
88 | #include <linux/i2c.h> | |
54fb4a05 | 89 | #include <linux/acpi.h> |
1561bfe5 | 90 | #include <linux/io.h> |
fa5bfab7 | 91 | #include <linux/dmi.h> |
665a96b7 | 92 | #include <linux/slab.h> |
636752bc | 93 | #include <linux/wait.h> |
3ad7ea18 | 94 | #include <linux/err.h> |
94246930 MW |
95 | #include <linux/platform_device.h> |
96 | #include <linux/platform_data/itco_wdt.h> | |
a7401ca5 | 97 | #include <linux/pm_runtime.h> |
3ad7ea18 | 98 | |
79e3e5b8 JD |
99 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
100 | defined CONFIG_DMI | |
3ad7ea18 JD |
101 | #include <linux/gpio.h> |
102 | #include <linux/i2c-mux-gpio.h> | |
3ad7ea18 | 103 | #endif |
1da177e4 | 104 | |
1da177e4 | 105 | /* I801 SMBus address offsets */ |
0cd96eb0 DW |
106 | #define SMBHSTSTS(p) (0 + (p)->smba) |
107 | #define SMBHSTCNT(p) (2 + (p)->smba) | |
108 | #define SMBHSTCMD(p) (3 + (p)->smba) | |
109 | #define SMBHSTADD(p) (4 + (p)->smba) | |
110 | #define SMBHSTDAT0(p) (5 + (p)->smba) | |
111 | #define SMBHSTDAT1(p) (6 + (p)->smba) | |
112 | #define SMBBLKDAT(p) (7 + (p)->smba) | |
113 | #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ | |
114 | #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ | |
115 | #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ | |
1da177e4 LT |
116 | |
117 | /* PCI Address Constants */ | |
6dcc19df | 118 | #define SMBBAR 4 |
aeb8a3d1 | 119 | #define SMBPCICTL 0x004 |
636752bc | 120 | #define SMBPCISTS 0x006 |
1da177e4 | 121 | #define SMBHSTCFG 0x040 |
94246930 MW |
122 | #define TCOBASE 0x050 |
123 | #define TCOCTL 0x054 | |
124 | ||
125 | #define ACPIBASE 0x040 | |
126 | #define ACPIBASE_SMI_OFF 0x030 | |
127 | #define ACPICTRL 0x044 | |
128 | #define ACPICTRL_EN 0x080 | |
129 | ||
130 | #define SBREG_BAR 0x10 | |
131 | #define SBREG_SMBCTRL 0xc6000c | |
1da177e4 | 132 | |
636752bc DK |
133 | /* Host status bits for SMBPCISTS */ |
134 | #define SMBPCISTS_INTS 0x08 | |
135 | ||
aeb8a3d1 JD |
136 | /* Control bits for SMBPCICTL */ |
137 | #define SMBPCICTL_INTDIS 0x0400 | |
138 | ||
1da177e4 LT |
139 | /* Host configuration bits for SMBHSTCFG */ |
140 | #define SMBHSTCFG_HST_EN 1 | |
141 | #define SMBHSTCFG_SMB_SMI_EN 2 | |
142 | #define SMBHSTCFG_I2C_EN 4 | |
143 | ||
94246930 MW |
144 | /* TCO configuration bits for TCOCTL */ |
145 | #define TCOCTL_EN 0x0100 | |
146 | ||
25985edc | 147 | /* Auxiliary control register bits, ICH4+ only */ |
ca8b9e32 OR |
148 | #define SMBAUXCTL_CRC 1 |
149 | #define SMBAUXCTL_E32B 2 | |
150 | ||
1da177e4 | 151 | /* Other settings */ |
84c1af4c | 152 | #define MAX_RETRIES 400 |
1da177e4 LT |
153 | |
154 | /* I801 command constants */ | |
155 | #define I801_QUICK 0x00 | |
156 | #define I801_BYTE 0x04 | |
157 | #define I801_BYTE_DATA 0x08 | |
158 | #define I801_WORD_DATA 0x0C | |
ae7b0497 | 159 | #define I801_PROC_CALL 0x10 /* unimplemented */ |
1da177e4 | 160 | #define I801_BLOCK_DATA 0x14 |
6342064c | 161 | #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ |
edbeea63 DK |
162 | |
163 | /* I801 Host Control register bits */ | |
164 | #define SMBHSTCNT_INTREN 0x01 | |
165 | #define SMBHSTCNT_KILL 0x02 | |
166 | #define SMBHSTCNT_LAST_BYTE 0x20 | |
167 | #define SMBHSTCNT_START 0x40 | |
168 | #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */ | |
1da177e4 | 169 | |
ca8b9e32 OR |
170 | /* I801 Hosts Status register bits */ |
171 | #define SMBHSTSTS_BYTE_DONE 0x80 | |
172 | #define SMBHSTSTS_INUSE_STS 0x40 | |
173 | #define SMBHSTSTS_SMBALERT_STS 0x20 | |
174 | #define SMBHSTSTS_FAILED 0x10 | |
175 | #define SMBHSTSTS_BUS_ERR 0x08 | |
176 | #define SMBHSTSTS_DEV_ERR 0x04 | |
177 | #define SMBHSTSTS_INTR 0x02 | |
178 | #define SMBHSTSTS_HOST_BUSY 0x01 | |
1da177e4 | 179 | |
70a1cc19 DK |
180 | #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ |
181 | SMBHSTSTS_DEV_ERR) | |
182 | ||
183 | #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ | |
184 | STATUS_ERROR_FLAGS) | |
cf898dc5 | 185 | |
a6e5e2be | 186 | /* Older devices have their ID defined in <linux/pci_ids.h> */ |
ce316110 | 187 | #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 |
34b57f40 | 188 | #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df |
ce316110 JD |
189 | #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 |
190 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 | |
55fee8d7 | 191 | /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ |
ce316110 JD |
192 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 |
193 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 | |
194 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 | |
195 | #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 | |
196 | #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c | |
34b57f40 | 197 | #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 |
ce316110 JD |
198 | #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 |
199 | #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 | |
200 | #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 | |
34b57f40 | 201 | #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 |
ce316110 | 202 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 |
b299de83 | 203 | #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 |
ce316110 JD |
204 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 |
205 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d | |
206 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e | |
207 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f | |
208 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 | |
afc65924 | 209 | #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 |
3eee1799 | 210 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 |
34b57f40 | 211 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 |
cdc5a311 AY |
212 | #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 |
213 | #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 | |
55fee8d7 | 214 | |
3ad7ea18 JD |
215 | struct i801_mux_config { |
216 | char *gpio_chip; | |
217 | unsigned values[3]; | |
218 | int n_values; | |
219 | unsigned classes[3]; | |
220 | unsigned gpios[2]; /* Relative to gpio_chip->base */ | |
221 | int n_gpios; | |
222 | }; | |
223 | ||
0cd96eb0 DW |
224 | struct i801_priv { |
225 | struct i2c_adapter adapter; | |
226 | unsigned long smba; | |
227 | unsigned char original_hstcfg; | |
228 | struct pci_dev *pci_dev; | |
229 | unsigned int features; | |
636752bc DK |
230 | |
231 | /* isr processing */ | |
232 | wait_queue_head_t waitq; | |
233 | u8 status; | |
d3ff6ce4 DK |
234 | |
235 | /* Command state used by isr for byte-by-byte block transactions */ | |
236 | u8 cmd; | |
237 | bool is_read; | |
238 | int count; | |
239 | int len; | |
240 | u8 *data; | |
3ad7ea18 | 241 | |
79e3e5b8 JD |
242 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
243 | defined CONFIG_DMI | |
3ad7ea18 | 244 | const struct i801_mux_config *mux_drvdata; |
3ad7ea18 JD |
245 | struct platform_device *mux_pdev; |
246 | #endif | |
94246930 | 247 | struct platform_device *tco_pdev; |
0cd96eb0 DW |
248 | }; |
249 | ||
369f6f4a JD |
250 | #define FEATURE_SMBUS_PEC (1 << 0) |
251 | #define FEATURE_BLOCK_BUFFER (1 << 1) | |
252 | #define FEATURE_BLOCK_PROC (1 << 2) | |
253 | #define FEATURE_I2C_BLOCK_READ (1 << 3) | |
636752bc | 254 | #define FEATURE_IRQ (1 << 4) |
e7198fbf JD |
255 | /* Not really a feature, but it's convenient to handle it as such */ |
256 | #define FEATURE_IDF (1 << 15) | |
94246930 | 257 | #define FEATURE_TCO (1 << 16) |
1da177e4 | 258 | |
adff687d JD |
259 | static const char *i801_feature_names[] = { |
260 | "SMBus PEC", | |
261 | "Block buffer", | |
262 | "Block process call", | |
263 | "I2C block read", | |
636752bc | 264 | "Interrupt", |
adff687d JD |
265 | }; |
266 | ||
267 | static unsigned int disable_features; | |
268 | module_param(disable_features, uint, S_IRUGO | S_IWUSR); | |
53229345 JD |
269 | MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" |
270 | "\t\t 0x01 disable SMBus PEC\n" | |
271 | "\t\t 0x02 disable the block buffer\n" | |
272 | "\t\t 0x08 disable the I2C block read functionality\n" | |
273 | "\t\t 0x10 don't use interrupts "); | |
adff687d | 274 | |
cf898dc5 JD |
275 | /* Make sure the SMBus host is ready to start transmitting. |
276 | Return 0 if it is, -EBUSY if it is not. */ | |
0cd96eb0 | 277 | static int i801_check_pre(struct i801_priv *priv) |
1da177e4 | 278 | { |
2b73809d | 279 | int status; |
1da177e4 | 280 | |
0cd96eb0 | 281 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 | 282 | if (status & SMBHSTSTS_HOST_BUSY) { |
0cd96eb0 | 283 | dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); |
cf898dc5 JD |
284 | return -EBUSY; |
285 | } | |
286 | ||
287 | status &= STATUS_FLAGS; | |
288 | if (status) { | |
0cd96eb0 | 289 | dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", |
2b73809d | 290 | status); |
0cd96eb0 DW |
291 | outb_p(status, SMBHSTSTS(priv)); |
292 | status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; | |
cf898dc5 | 293 | if (status) { |
0cd96eb0 | 294 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
295 | "Failed clearing status flags (%02x)\n", |
296 | status); | |
97140342 | 297 | return -EBUSY; |
1da177e4 LT |
298 | } |
299 | } | |
300 | ||
cf898dc5 JD |
301 | return 0; |
302 | } | |
1da177e4 | 303 | |
6cad93c4 JD |
304 | /* |
305 | * Convert the status register to an error code, and clear it. | |
306 | * Note that status only contains the bits we want to clear, not the | |
307 | * actual register value. | |
308 | */ | |
309 | static int i801_check_post(struct i801_priv *priv, int status) | |
cf898dc5 JD |
310 | { |
311 | int result = 0; | |
1da177e4 | 312 | |
636752bc DK |
313 | /* |
314 | * If the SMBus is still busy, we give up | |
315 | * Note: This timeout condition only happens when using polling | |
316 | * transactions. For interrupt operation, NAK/timeout is indicated by | |
317 | * DEV_ERR. | |
318 | */ | |
6cad93c4 | 319 | if (unlikely(status < 0)) { |
0cd96eb0 | 320 | dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); |
ca8b9e32 | 321 | /* try to stop the current command */ |
0cd96eb0 DW |
322 | dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); |
323 | outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, | |
324 | SMBHSTCNT(priv)); | |
84c1af4c | 325 | usleep_range(1000, 2000); |
0cd96eb0 DW |
326 | outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), |
327 | SMBHSTCNT(priv)); | |
cf898dc5 JD |
328 | |
329 | /* Check if it worked */ | |
0cd96eb0 | 330 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 JD |
331 | if ((status & SMBHSTSTS_HOST_BUSY) || |
332 | !(status & SMBHSTSTS_FAILED)) | |
0cd96eb0 | 333 | dev_err(&priv->pci_dev->dev, |
cf898dc5 | 334 | "Failed terminating the transaction\n"); |
0cd96eb0 | 335 | outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); |
cf898dc5 | 336 | return -ETIMEDOUT; |
1da177e4 LT |
337 | } |
338 | ||
2b73809d | 339 | if (status & SMBHSTSTS_FAILED) { |
97140342 | 340 | result = -EIO; |
0cd96eb0 | 341 | dev_err(&priv->pci_dev->dev, "Transaction failed\n"); |
cf898dc5 JD |
342 | } |
343 | if (status & SMBHSTSTS_DEV_ERR) { | |
344 | result = -ENXIO; | |
0cd96eb0 | 345 | dev_dbg(&priv->pci_dev->dev, "No response\n"); |
1da177e4 | 346 | } |
2b73809d | 347 | if (status & SMBHSTSTS_BUS_ERR) { |
dcb5c923 | 348 | result = -EAGAIN; |
0cd96eb0 | 349 | dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); |
1da177e4 LT |
350 | } |
351 | ||
6cad93c4 JD |
352 | /* Clear status flags except BYTE_DONE, to be cleared by caller */ |
353 | outb_p(status, SMBHSTSTS(priv)); | |
1da177e4 | 354 | |
1da177e4 LT |
355 | return result; |
356 | } | |
357 | ||
6cad93c4 JD |
358 | /* Wait for BUSY being cleared and either INTR or an error flag being set */ |
359 | static int i801_wait_intr(struct i801_priv *priv) | |
cf898dc5 | 360 | { |
cf898dc5 | 361 | int timeout = 0; |
6cad93c4 | 362 | int status; |
cf898dc5 JD |
363 | |
364 | /* We will always wait for a fraction of a second! */ | |
365 | do { | |
84c1af4c | 366 | usleep_range(250, 500); |
0cd96eb0 | 367 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
368 | } while (((status & SMBHSTSTS_HOST_BUSY) || |
369 | !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && | |
370 | (timeout++ < MAX_RETRIES)); | |
cf898dc5 | 371 | |
6cad93c4 JD |
372 | if (timeout > MAX_RETRIES) { |
373 | dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); | |
374 | return -ETIMEDOUT; | |
375 | } | |
376 | return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); | |
cf898dc5 JD |
377 | } |
378 | ||
6cad93c4 JD |
379 | /* Wait for either BYTE_DONE or an error flag being set */ |
380 | static int i801_wait_byte_done(struct i801_priv *priv) | |
ca8b9e32 OR |
381 | { |
382 | int timeout = 0; | |
2b73809d | 383 | int status; |
ca8b9e32 | 384 | |
6cad93c4 | 385 | /* We will always wait for a fraction of a second! */ |
ca8b9e32 | 386 | do { |
84c1af4c | 387 | usleep_range(250, 500); |
0cd96eb0 | 388 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
389 | } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && |
390 | (timeout++ < MAX_RETRIES)); | |
391 | ||
392 | if (timeout > MAX_RETRIES) { | |
393 | dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); | |
394 | return -ETIMEDOUT; | |
395 | } | |
396 | return status & STATUS_ERROR_FLAGS; | |
397 | } | |
398 | ||
399 | static int i801_transaction(struct i801_priv *priv, int xact) | |
400 | { | |
401 | int status; | |
402 | int result; | |
b3b8df97 | 403 | const struct i2c_adapter *adap = &priv->adapter; |
ca8b9e32 | 404 | |
6cad93c4 JD |
405 | result = i801_check_pre(priv); |
406 | if (result < 0) | |
407 | return result; | |
4ccc28f7 | 408 | |
636752bc DK |
409 | if (priv->features & FEATURE_IRQ) { |
410 | outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, | |
411 | SMBHSTCNT(priv)); | |
b3b8df97 JD |
412 | result = wait_event_timeout(priv->waitq, |
413 | (status = priv->status), | |
414 | adap->timeout); | |
415 | if (!result) { | |
416 | status = -ETIMEDOUT; | |
417 | dev_warn(&priv->pci_dev->dev, | |
418 | "Timeout waiting for interrupt!\n"); | |
419 | } | |
636752bc DK |
420 | priv->status = 0; |
421 | return i801_check_post(priv, status); | |
422 | } | |
423 | ||
6cad93c4 JD |
424 | /* the current contents of SMBHSTCNT can be overwritten, since PEC, |
425 | * SMBSCMD are passed in xact */ | |
426 | outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); | |
427 | ||
428 | status = i801_wait_intr(priv); | |
429 | return i801_check_post(priv, status); | |
ca8b9e32 OR |
430 | } |
431 | ||
0cd96eb0 DW |
432 | static int i801_block_transaction_by_block(struct i801_priv *priv, |
433 | union i2c_smbus_data *data, | |
7edcb9ab OR |
434 | char read_write, int hwpec) |
435 | { | |
436 | int i, len; | |
97140342 | 437 | int status; |
7edcb9ab | 438 | |
0cd96eb0 | 439 | inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ |
7edcb9ab OR |
440 | |
441 | /* Use 32-byte buffer to process this transaction */ | |
442 | if (read_write == I2C_SMBUS_WRITE) { | |
443 | len = data->block[0]; | |
0cd96eb0 | 444 | outb_p(len, SMBHSTDAT0(priv)); |
7edcb9ab | 445 | for (i = 0; i < len; i++) |
0cd96eb0 | 446 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
7edcb9ab OR |
447 | } |
448 | ||
37af8711 | 449 | status = i801_transaction(priv, I801_BLOCK_DATA | |
edbeea63 | 450 | (hwpec ? SMBHSTCNT_PEC_EN : 0)); |
97140342 DB |
451 | if (status) |
452 | return status; | |
7edcb9ab OR |
453 | |
454 | if (read_write == I2C_SMBUS_READ) { | |
0cd96eb0 | 455 | len = inb_p(SMBHSTDAT0(priv)); |
7edcb9ab | 456 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) |
97140342 | 457 | return -EPROTO; |
7edcb9ab OR |
458 | |
459 | data->block[0] = len; | |
460 | for (i = 0; i < len; i++) | |
0cd96eb0 | 461 | data->block[i + 1] = inb_p(SMBBLKDAT(priv)); |
7edcb9ab OR |
462 | } |
463 | return 0; | |
464 | } | |
465 | ||
d3ff6ce4 DK |
466 | static void i801_isr_byte_done(struct i801_priv *priv) |
467 | { | |
468 | if (priv->is_read) { | |
469 | /* For SMBus block reads, length is received with first byte */ | |
470 | if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && | |
471 | (priv->count == 0)) { | |
472 | priv->len = inb_p(SMBHSTDAT0(priv)); | |
473 | if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { | |
474 | dev_err(&priv->pci_dev->dev, | |
475 | "Illegal SMBus block read size %d\n", | |
476 | priv->len); | |
477 | /* FIXME: Recover */ | |
478 | priv->len = I2C_SMBUS_BLOCK_MAX; | |
479 | } else { | |
480 | dev_dbg(&priv->pci_dev->dev, | |
481 | "SMBus block read size is %d\n", | |
482 | priv->len); | |
483 | } | |
484 | priv->data[-1] = priv->len; | |
485 | } | |
486 | ||
487 | /* Read next byte */ | |
488 | if (priv->count < priv->len) | |
489 | priv->data[priv->count++] = inb(SMBBLKDAT(priv)); | |
490 | else | |
491 | dev_dbg(&priv->pci_dev->dev, | |
492 | "Discarding extra byte on block read\n"); | |
493 | ||
494 | /* Set LAST_BYTE for last byte of read transaction */ | |
495 | if (priv->count == priv->len - 1) | |
496 | outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, | |
497 | SMBHSTCNT(priv)); | |
498 | } else if (priv->count < priv->len - 1) { | |
499 | /* Write next byte, except for IRQ after last byte */ | |
500 | outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); | |
501 | } | |
502 | ||
503 | /* Clear BYTE_DONE to continue with next byte */ | |
504 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); | |
505 | } | |
506 | ||
636752bc | 507 | /* |
d3ff6ce4 DK |
508 | * There are two kinds of interrupts: |
509 | * | |
510 | * 1) i801 signals transaction completion with one of these interrupts: | |
511 | * INTR - Success | |
512 | * DEV_ERR - Invalid command, NAK or communication timeout | |
513 | * BUS_ERR - SMI# transaction collision | |
514 | * FAILED - transaction was canceled due to a KILL request | |
515 | * When any of these occur, update ->status and wake up the waitq. | |
516 | * ->status must be cleared before kicking off the next transaction. | |
517 | * | |
518 | * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt | |
519 | * occurs for each byte of a byte-by-byte to prepare the next byte. | |
636752bc DK |
520 | */ |
521 | static irqreturn_t i801_isr(int irq, void *dev_id) | |
522 | { | |
523 | struct i801_priv *priv = dev_id; | |
524 | u16 pcists; | |
525 | u8 status; | |
526 | ||
527 | /* Confirm this is our interrupt */ | |
528 | pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); | |
529 | if (!(pcists & SMBPCISTS_INTS)) | |
530 | return IRQ_NONE; | |
531 | ||
532 | status = inb_p(SMBHSTSTS(priv)); | |
d3ff6ce4 DK |
533 | if (status & SMBHSTSTS_BYTE_DONE) |
534 | i801_isr_byte_done(priv); | |
535 | ||
636752bc DK |
536 | /* |
537 | * Clear irq sources and report transaction result. | |
538 | * ->status must be cleared before the next transaction is started. | |
539 | */ | |
540 | status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; | |
541 | if (status) { | |
542 | outb_p(status, SMBHSTSTS(priv)); | |
543 | priv->status |= status; | |
544 | wake_up(&priv->waitq); | |
545 | } | |
546 | ||
547 | return IRQ_HANDLED; | |
548 | } | |
549 | ||
efa3cb15 DK |
550 | /* |
551 | * For "byte-by-byte" block transactions: | |
552 | * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 | |
553 | * I2C read uses cmd=I801_I2C_BLOCK_DATA | |
554 | */ | |
0cd96eb0 DW |
555 | static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, |
556 | union i2c_smbus_data *data, | |
6342064c JD |
557 | char read_write, int command, |
558 | int hwpec) | |
1da177e4 LT |
559 | { |
560 | int i, len; | |
561 | int smbcmd; | |
2b73809d | 562 | int status; |
cf898dc5 | 563 | int result; |
b3b8df97 | 564 | const struct i2c_adapter *adap = &priv->adapter; |
cf898dc5 | 565 | |
0cd96eb0 | 566 | result = i801_check_pre(priv); |
cf898dc5 JD |
567 | if (result < 0) |
568 | return result; | |
1da177e4 | 569 | |
7edcb9ab | 570 | len = data->block[0]; |
1da177e4 LT |
571 | |
572 | if (read_write == I2C_SMBUS_WRITE) { | |
0cd96eb0 DW |
573 | outb_p(len, SMBHSTDAT0(priv)); |
574 | outb_p(data->block[1], SMBBLKDAT(priv)); | |
1da177e4 LT |
575 | } |
576 | ||
efa3cb15 DK |
577 | if (command == I2C_SMBUS_I2C_BLOCK_DATA && |
578 | read_write == I2C_SMBUS_READ) | |
579 | smbcmd = I801_I2C_BLOCK_DATA; | |
580 | else | |
581 | smbcmd = I801_BLOCK_DATA; | |
582 | ||
d3ff6ce4 DK |
583 | if (priv->features & FEATURE_IRQ) { |
584 | priv->is_read = (read_write == I2C_SMBUS_READ); | |
585 | if (len == 1 && priv->is_read) | |
586 | smbcmd |= SMBHSTCNT_LAST_BYTE; | |
587 | priv->cmd = smbcmd | SMBHSTCNT_INTREN; | |
588 | priv->len = len; | |
589 | priv->count = 0; | |
590 | priv->data = &data->block[1]; | |
591 | ||
592 | outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); | |
b3b8df97 JD |
593 | result = wait_event_timeout(priv->waitq, |
594 | (status = priv->status), | |
595 | adap->timeout); | |
596 | if (!result) { | |
597 | status = -ETIMEDOUT; | |
598 | dev_warn(&priv->pci_dev->dev, | |
599 | "Timeout waiting for interrupt!\n"); | |
600 | } | |
d3ff6ce4 DK |
601 | priv->status = 0; |
602 | return i801_check_post(priv, status); | |
603 | } | |
604 | ||
1da177e4 | 605 | for (i = 1; i <= len; i++) { |
efa3cb15 | 606 | if (i == len && read_write == I2C_SMBUS_READ) |
edbeea63 | 607 | smbcmd |= SMBHSTCNT_LAST_BYTE; |
37af8711 | 608 | outb_p(smbcmd, SMBHSTCNT(priv)); |
1da177e4 | 609 | |
1da177e4 | 610 | if (i == 1) |
edbeea63 | 611 | outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, |
0cd96eb0 | 612 | SMBHSTCNT(priv)); |
1da177e4 | 613 | |
6cad93c4 JD |
614 | status = i801_wait_byte_done(priv); |
615 | if (status) | |
616 | goto exit; | |
1da177e4 | 617 | |
6342064c JD |
618 | if (i == 1 && read_write == I2C_SMBUS_READ |
619 | && command != I2C_SMBUS_I2C_BLOCK_DATA) { | |
0cd96eb0 | 620 | len = inb_p(SMBHSTDAT0(priv)); |
cf898dc5 | 621 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { |
0cd96eb0 | 622 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
623 | "Illegal SMBus block read size %d\n", |
624 | len); | |
625 | /* Recover */ | |
0cd96eb0 DW |
626 | while (inb_p(SMBHSTSTS(priv)) & |
627 | SMBHSTSTS_HOST_BUSY) | |
628 | outb_p(SMBHSTSTS_BYTE_DONE, | |
629 | SMBHSTSTS(priv)); | |
630 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); | |
97140342 | 631 | return -EPROTO; |
cf898dc5 | 632 | } |
1da177e4 LT |
633 | data->block[0] = len; |
634 | } | |
635 | ||
636 | /* Retrieve/store value in SMBBLKDAT */ | |
637 | if (read_write == I2C_SMBUS_READ) | |
0cd96eb0 | 638 | data->block[i] = inb_p(SMBBLKDAT(priv)); |
1da177e4 | 639 | if (read_write == I2C_SMBUS_WRITE && i+1 <= len) |
0cd96eb0 | 640 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
1da177e4 | 641 | |
cf898dc5 | 642 | /* signals SMBBLKDAT ready */ |
6cad93c4 | 643 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); |
1da177e4 | 644 | } |
cf898dc5 | 645 | |
6cad93c4 JD |
646 | status = i801_wait_intr(priv); |
647 | exit: | |
648 | return i801_check_post(priv, status); | |
7edcb9ab | 649 | } |
1da177e4 | 650 | |
0cd96eb0 | 651 | static int i801_set_block_buffer_mode(struct i801_priv *priv) |
7edcb9ab | 652 | { |
0cd96eb0 DW |
653 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); |
654 | if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) | |
97140342 | 655 | return -EIO; |
7edcb9ab OR |
656 | return 0; |
657 | } | |
658 | ||
659 | /* Block transaction function */ | |
0cd96eb0 DW |
660 | static int i801_block_transaction(struct i801_priv *priv, |
661 | union i2c_smbus_data *data, char read_write, | |
7edcb9ab OR |
662 | int command, int hwpec) |
663 | { | |
664 | int result = 0; | |
665 | unsigned char hostc; | |
666 | ||
667 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
668 | if (read_write == I2C_SMBUS_WRITE) { | |
669 | /* set I2C_EN bit in configuration register */ | |
0cd96eb0 DW |
670 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); |
671 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, | |
7edcb9ab | 672 | hostc | SMBHSTCFG_I2C_EN); |
0cd96eb0 DW |
673 | } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { |
674 | dev_err(&priv->pci_dev->dev, | |
6342064c | 675 | "I2C block read is unsupported!\n"); |
97140342 | 676 | return -EOPNOTSUPP; |
7edcb9ab OR |
677 | } |
678 | } | |
679 | ||
6342064c JD |
680 | if (read_write == I2C_SMBUS_WRITE |
681 | || command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
7edcb9ab OR |
682 | if (data->block[0] < 1) |
683 | data->block[0] = 1; | |
684 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) | |
685 | data->block[0] = I2C_SMBUS_BLOCK_MAX; | |
686 | } else { | |
6342064c | 687 | data->block[0] = 32; /* max for SMBus block reads */ |
7edcb9ab OR |
688 | } |
689 | ||
c074c39d JD |
690 | /* Experience has shown that the block buffer can only be used for |
691 | SMBus (not I2C) block transactions, even though the datasheet | |
692 | doesn't mention this limitation. */ | |
0cd96eb0 | 693 | if ((priv->features & FEATURE_BLOCK_BUFFER) |
c074c39d | 694 | && command != I2C_SMBUS_I2C_BLOCK_DATA |
0cd96eb0 DW |
695 | && i801_set_block_buffer_mode(priv) == 0) |
696 | result = i801_block_transaction_by_block(priv, data, | |
697 | read_write, hwpec); | |
7edcb9ab | 698 | else |
0cd96eb0 DW |
699 | result = i801_block_transaction_byte_by_byte(priv, data, |
700 | read_write, | |
6342064c | 701 | command, hwpec); |
7edcb9ab | 702 | |
6342064c JD |
703 | if (command == I2C_SMBUS_I2C_BLOCK_DATA |
704 | && read_write == I2C_SMBUS_WRITE) { | |
1da177e4 | 705 | /* restore saved configuration register value */ |
0cd96eb0 | 706 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); |
1da177e4 LT |
707 | } |
708 | return result; | |
709 | } | |
710 | ||
97140342 | 711 | /* Return negative errno on error. */ |
3fb21c64 | 712 | static s32 i801_access(struct i2c_adapter *adap, u16 addr, |
1da177e4 | 713 | unsigned short flags, char read_write, u8 command, |
3fb21c64 | 714 | int size, union i2c_smbus_data *data) |
1da177e4 | 715 | { |
e8aac4a9 | 716 | int hwpec; |
1da177e4 | 717 | int block = 0; |
a7401ca5 | 718 | int ret = 0, xact = 0; |
0cd96eb0 | 719 | struct i801_priv *priv = i2c_get_adapdata(adap); |
1da177e4 | 720 | |
a7401ca5 JN |
721 | pm_runtime_get_sync(&priv->pci_dev->dev); |
722 | ||
0cd96eb0 | 723 | hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) |
e8aac4a9 JD |
724 | && size != I2C_SMBUS_QUICK |
725 | && size != I2C_SMBUS_I2C_BLOCK_DATA; | |
1da177e4 LT |
726 | |
727 | switch (size) { | |
728 | case I2C_SMBUS_QUICK: | |
729 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 730 | SMBHSTADD(priv)); |
1da177e4 LT |
731 | xact = I801_QUICK; |
732 | break; | |
733 | case I2C_SMBUS_BYTE: | |
734 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 735 | SMBHSTADD(priv)); |
1da177e4 | 736 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 737 | outb_p(command, SMBHSTCMD(priv)); |
1da177e4 LT |
738 | xact = I801_BYTE; |
739 | break; | |
740 | case I2C_SMBUS_BYTE_DATA: | |
741 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
742 | SMBHSTADD(priv)); |
743 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 744 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 745 | outb_p(data->byte, SMBHSTDAT0(priv)); |
1da177e4 LT |
746 | xact = I801_BYTE_DATA; |
747 | break; | |
748 | case I2C_SMBUS_WORD_DATA: | |
749 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
750 | SMBHSTADD(priv)); |
751 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 752 | if (read_write == I2C_SMBUS_WRITE) { |
0cd96eb0 DW |
753 | outb_p(data->word & 0xff, SMBHSTDAT0(priv)); |
754 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); | |
1da177e4 LT |
755 | } |
756 | xact = I801_WORD_DATA; | |
757 | break; | |
758 | case I2C_SMBUS_BLOCK_DATA: | |
1da177e4 | 759 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
0cd96eb0 DW |
760 | SMBHSTADD(priv)); |
761 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 LT |
762 | block = 1; |
763 | break; | |
6342064c JD |
764 | case I2C_SMBUS_I2C_BLOCK_DATA: |
765 | /* NB: page 240 of ICH5 datasheet shows that the R/#W | |
766 | * bit should be cleared here, even when reading */ | |
0cd96eb0 | 767 | outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); |
6342064c JD |
768 | if (read_write == I2C_SMBUS_READ) { |
769 | /* NB: page 240 of ICH5 datasheet also shows | |
770 | * that DATA1 is the cmd field when reading */ | |
0cd96eb0 | 771 | outb_p(command, SMBHSTDAT1(priv)); |
6342064c | 772 | } else |
0cd96eb0 | 773 | outb_p(command, SMBHSTCMD(priv)); |
6342064c JD |
774 | block = 1; |
775 | break; | |
1da177e4 | 776 | default: |
0cd96eb0 DW |
777 | dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", |
778 | size); | |
a7401ca5 JN |
779 | ret = -EOPNOTSUPP; |
780 | goto out; | |
1da177e4 LT |
781 | } |
782 | ||
ca8b9e32 | 783 | if (hwpec) /* enable/disable hardware PEC */ |
0cd96eb0 | 784 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); |
ca8b9e32 | 785 | else |
0cd96eb0 DW |
786 | outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), |
787 | SMBAUXCTL(priv)); | |
e8aac4a9 | 788 | |
3fb21c64 | 789 | if (block) |
0cd96eb0 DW |
790 | ret = i801_block_transaction(priv, data, read_write, size, |
791 | hwpec); | |
7edcb9ab | 792 | else |
37af8711 | 793 | ret = i801_transaction(priv, xact); |
1da177e4 | 794 | |
c79cfbac | 795 | /* Some BIOSes don't like it when PEC is enabled at reboot or resume |
7edcb9ab OR |
796 | time, so we forcibly disable it after every transaction. Turn off |
797 | E32B for the same reason. */ | |
a0921b6c | 798 | if (hwpec || block) |
0cd96eb0 DW |
799 | outb_p(inb_p(SMBAUXCTL(priv)) & |
800 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
c79cfbac | 801 | |
3fb21c64 | 802 | if (block) |
a7401ca5 | 803 | goto out; |
3fb21c64 | 804 | if (ret) |
a7401ca5 | 805 | goto out; |
1da177e4 | 806 | if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) |
a7401ca5 | 807 | goto out; |
1da177e4 LT |
808 | |
809 | switch (xact & 0x7f) { | |
810 | case I801_BYTE: /* Result put in SMBHSTDAT0 */ | |
811 | case I801_BYTE_DATA: | |
0cd96eb0 | 812 | data->byte = inb_p(SMBHSTDAT0(priv)); |
1da177e4 LT |
813 | break; |
814 | case I801_WORD_DATA: | |
0cd96eb0 DW |
815 | data->word = inb_p(SMBHSTDAT0(priv)) + |
816 | (inb_p(SMBHSTDAT1(priv)) << 8); | |
1da177e4 LT |
817 | break; |
818 | } | |
a7401ca5 JN |
819 | |
820 | out: | |
821 | pm_runtime_mark_last_busy(&priv->pci_dev->dev); | |
822 | pm_runtime_put_autosuspend(&priv->pci_dev->dev); | |
823 | return ret; | |
1da177e4 LT |
824 | } |
825 | ||
826 | ||
827 | static u32 i801_func(struct i2c_adapter *adapter) | |
828 | { | |
0cd96eb0 DW |
829 | struct i801_priv *priv = i2c_get_adapdata(adapter); |
830 | ||
1da177e4 | 831 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | |
369f6f4a JD |
832 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | |
833 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | | |
0cd96eb0 DW |
834 | ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | |
835 | ((priv->features & FEATURE_I2C_BLOCK_READ) ? | |
6342064c | 836 | I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); |
1da177e4 LT |
837 | } |
838 | ||
8f9082c5 | 839 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
840 | .smbus_xfer = i801_access, |
841 | .functionality = i801_func, | |
842 | }; | |
843 | ||
392debf1 | 844 | static const struct pci_device_id i801_ids[] = { |
1da177e4 LT |
845 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, |
846 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, | |
847 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, | |
848 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, | |
849 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, | |
850 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, | |
851 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, | |
852 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, | |
853 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, | |
b0a70b57 | 854 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, |
8254fc4a | 855 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, |
adbc2a10 | 856 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, |
cb04e95b | 857 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, |
d28dc711 GJ |
858 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, |
859 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, | |
cb04e95b SH |
860 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, |
861 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, | |
e30d9859 | 862 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, |
55fee8d7 DW |
863 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, |
864 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, | |
865 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, | |
662cda8a | 866 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, |
6e2a851e | 867 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, |
062737fb | 868 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, |
4a8f1ddd | 869 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, |
c2db409c | 870 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, |
a3fc0ff0 JR |
871 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, |
872 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, | |
873 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, | |
874 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, | |
f39901c1 | 875 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, |
b299de83 | 876 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, |
afc65924 | 877 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, |
1b31e9b7 | 878 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, |
39e8e30e | 879 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, |
3e27a844 | 880 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, |
3eee1799 | 881 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, |
84d7f2eb | 882 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, |
dd77f423 | 883 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, |
cdc5a311 AY |
884 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, |
885 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, | |
1da177e4 LT |
886 | { 0, } |
887 | }; | |
888 | ||
3fb21c64 | 889 | MODULE_DEVICE_TABLE(pci, i801_ids); |
1da177e4 | 890 | |
8eacfceb | 891 | #if defined CONFIG_X86 && defined CONFIG_DMI |
1561bfe5 JD |
892 | static unsigned char apanel_addr; |
893 | ||
894 | /* Scan the system ROM for the signature "FJKEYINF" */ | |
895 | static __init const void __iomem *bios_signature(const void __iomem *bios) | |
896 | { | |
897 | ssize_t offset; | |
898 | const unsigned char signature[] = "FJKEYINF"; | |
899 | ||
900 | for (offset = 0; offset < 0x10000; offset += 0x10) { | |
901 | if (check_signature(bios + offset, signature, | |
902 | sizeof(signature)-1)) | |
903 | return bios + offset; | |
904 | } | |
905 | return NULL; | |
906 | } | |
907 | ||
908 | static void __init input_apanel_init(void) | |
909 | { | |
910 | void __iomem *bios; | |
911 | const void __iomem *p; | |
912 | ||
913 | bios = ioremap(0xF0000, 0x10000); /* Can't fail */ | |
914 | p = bios_signature(bios); | |
915 | if (p) { | |
916 | /* just use the first address */ | |
917 | apanel_addr = readb(p + 8 + 3) >> 1; | |
918 | } | |
919 | iounmap(bios); | |
920 | } | |
1561bfe5 | 921 | |
fa5bfab7 HG |
922 | struct dmi_onboard_device_info { |
923 | const char *name; | |
924 | u8 type; | |
925 | unsigned short i2c_addr; | |
926 | const char *i2c_type; | |
927 | }; | |
928 | ||
0b255e92 | 929 | static const struct dmi_onboard_device_info dmi_devices[] = { |
fa5bfab7 HG |
930 | { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, |
931 | { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, | |
932 | { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, | |
933 | }; | |
934 | ||
0b255e92 BP |
935 | static void dmi_check_onboard_device(u8 type, const char *name, |
936 | struct i2c_adapter *adap) | |
fa5bfab7 HG |
937 | { |
938 | int i; | |
939 | struct i2c_board_info info; | |
940 | ||
941 | for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { | |
942 | /* & ~0x80, ignore enabled/disabled bit */ | |
943 | if ((type & ~0x80) != dmi_devices[i].type) | |
944 | continue; | |
faabd47f | 945 | if (strcasecmp(name, dmi_devices[i].name)) |
fa5bfab7 HG |
946 | continue; |
947 | ||
948 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
949 | info.addr = dmi_devices[i].i2c_addr; | |
950 | strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); | |
951 | i2c_new_device(adap, &info); | |
952 | break; | |
953 | } | |
954 | } | |
955 | ||
956 | /* We use our own function to check for onboard devices instead of | |
957 | dmi_find_device() as some buggy BIOS's have the devices we are interested | |
958 | in marked as disabled */ | |
0b255e92 | 959 | static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) |
fa5bfab7 HG |
960 | { |
961 | int i, count; | |
962 | ||
963 | if (dm->type != 10) | |
964 | return; | |
965 | ||
966 | count = (dm->length - sizeof(struct dmi_header)) / 2; | |
967 | for (i = 0; i < count; i++) { | |
968 | const u8 *d = (char *)(dm + 1) + (i * 2); | |
969 | const char *name = ((char *) dm) + dm->length; | |
970 | u8 type = d[0]; | |
971 | u8 s = d[1]; | |
972 | ||
973 | if (!s) | |
974 | continue; | |
975 | s--; | |
976 | while (s > 0 && name[0]) { | |
977 | name += strlen(name) + 1; | |
978 | s--; | |
979 | } | |
980 | if (name[0] == 0) /* Bogus string reference */ | |
981 | continue; | |
982 | ||
983 | dmi_check_onboard_device(type, name, adap); | |
984 | } | |
985 | } | |
fa5bfab7 | 986 | |
e7198fbf | 987 | /* Register optional slaves */ |
0b255e92 | 988 | static void i801_probe_optional_slaves(struct i801_priv *priv) |
e7198fbf JD |
989 | { |
990 | /* Only register slaves on main SMBus channel */ | |
991 | if (priv->features & FEATURE_IDF) | |
992 | return; | |
993 | ||
e7198fbf JD |
994 | if (apanel_addr) { |
995 | struct i2c_board_info info; | |
996 | ||
997 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
998 | info.addr = apanel_addr; | |
999 | strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); | |
1000 | i2c_new_device(&priv->adapter, &info); | |
1001 | } | |
8eacfceb | 1002 | |
e7198fbf JD |
1003 | if (dmi_name_in_vendors("FUJITSU")) |
1004 | dmi_walk(dmi_check_onboard_devices, &priv->adapter); | |
e7198fbf | 1005 | } |
8eacfceb JD |
1006 | #else |
1007 | static void __init input_apanel_init(void) {} | |
0b255e92 | 1008 | static void i801_probe_optional_slaves(struct i801_priv *priv) {} |
8eacfceb | 1009 | #endif /* CONFIG_X86 && CONFIG_DMI */ |
e7198fbf | 1010 | |
79e3e5b8 JD |
1011 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
1012 | defined CONFIG_DMI | |
3ad7ea18 JD |
1013 | static struct i801_mux_config i801_mux_config_asus_z8_d12 = { |
1014 | .gpio_chip = "gpio_ich", | |
1015 | .values = { 0x02, 0x03 }, | |
1016 | .n_values = 2, | |
1017 | .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, | |
1018 | .gpios = { 52, 53 }, | |
1019 | .n_gpios = 2, | |
1020 | }; | |
1021 | ||
1022 | static struct i801_mux_config i801_mux_config_asus_z8_d18 = { | |
1023 | .gpio_chip = "gpio_ich", | |
1024 | .values = { 0x02, 0x03, 0x01 }, | |
1025 | .n_values = 3, | |
1026 | .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, | |
1027 | .gpios = { 52, 53 }, | |
1028 | .n_gpios = 2, | |
1029 | }; | |
1030 | ||
0b255e92 | 1031 | static const struct dmi_system_id mux_dmi_table[] = { |
3ad7ea18 JD |
1032 | { |
1033 | .matches = { | |
1034 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1035 | DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), | |
1036 | }, | |
1037 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1038 | }, | |
1039 | { | |
1040 | .matches = { | |
1041 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1042 | DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), | |
1043 | }, | |
1044 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1045 | }, | |
1046 | { | |
1047 | .matches = { | |
1048 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1049 | DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), | |
1050 | }, | |
1051 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1052 | }, | |
1053 | { | |
1054 | .matches = { | |
1055 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1056 | DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), | |
1057 | }, | |
1058 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1059 | }, | |
1060 | { | |
1061 | .matches = { | |
1062 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1063 | DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), | |
1064 | }, | |
1065 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1066 | }, | |
1067 | { | |
1068 | .matches = { | |
1069 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1070 | DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), | |
1071 | }, | |
1072 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1073 | }, | |
1074 | { | |
1075 | .matches = { | |
1076 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1077 | DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), | |
1078 | }, | |
1079 | .driver_data = &i801_mux_config_asus_z8_d18, | |
1080 | }, | |
1081 | { | |
1082 | .matches = { | |
1083 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1084 | DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), | |
1085 | }, | |
1086 | .driver_data = &i801_mux_config_asus_z8_d18, | |
1087 | }, | |
1088 | { | |
1089 | .matches = { | |
1090 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1091 | DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), | |
1092 | }, | |
1093 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1094 | }, | |
1095 | { } | |
1096 | }; | |
1097 | ||
3ad7ea18 | 1098 | /* Setup multiplexing if needed */ |
0b255e92 | 1099 | static int i801_add_mux(struct i801_priv *priv) |
3ad7ea18 JD |
1100 | { |
1101 | struct device *dev = &priv->adapter.dev; | |
1102 | const struct i801_mux_config *mux_config; | |
3ad7ea18 | 1103 | struct i2c_mux_gpio_platform_data gpio_data; |
f82b8626 | 1104 | int err; |
3ad7ea18 JD |
1105 | |
1106 | if (!priv->mux_drvdata) | |
1107 | return 0; | |
1108 | mux_config = priv->mux_drvdata; | |
1109 | ||
3ad7ea18 JD |
1110 | /* Prepare the platform data */ |
1111 | memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); | |
1112 | gpio_data.parent = priv->adapter.nr; | |
1113 | gpio_data.values = mux_config->values; | |
1114 | gpio_data.n_values = mux_config->n_values; | |
1115 | gpio_data.classes = mux_config->classes; | |
f82b8626 JD |
1116 | gpio_data.gpio_chip = mux_config->gpio_chip; |
1117 | gpio_data.gpios = mux_config->gpios; | |
3ad7ea18 JD |
1118 | gpio_data.n_gpios = mux_config->n_gpios; |
1119 | gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; | |
1120 | ||
1121 | /* Register the mux device */ | |
1122 | priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", | |
f82b8626 | 1123 | PLATFORM_DEVID_AUTO, &gpio_data, |
3ad7ea18 JD |
1124 | sizeof(struct i2c_mux_gpio_platform_data)); |
1125 | if (IS_ERR(priv->mux_pdev)) { | |
1126 | err = PTR_ERR(priv->mux_pdev); | |
1127 | priv->mux_pdev = NULL; | |
1128 | dev_err(dev, "Failed to register i2c-mux-gpio device\n"); | |
1129 | return err; | |
1130 | } | |
1131 | ||
1132 | return 0; | |
1133 | } | |
1134 | ||
0b255e92 | 1135 | static void i801_del_mux(struct i801_priv *priv) |
3ad7ea18 JD |
1136 | { |
1137 | if (priv->mux_pdev) | |
1138 | platform_device_unregister(priv->mux_pdev); | |
1139 | } | |
1140 | ||
0b255e92 | 1141 | static unsigned int i801_get_adapter_class(struct i801_priv *priv) |
3ad7ea18 JD |
1142 | { |
1143 | const struct dmi_system_id *id; | |
1144 | const struct i801_mux_config *mux_config; | |
1145 | unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1146 | int i; | |
1147 | ||
1148 | id = dmi_first_match(mux_dmi_table); | |
1149 | if (id) { | |
28901f57 | 1150 | /* Remove branch classes from trunk */ |
3ad7ea18 JD |
1151 | mux_config = id->driver_data; |
1152 | for (i = 0; i < mux_config->n_values; i++) | |
1153 | class &= ~mux_config->classes[i]; | |
1154 | ||
1155 | /* Remember for later */ | |
1156 | priv->mux_drvdata = mux_config; | |
1157 | } | |
1158 | ||
1159 | return class; | |
1160 | } | |
1161 | #else | |
1162 | static inline int i801_add_mux(struct i801_priv *priv) { return 0; } | |
1163 | static inline void i801_del_mux(struct i801_priv *priv) { } | |
1164 | ||
1165 | static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) | |
1166 | { | |
1167 | return I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1168 | } | |
1169 | #endif | |
1170 | ||
94246930 MW |
1171 | static const struct itco_wdt_platform_data tco_platform_data = { |
1172 | .name = "Intel PCH", | |
1173 | .version = 4, | |
1174 | }; | |
1175 | ||
1176 | static DEFINE_SPINLOCK(p2sb_spinlock); | |
1177 | ||
1178 | static void i801_add_tco(struct i801_priv *priv) | |
1179 | { | |
1180 | struct pci_dev *pci_dev = priv->pci_dev; | |
1181 | struct resource tco_res[3], *res; | |
1182 | struct platform_device *pdev; | |
1183 | unsigned int devfn; | |
1184 | u32 tco_base, tco_ctl; | |
1185 | u32 base_addr, ctrl_val; | |
1186 | u64 base64_addr; | |
1187 | ||
1188 | if (!(priv->features & FEATURE_TCO)) | |
1189 | return; | |
1190 | ||
1191 | pci_read_config_dword(pci_dev, TCOBASE, &tco_base); | |
1192 | pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); | |
1193 | if (!(tco_ctl & TCOCTL_EN)) | |
1194 | return; | |
1195 | ||
1196 | memset(tco_res, 0, sizeof(tco_res)); | |
1197 | ||
1198 | res = &tco_res[ICH_RES_IO_TCO]; | |
1199 | res->start = tco_base & ~1; | |
1200 | res->end = res->start + 32 - 1; | |
1201 | res->flags = IORESOURCE_IO; | |
1202 | ||
1203 | /* | |
1204 | * Power Management registers. | |
1205 | */ | |
1206 | devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2); | |
1207 | pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr); | |
1208 | ||
1209 | res = &tco_res[ICH_RES_IO_SMI]; | |
1210 | res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF; | |
1211 | res->end = res->start + 3; | |
1212 | res->flags = IORESOURCE_IO; | |
1213 | ||
1214 | /* | |
1215 | * Enable the ACPI I/O space. | |
1216 | */ | |
1217 | pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val); | |
1218 | ctrl_val |= ACPICTRL_EN; | |
1219 | pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val); | |
1220 | ||
1221 | /* | |
1222 | * We must access the NO_REBOOT bit over the Primary to Sideband | |
1223 | * bridge (P2SB). The BIOS prevents the P2SB device from being | |
1224 | * enumerated by the PCI subsystem, so we need to unhide/hide it | |
1225 | * to lookup the P2SB BAR. | |
1226 | */ | |
1227 | spin_lock(&p2sb_spinlock); | |
1228 | ||
1229 | devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); | |
1230 | ||
1231 | /* Unhide the P2SB device */ | |
1232 | pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); | |
1233 | ||
1234 | pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); | |
1235 | base64_addr = base_addr & 0xfffffff0; | |
1236 | ||
1237 | pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); | |
1238 | base64_addr |= (u64)base_addr << 32; | |
1239 | ||
1240 | /* Hide the P2SB device */ | |
1241 | pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1); | |
1242 | spin_unlock(&p2sb_spinlock); | |
1243 | ||
1244 | res = &tco_res[ICH_RES_MEM_OFF]; | |
1245 | res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; | |
1246 | res->end = res->start + 3; | |
1247 | res->flags = IORESOURCE_MEM; | |
1248 | ||
1249 | pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, | |
1250 | tco_res, 3, &tco_platform_data, | |
1251 | sizeof(tco_platform_data)); | |
1252 | if (IS_ERR(pdev)) { | |
1253 | dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); | |
1254 | return; | |
1255 | } | |
1256 | ||
1257 | priv->tco_pdev = pdev; | |
1258 | } | |
1259 | ||
0b255e92 | 1260 | static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) |
1da177e4 | 1261 | { |
02dd7ae2 | 1262 | unsigned char temp; |
adff687d | 1263 | int err, i; |
0cd96eb0 DW |
1264 | struct i801_priv *priv; |
1265 | ||
1621c59d | 1266 | priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); |
0cd96eb0 DW |
1267 | if (!priv) |
1268 | return -ENOMEM; | |
1269 | ||
1270 | i2c_set_adapdata(&priv->adapter, priv); | |
1271 | priv->adapter.owner = THIS_MODULE; | |
3ad7ea18 | 1272 | priv->adapter.class = i801_get_adapter_class(priv); |
0cd96eb0 | 1273 | priv->adapter.algo = &smbus_algorithm; |
8eb5c87a DB |
1274 | priv->adapter.dev.parent = &dev->dev; |
1275 | ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); | |
1276 | priv->adapter.retries = 3; | |
1da177e4 | 1277 | |
0cd96eb0 | 1278 | priv->pci_dev = dev; |
250d1bd3 | 1279 | switch (dev->device) { |
94246930 MW |
1280 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: |
1281 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: | |
1a1503c5 AY |
1282 | case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: |
1283 | case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: | |
84d7f2eb | 1284 | case PCI_DEVICE_ID_INTEL_DNV_SMBUS: |
94246930 MW |
1285 | priv->features |= FEATURE_I2C_BLOCK_READ; |
1286 | priv->features |= FEATURE_IRQ; | |
1287 | priv->features |= FEATURE_SMBUS_PEC; | |
1288 | priv->features |= FEATURE_BLOCK_BUFFER; | |
1289 | priv->features |= FEATURE_TCO; | |
1290 | break; | |
1291 | ||
e7198fbf JD |
1292 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: |
1293 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: | |
1294 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: | |
a3fc0ff0 JR |
1295 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: |
1296 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: | |
1297 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: | |
e7198fbf JD |
1298 | priv->features |= FEATURE_IDF; |
1299 | /* fall through */ | |
e0e8398c | 1300 | default: |
0cd96eb0 | 1301 | priv->features |= FEATURE_I2C_BLOCK_READ; |
6676a847 | 1302 | priv->features |= FEATURE_IRQ; |
6342064c JD |
1303 | /* fall through */ |
1304 | case PCI_DEVICE_ID_INTEL_82801DB_3: | |
0cd96eb0 DW |
1305 | priv->features |= FEATURE_SMBUS_PEC; |
1306 | priv->features |= FEATURE_BLOCK_BUFFER; | |
e0e8398c JD |
1307 | /* fall through */ |
1308 | case PCI_DEVICE_ID_INTEL_82801CA_3: | |
1309 | case PCI_DEVICE_ID_INTEL_82801BA_2: | |
1310 | case PCI_DEVICE_ID_INTEL_82801AB_3: | |
1311 | case PCI_DEVICE_ID_INTEL_82801AA_3: | |
250d1bd3 | 1312 | break; |
250d1bd3 | 1313 | } |
02dd7ae2 | 1314 | |
adff687d JD |
1315 | /* Disable features on user request */ |
1316 | for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { | |
0cd96eb0 | 1317 | if (priv->features & disable_features & (1 << i)) |
adff687d JD |
1318 | dev_notice(&dev->dev, "%s disabled by user\n", |
1319 | i801_feature_names[i]); | |
1320 | } | |
0cd96eb0 | 1321 | priv->features &= ~disable_features; |
adff687d | 1322 | |
fef220da | 1323 | err = pcim_enable_device(dev); |
02dd7ae2 JD |
1324 | if (err) { |
1325 | dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", | |
1326 | err); | |
fef220da | 1327 | return err; |
02dd7ae2 | 1328 | } |
fef220da | 1329 | pcim_pin_device(dev); |
02dd7ae2 JD |
1330 | |
1331 | /* Determine the address of the SMBus area */ | |
0cd96eb0 DW |
1332 | priv->smba = pci_resource_start(dev, SMBBAR); |
1333 | if (!priv->smba) { | |
9cbbf3dc JN |
1334 | dev_err(&dev->dev, |
1335 | "SMBus base address uninitialized, upgrade BIOS\n"); | |
fef220da | 1336 | return -ENODEV; |
02dd7ae2 JD |
1337 | } |
1338 | ||
54fb4a05 | 1339 | err = acpi_check_resource_conflict(&dev->resource[SMBBAR]); |
18669eab | 1340 | if (err) { |
fef220da | 1341 | return -ENODEV; |
18669eab | 1342 | } |
54fb4a05 | 1343 | |
fef220da JN |
1344 | err = pcim_iomap_regions(dev, 1 << SMBBAR, |
1345 | dev_driver_string(&dev->dev)); | |
02dd7ae2 | 1346 | if (err) { |
9cbbf3dc JN |
1347 | dev_err(&dev->dev, |
1348 | "Failed to request SMBus region 0x%lx-0x%Lx\n", | |
1349 | priv->smba, | |
598736c5 | 1350 | (unsigned long long)pci_resource_end(dev, SMBBAR)); |
fef220da | 1351 | return err; |
02dd7ae2 JD |
1352 | } |
1353 | ||
0cd96eb0 DW |
1354 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); |
1355 | priv->original_hstcfg = temp; | |
02dd7ae2 JD |
1356 | temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ |
1357 | if (!(temp & SMBHSTCFG_HST_EN)) { | |
1358 | dev_info(&dev->dev, "Enabling SMBus device\n"); | |
1359 | temp |= SMBHSTCFG_HST_EN; | |
1360 | } | |
0cd96eb0 | 1361 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); |
02dd7ae2 | 1362 | |
636752bc | 1363 | if (temp & SMBHSTCFG_SMB_SMI_EN) { |
02dd7ae2 | 1364 | dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); |
636752bc DK |
1365 | /* Disable SMBus interrupt feature if SMBus using SMI# */ |
1366 | priv->features &= ~FEATURE_IRQ; | |
636752bc | 1367 | } |
1da177e4 | 1368 | |
a0921b6c | 1369 | /* Clear special mode bits */ |
0cd96eb0 DW |
1370 | if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) |
1371 | outb_p(inb_p(SMBAUXCTL(priv)) & | |
1372 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
a0921b6c | 1373 | |
b3b8df97 JD |
1374 | /* Default timeout in interrupt mode: 200 ms */ |
1375 | priv->adapter.timeout = HZ / 5; | |
1376 | ||
aeb8a3d1 JD |
1377 | if (priv->features & FEATURE_IRQ) { |
1378 | u16 pcictl, pcists; | |
1379 | ||
1380 | /* Complain if an interrupt is already pending */ | |
1381 | pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); | |
1382 | if (pcists & SMBPCISTS_INTS) | |
1383 | dev_warn(&dev->dev, "An interrupt is pending!\n"); | |
1384 | ||
1385 | /* Check if interrupts have been disabled */ | |
1386 | pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); | |
1387 | if (pcictl & SMBPCICTL_INTDIS) { | |
1388 | dev_info(&dev->dev, "Interrupts are disabled\n"); | |
1389 | priv->features &= ~FEATURE_IRQ; | |
1390 | } | |
1391 | } | |
1392 | ||
636752bc DK |
1393 | if (priv->features & FEATURE_IRQ) { |
1394 | init_waitqueue_head(&priv->waitq); | |
1395 | ||
1621c59d JN |
1396 | err = devm_request_irq(&dev->dev, dev->irq, i801_isr, |
1397 | IRQF_SHARED, | |
1398 | dev_driver_string(&dev->dev), priv); | |
636752bc DK |
1399 | if (err) { |
1400 | dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", | |
1401 | dev->irq, err); | |
ae944717 | 1402 | priv->features &= ~FEATURE_IRQ; |
636752bc DK |
1403 | } |
1404 | } | |
ae944717 JD |
1405 | dev_info(&dev->dev, "SMBus using %s\n", |
1406 | priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); | |
636752bc | 1407 | |
94246930 MW |
1408 | i801_add_tco(priv); |
1409 | ||
0cd96eb0 DW |
1410 | snprintf(priv->adapter.name, sizeof(priv->adapter.name), |
1411 | "SMBus I801 adapter at %04lx", priv->smba); | |
1412 | err = i2c_add_adapter(&priv->adapter); | |
02dd7ae2 JD |
1413 | if (err) { |
1414 | dev_err(&dev->dev, "Failed to add SMBus adapter\n"); | |
fef220da | 1415 | return err; |
02dd7ae2 | 1416 | } |
1561bfe5 | 1417 | |
e7198fbf | 1418 | i801_probe_optional_slaves(priv); |
3ad7ea18 JD |
1419 | /* We ignore errors - multiplexing is optional */ |
1420 | i801_add_mux(priv); | |
1561bfe5 | 1421 | |
0cd96eb0 | 1422 | pci_set_drvdata(dev, priv); |
636752bc | 1423 | |
a7401ca5 JN |
1424 | pm_runtime_set_autosuspend_delay(&dev->dev, 1000); |
1425 | pm_runtime_use_autosuspend(&dev->dev); | |
1426 | pm_runtime_put_autosuspend(&dev->dev); | |
1427 | pm_runtime_allow(&dev->dev); | |
1428 | ||
d6fcb3b9 | 1429 | return 0; |
1da177e4 LT |
1430 | } |
1431 | ||
0b255e92 | 1432 | static void i801_remove(struct pci_dev *dev) |
1da177e4 | 1433 | { |
0cd96eb0 DW |
1434 | struct i801_priv *priv = pci_get_drvdata(dev); |
1435 | ||
a7401ca5 JN |
1436 | pm_runtime_forbid(&dev->dev); |
1437 | pm_runtime_get_noresume(&dev->dev); | |
1438 | ||
3ad7ea18 | 1439 | i801_del_mux(priv); |
0cd96eb0 DW |
1440 | i2c_del_adapter(&priv->adapter); |
1441 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); | |
636752bc | 1442 | |
94246930 MW |
1443 | platform_device_unregister(priv->tco_pdev); |
1444 | ||
d6fcb3b9 DR |
1445 | /* |
1446 | * do not call pci_disable_device(dev) since it can cause hard hangs on | |
1447 | * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) | |
1448 | */ | |
1da177e4 LT |
1449 | } |
1450 | ||
a5aaea37 | 1451 | #ifdef CONFIG_PM |
2ee73c48 | 1452 | static int i801_suspend(struct device *dev) |
a5aaea37 | 1453 | { |
2ee73c48 JN |
1454 | struct pci_dev *pci_dev = to_pci_dev(dev); |
1455 | struct i801_priv *priv = pci_get_drvdata(pci_dev); | |
0cd96eb0 | 1456 | |
2ee73c48 | 1457 | pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg); |
a5aaea37 JD |
1458 | return 0; |
1459 | } | |
1460 | ||
2ee73c48 | 1461 | static int i801_resume(struct device *dev) |
a5aaea37 | 1462 | { |
f85da3f5 | 1463 | return 0; |
a5aaea37 | 1464 | } |
a5aaea37 JD |
1465 | #endif |
1466 | ||
2ee73c48 JN |
1467 | static UNIVERSAL_DEV_PM_OPS(i801_pm_ops, i801_suspend, |
1468 | i801_resume, NULL); | |
1469 | ||
1da177e4 LT |
1470 | static struct pci_driver i801_driver = { |
1471 | .name = "i801_smbus", | |
1472 | .id_table = i801_ids, | |
1473 | .probe = i801_probe, | |
0b255e92 | 1474 | .remove = i801_remove, |
2ee73c48 JN |
1475 | .driver = { |
1476 | .pm = &i801_pm_ops, | |
1477 | }, | |
1da177e4 LT |
1478 | }; |
1479 | ||
1480 | static int __init i2c_i801_init(void) | |
1481 | { | |
6aa1464d JD |
1482 | if (dmi_name_in_vendors("FUJITSU")) |
1483 | input_apanel_init(); | |
1da177e4 LT |
1484 | return pci_register_driver(&i801_driver); |
1485 | } | |
1486 | ||
1487 | static void __exit i2c_i801_exit(void) | |
1488 | { | |
1489 | pci_unregister_driver(&i801_driver); | |
1490 | } | |
1491 | ||
7c81c60f | 1492 | MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>"); |
1da177e4 LT |
1493 | MODULE_DESCRIPTION("I801 SMBus driver"); |
1494 | MODULE_LICENSE("GPL"); | |
1495 | ||
1496 | module_init(i2c_i801_init); | |
1497 | module_exit(i2c_i801_exit); |