Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, |
3 | Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker | |
4 | <mdsxyz123@yahoo.com> | |
cf898dc5 | 5 | Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org> |
0cd96eb0 DW |
6 | Copyright (C) 2010 Intel Corporation, |
7 | David Woodhouse <dwmw2@infradead.org> | |
1da177e4 LT |
8 | |
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
24 | /* | |
ae7b0497 JD |
25 | Supports the following Intel I/O Controller Hubs (ICH): |
26 | ||
27 | I/O Block I2C | |
28 | region SMBus Block proc. block | |
29 | Chip name PCI ID size PEC buffer call read | |
30 | ---------------------------------------------------------------------- | |
31 | 82801AA (ICH) 0x2413 16 no no no no | |
32 | 82801AB (ICH0) 0x2423 16 no no no no | |
33 | 82801BA (ICH2) 0x2443 16 no no no no | |
34 | 82801CA (ICH3) 0x2483 32 soft no no no | |
35 | 82801DB (ICH4) 0x24c3 32 hard yes no no | |
36 | 82801E (ICH5) 0x24d3 32 hard yes yes yes | |
37 | 6300ESB 0x25a4 32 hard yes yes yes | |
38 | 82801F (ICH6) 0x266a 32 hard yes yes yes | |
39 | 6310ESB/6320ESB 0x269b 32 hard yes yes yes | |
40 | 82801G (ICH7) 0x27da 32 hard yes yes yes | |
41 | 82801H (ICH8) 0x283e 32 hard yes yes yes | |
42 | 82801I (ICH9) 0x2930 32 hard yes yes yes | |
cb04e95b | 43 | EP80579 (Tolapai) 0x5032 32 hard yes yes yes |
d28dc711 GJ |
44 | ICH10 0x3a30 32 hard yes yes yes |
45 | ICH10 0x3a60 32 hard yes yes yes | |
cb04e95b | 46 | 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes |
662cda8a | 47 | 6 Series (PCH) 0x1c22 32 hard yes yes yes |
e30d9859 | 48 | Patsburg (PCH) 0x1d22 32 hard yes yes yes |
55fee8d7 DW |
49 | Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes |
50 | Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes | |
51 | Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes | |
662cda8a | 52 | DH89xxCC (PCH) 0x2330 32 hard yes yes yes |
ae7b0497 JD |
53 | |
54 | Features supported by this driver: | |
55 | Software PEC no | |
56 | Hardware PEC yes | |
57 | Block buffer yes | |
58 | Block process call transaction no | |
6342064c | 59 | I2C block read transaction yes (doesn't use the block buffer) |
55fee8d7 | 60 | Slave mode no |
ae7b0497 JD |
61 | |
62 | See the file Documentation/i2c/busses/i2c-i801 for details. | |
1da177e4 LT |
63 | */ |
64 | ||
1da177e4 LT |
65 | #include <linux/module.h> |
66 | #include <linux/pci.h> | |
67 | #include <linux/kernel.h> | |
68 | #include <linux/stddef.h> | |
69 | #include <linux/delay.h> | |
1da177e4 LT |
70 | #include <linux/ioport.h> |
71 | #include <linux/init.h> | |
72 | #include <linux/i2c.h> | |
54fb4a05 | 73 | #include <linux/acpi.h> |
1561bfe5 | 74 | #include <linux/io.h> |
fa5bfab7 | 75 | #include <linux/dmi.h> |
665a96b7 | 76 | #include <linux/slab.h> |
1da177e4 | 77 | |
1da177e4 | 78 | /* I801 SMBus address offsets */ |
0cd96eb0 DW |
79 | #define SMBHSTSTS(p) (0 + (p)->smba) |
80 | #define SMBHSTCNT(p) (2 + (p)->smba) | |
81 | #define SMBHSTCMD(p) (3 + (p)->smba) | |
82 | #define SMBHSTADD(p) (4 + (p)->smba) | |
83 | #define SMBHSTDAT0(p) (5 + (p)->smba) | |
84 | #define SMBHSTDAT1(p) (6 + (p)->smba) | |
85 | #define SMBBLKDAT(p) (7 + (p)->smba) | |
86 | #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ | |
87 | #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ | |
88 | #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ | |
1da177e4 LT |
89 | |
90 | /* PCI Address Constants */ | |
6dcc19df | 91 | #define SMBBAR 4 |
1da177e4 | 92 | #define SMBHSTCFG 0x040 |
1da177e4 LT |
93 | |
94 | /* Host configuration bits for SMBHSTCFG */ | |
95 | #define SMBHSTCFG_HST_EN 1 | |
96 | #define SMBHSTCFG_SMB_SMI_EN 2 | |
97 | #define SMBHSTCFG_I2C_EN 4 | |
98 | ||
25985edc | 99 | /* Auxiliary control register bits, ICH4+ only */ |
ca8b9e32 OR |
100 | #define SMBAUXCTL_CRC 1 |
101 | #define SMBAUXCTL_E32B 2 | |
102 | ||
103 | /* kill bit for SMBHSTCNT */ | |
104 | #define SMBHSTCNT_KILL 2 | |
105 | ||
1da177e4 LT |
106 | /* Other settings */ |
107 | #define MAX_TIMEOUT 100 | |
108 | #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */ | |
109 | ||
110 | /* I801 command constants */ | |
111 | #define I801_QUICK 0x00 | |
112 | #define I801_BYTE 0x04 | |
113 | #define I801_BYTE_DATA 0x08 | |
114 | #define I801_WORD_DATA 0x0C | |
ae7b0497 | 115 | #define I801_PROC_CALL 0x10 /* unimplemented */ |
1da177e4 | 116 | #define I801_BLOCK_DATA 0x14 |
6342064c | 117 | #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ |
1da177e4 | 118 | #define I801_BLOCK_LAST 0x34 |
6342064c | 119 | #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */ |
1da177e4 | 120 | #define I801_START 0x40 |
ae7b0497 | 121 | #define I801_PEC_EN 0x80 /* ICH3 and later */ |
1da177e4 | 122 | |
ca8b9e32 OR |
123 | /* I801 Hosts Status register bits */ |
124 | #define SMBHSTSTS_BYTE_DONE 0x80 | |
125 | #define SMBHSTSTS_INUSE_STS 0x40 | |
126 | #define SMBHSTSTS_SMBALERT_STS 0x20 | |
127 | #define SMBHSTSTS_FAILED 0x10 | |
128 | #define SMBHSTSTS_BUS_ERR 0x08 | |
129 | #define SMBHSTSTS_DEV_ERR 0x04 | |
130 | #define SMBHSTSTS_INTR 0x02 | |
131 | #define SMBHSTSTS_HOST_BUSY 0x01 | |
1da177e4 | 132 | |
cf898dc5 JD |
133 | #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \ |
134 | SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \ | |
135 | SMBHSTSTS_INTR) | |
136 | ||
a6e5e2be JD |
137 | /* Older devices have their ID defined in <linux/pci_ids.h> */ |
138 | #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 | |
139 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 | |
5e152b4c | 140 | #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 |
55fee8d7 DW |
141 | /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ |
142 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 | |
143 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 | |
144 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 | |
a6e5e2be JD |
145 | #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 |
146 | #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 | |
55fee8d7 | 147 | |
0cd96eb0 DW |
148 | struct i801_priv { |
149 | struct i2c_adapter adapter; | |
150 | unsigned long smba; | |
151 | unsigned char original_hstcfg; | |
152 | struct pci_dev *pci_dev; | |
153 | unsigned int features; | |
154 | }; | |
155 | ||
d6072f84 | 156 | static struct pci_driver i801_driver; |
369f6f4a JD |
157 | |
158 | #define FEATURE_SMBUS_PEC (1 << 0) | |
159 | #define FEATURE_BLOCK_BUFFER (1 << 1) | |
160 | #define FEATURE_BLOCK_PROC (1 << 2) | |
161 | #define FEATURE_I2C_BLOCK_READ (1 << 3) | |
1da177e4 | 162 | |
adff687d JD |
163 | static const char *i801_feature_names[] = { |
164 | "SMBus PEC", | |
165 | "Block buffer", | |
166 | "Block process call", | |
167 | "I2C block read", | |
168 | }; | |
169 | ||
170 | static unsigned int disable_features; | |
171 | module_param(disable_features, uint, S_IRUGO | S_IWUSR); | |
172 | MODULE_PARM_DESC(disable_features, "Disable selected driver features"); | |
173 | ||
cf898dc5 JD |
174 | /* Make sure the SMBus host is ready to start transmitting. |
175 | Return 0 if it is, -EBUSY if it is not. */ | |
0cd96eb0 | 176 | static int i801_check_pre(struct i801_priv *priv) |
1da177e4 | 177 | { |
2b73809d | 178 | int status; |
1da177e4 | 179 | |
0cd96eb0 | 180 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 | 181 | if (status & SMBHSTSTS_HOST_BUSY) { |
0cd96eb0 | 182 | dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); |
cf898dc5 JD |
183 | return -EBUSY; |
184 | } | |
185 | ||
186 | status &= STATUS_FLAGS; | |
187 | if (status) { | |
0cd96eb0 | 188 | dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", |
2b73809d | 189 | status); |
0cd96eb0 DW |
190 | outb_p(status, SMBHSTSTS(priv)); |
191 | status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; | |
cf898dc5 | 192 | if (status) { |
0cd96eb0 | 193 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
194 | "Failed clearing status flags (%02x)\n", |
195 | status); | |
97140342 | 196 | return -EBUSY; |
1da177e4 LT |
197 | } |
198 | } | |
199 | ||
cf898dc5 JD |
200 | return 0; |
201 | } | |
1da177e4 | 202 | |
cf898dc5 | 203 | /* Convert the status register to an error code, and clear it. */ |
0cd96eb0 | 204 | static int i801_check_post(struct i801_priv *priv, int status, int timeout) |
cf898dc5 JD |
205 | { |
206 | int result = 0; | |
1da177e4 LT |
207 | |
208 | /* If the SMBus is still busy, we give up */ | |
cf898dc5 | 209 | if (timeout) { |
0cd96eb0 | 210 | dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); |
ca8b9e32 | 211 | /* try to stop the current command */ |
0cd96eb0 DW |
212 | dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); |
213 | outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, | |
214 | SMBHSTCNT(priv)); | |
ca8b9e32 | 215 | msleep(1); |
0cd96eb0 DW |
216 | outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), |
217 | SMBHSTCNT(priv)); | |
cf898dc5 JD |
218 | |
219 | /* Check if it worked */ | |
0cd96eb0 | 220 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 JD |
221 | if ((status & SMBHSTSTS_HOST_BUSY) || |
222 | !(status & SMBHSTSTS_FAILED)) | |
0cd96eb0 | 223 | dev_err(&priv->pci_dev->dev, |
cf898dc5 | 224 | "Failed terminating the transaction\n"); |
0cd96eb0 | 225 | outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); |
cf898dc5 | 226 | return -ETIMEDOUT; |
1da177e4 LT |
227 | } |
228 | ||
2b73809d | 229 | if (status & SMBHSTSTS_FAILED) { |
97140342 | 230 | result = -EIO; |
0cd96eb0 | 231 | dev_err(&priv->pci_dev->dev, "Transaction failed\n"); |
cf898dc5 JD |
232 | } |
233 | if (status & SMBHSTSTS_DEV_ERR) { | |
234 | result = -ENXIO; | |
0cd96eb0 | 235 | dev_dbg(&priv->pci_dev->dev, "No response\n"); |
1da177e4 | 236 | } |
2b73809d | 237 | if (status & SMBHSTSTS_BUS_ERR) { |
dcb5c923 | 238 | result = -EAGAIN; |
0cd96eb0 | 239 | dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); |
1da177e4 LT |
240 | } |
241 | ||
cf898dc5 JD |
242 | if (result) { |
243 | /* Clear error flags */ | |
0cd96eb0 DW |
244 | outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv)); |
245 | status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; | |
cf898dc5 | 246 | if (status) { |
0cd96eb0 | 247 | dev_warn(&priv->pci_dev->dev, "Failed clearing status " |
cf898dc5 JD |
248 | "flags at end of transaction (%02x)\n", |
249 | status); | |
250 | } | |
1da177e4 LT |
251 | } |
252 | ||
1da177e4 LT |
253 | return result; |
254 | } | |
255 | ||
0cd96eb0 | 256 | static int i801_transaction(struct i801_priv *priv, int xact) |
cf898dc5 JD |
257 | { |
258 | int status; | |
259 | int result; | |
260 | int timeout = 0; | |
261 | ||
0cd96eb0 | 262 | result = i801_check_pre(priv); |
cf898dc5 JD |
263 | if (result < 0) |
264 | return result; | |
265 | ||
266 | /* the current contents of SMBHSTCNT can be overwritten, since PEC, | |
267 | * INTREN, SMBSCMD are passed in xact */ | |
0cd96eb0 | 268 | outb_p(xact | I801_START, SMBHSTCNT(priv)); |
cf898dc5 JD |
269 | |
270 | /* We will always wait for a fraction of a second! */ | |
271 | do { | |
272 | msleep(1); | |
0cd96eb0 | 273 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 JD |
274 | } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT)); |
275 | ||
0cd96eb0 | 276 | result = i801_check_post(priv, status, timeout > MAX_TIMEOUT); |
cf898dc5 JD |
277 | if (result < 0) |
278 | return result; | |
279 | ||
0cd96eb0 | 280 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); |
cf898dc5 JD |
281 | return 0; |
282 | } | |
283 | ||
ca8b9e32 | 284 | /* wait for INTR bit as advised by Intel */ |
0cd96eb0 | 285 | static void i801_wait_hwpec(struct i801_priv *priv) |
ca8b9e32 OR |
286 | { |
287 | int timeout = 0; | |
2b73809d | 288 | int status; |
ca8b9e32 OR |
289 | |
290 | do { | |
291 | msleep(1); | |
0cd96eb0 | 292 | status = inb_p(SMBHSTSTS(priv)); |
2b73809d | 293 | } while ((!(status & SMBHSTSTS_INTR)) |
ca8b9e32 OR |
294 | && (timeout++ < MAX_TIMEOUT)); |
295 | ||
4ccc28f7 | 296 | if (timeout > MAX_TIMEOUT) |
0cd96eb0 | 297 | dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n"); |
4ccc28f7 | 298 | |
0cd96eb0 | 299 | outb_p(status, SMBHSTSTS(priv)); |
ca8b9e32 OR |
300 | } |
301 | ||
0cd96eb0 DW |
302 | static int i801_block_transaction_by_block(struct i801_priv *priv, |
303 | union i2c_smbus_data *data, | |
7edcb9ab OR |
304 | char read_write, int hwpec) |
305 | { | |
306 | int i, len; | |
97140342 | 307 | int status; |
7edcb9ab | 308 | |
0cd96eb0 | 309 | inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ |
7edcb9ab OR |
310 | |
311 | /* Use 32-byte buffer to process this transaction */ | |
312 | if (read_write == I2C_SMBUS_WRITE) { | |
313 | len = data->block[0]; | |
0cd96eb0 | 314 | outb_p(len, SMBHSTDAT0(priv)); |
7edcb9ab | 315 | for (i = 0; i < len; i++) |
0cd96eb0 | 316 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
7edcb9ab OR |
317 | } |
318 | ||
0cd96eb0 | 319 | status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 | |
97140342 DB |
320 | I801_PEC_EN * hwpec); |
321 | if (status) | |
322 | return status; | |
7edcb9ab OR |
323 | |
324 | if (read_write == I2C_SMBUS_READ) { | |
0cd96eb0 | 325 | len = inb_p(SMBHSTDAT0(priv)); |
7edcb9ab | 326 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) |
97140342 | 327 | return -EPROTO; |
7edcb9ab OR |
328 | |
329 | data->block[0] = len; | |
330 | for (i = 0; i < len; i++) | |
0cd96eb0 | 331 | data->block[i + 1] = inb_p(SMBBLKDAT(priv)); |
7edcb9ab OR |
332 | } |
333 | return 0; | |
334 | } | |
335 | ||
0cd96eb0 DW |
336 | static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, |
337 | union i2c_smbus_data *data, | |
6342064c JD |
338 | char read_write, int command, |
339 | int hwpec) | |
1da177e4 LT |
340 | { |
341 | int i, len; | |
342 | int smbcmd; | |
2b73809d | 343 | int status; |
cf898dc5 | 344 | int result; |
1da177e4 | 345 | int timeout; |
cf898dc5 | 346 | |
0cd96eb0 | 347 | result = i801_check_pre(priv); |
cf898dc5 JD |
348 | if (result < 0) |
349 | return result; | |
1da177e4 | 350 | |
7edcb9ab | 351 | len = data->block[0]; |
1da177e4 LT |
352 | |
353 | if (read_write == I2C_SMBUS_WRITE) { | |
0cd96eb0 DW |
354 | outb_p(len, SMBHSTDAT0(priv)); |
355 | outb_p(data->block[1], SMBBLKDAT(priv)); | |
1da177e4 LT |
356 | } |
357 | ||
358 | for (i = 1; i <= len; i++) { | |
6342064c JD |
359 | if (i == len && read_write == I2C_SMBUS_READ) { |
360 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) | |
361 | smbcmd = I801_I2C_BLOCK_LAST; | |
362 | else | |
363 | smbcmd = I801_BLOCK_LAST; | |
364 | } else { | |
365 | if (command == I2C_SMBUS_I2C_BLOCK_DATA | |
366 | && read_write == I2C_SMBUS_READ) | |
367 | smbcmd = I801_I2C_BLOCK_DATA; | |
368 | else | |
369 | smbcmd = I801_BLOCK_DATA; | |
370 | } | |
0cd96eb0 | 371 | outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv)); |
1da177e4 | 372 | |
1da177e4 | 373 | if (i == 1) |
0cd96eb0 DW |
374 | outb_p(inb(SMBHSTCNT(priv)) | I801_START, |
375 | SMBHSTCNT(priv)); | |
1da177e4 LT |
376 | |
377 | /* We will always wait for a fraction of a second! */ | |
378 | timeout = 0; | |
379 | do { | |
1da177e4 | 380 | msleep(1); |
0cd96eb0 | 381 | status = inb_p(SMBHSTSTS(priv)); |
3fb21c64 IM |
382 | } while ((!(status & SMBHSTSTS_BYTE_DONE)) |
383 | && (timeout++ < MAX_TIMEOUT)); | |
1da177e4 | 384 | |
0cd96eb0 | 385 | result = i801_check_post(priv, status, timeout > MAX_TIMEOUT); |
cf898dc5 JD |
386 | if (result < 0) |
387 | return result; | |
1da177e4 | 388 | |
6342064c JD |
389 | if (i == 1 && read_write == I2C_SMBUS_READ |
390 | && command != I2C_SMBUS_I2C_BLOCK_DATA) { | |
0cd96eb0 | 391 | len = inb_p(SMBHSTDAT0(priv)); |
cf898dc5 | 392 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { |
0cd96eb0 | 393 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
394 | "Illegal SMBus block read size %d\n", |
395 | len); | |
396 | /* Recover */ | |
0cd96eb0 DW |
397 | while (inb_p(SMBHSTSTS(priv)) & |
398 | SMBHSTSTS_HOST_BUSY) | |
399 | outb_p(SMBHSTSTS_BYTE_DONE, | |
400 | SMBHSTSTS(priv)); | |
401 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); | |
97140342 | 402 | return -EPROTO; |
cf898dc5 | 403 | } |
1da177e4 LT |
404 | data->block[0] = len; |
405 | } | |
406 | ||
407 | /* Retrieve/store value in SMBBLKDAT */ | |
408 | if (read_write == I2C_SMBUS_READ) | |
0cd96eb0 | 409 | data->block[i] = inb_p(SMBBLKDAT(priv)); |
1da177e4 | 410 | if (read_write == I2C_SMBUS_WRITE && i+1 <= len) |
0cd96eb0 | 411 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
1da177e4 | 412 | |
cf898dc5 | 413 | /* signals SMBBLKDAT ready */ |
0cd96eb0 | 414 | outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv)); |
1da177e4 | 415 | } |
cf898dc5 JD |
416 | |
417 | return 0; | |
7edcb9ab | 418 | } |
1da177e4 | 419 | |
0cd96eb0 | 420 | static int i801_set_block_buffer_mode(struct i801_priv *priv) |
7edcb9ab | 421 | { |
0cd96eb0 DW |
422 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); |
423 | if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) | |
97140342 | 424 | return -EIO; |
7edcb9ab OR |
425 | return 0; |
426 | } | |
427 | ||
428 | /* Block transaction function */ | |
0cd96eb0 DW |
429 | static int i801_block_transaction(struct i801_priv *priv, |
430 | union i2c_smbus_data *data, char read_write, | |
7edcb9ab OR |
431 | int command, int hwpec) |
432 | { | |
433 | int result = 0; | |
434 | unsigned char hostc; | |
435 | ||
436 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
437 | if (read_write == I2C_SMBUS_WRITE) { | |
438 | /* set I2C_EN bit in configuration register */ | |
0cd96eb0 DW |
439 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); |
440 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, | |
7edcb9ab | 441 | hostc | SMBHSTCFG_I2C_EN); |
0cd96eb0 DW |
442 | } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { |
443 | dev_err(&priv->pci_dev->dev, | |
6342064c | 444 | "I2C block read is unsupported!\n"); |
97140342 | 445 | return -EOPNOTSUPP; |
7edcb9ab OR |
446 | } |
447 | } | |
448 | ||
6342064c JD |
449 | if (read_write == I2C_SMBUS_WRITE |
450 | || command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
7edcb9ab OR |
451 | if (data->block[0] < 1) |
452 | data->block[0] = 1; | |
453 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) | |
454 | data->block[0] = I2C_SMBUS_BLOCK_MAX; | |
455 | } else { | |
6342064c | 456 | data->block[0] = 32; /* max for SMBus block reads */ |
7edcb9ab OR |
457 | } |
458 | ||
c074c39d JD |
459 | /* Experience has shown that the block buffer can only be used for |
460 | SMBus (not I2C) block transactions, even though the datasheet | |
461 | doesn't mention this limitation. */ | |
0cd96eb0 | 462 | if ((priv->features & FEATURE_BLOCK_BUFFER) |
c074c39d | 463 | && command != I2C_SMBUS_I2C_BLOCK_DATA |
0cd96eb0 DW |
464 | && i801_set_block_buffer_mode(priv) == 0) |
465 | result = i801_block_transaction_by_block(priv, data, | |
466 | read_write, hwpec); | |
7edcb9ab | 467 | else |
0cd96eb0 DW |
468 | result = i801_block_transaction_byte_by_byte(priv, data, |
469 | read_write, | |
6342064c | 470 | command, hwpec); |
7edcb9ab OR |
471 | |
472 | if (result == 0 && hwpec) | |
0cd96eb0 | 473 | i801_wait_hwpec(priv); |
1da177e4 | 474 | |
6342064c JD |
475 | if (command == I2C_SMBUS_I2C_BLOCK_DATA |
476 | && read_write == I2C_SMBUS_WRITE) { | |
1da177e4 | 477 | /* restore saved configuration register value */ |
0cd96eb0 | 478 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); |
1da177e4 LT |
479 | } |
480 | return result; | |
481 | } | |
482 | ||
97140342 | 483 | /* Return negative errno on error. */ |
3fb21c64 | 484 | static s32 i801_access(struct i2c_adapter *adap, u16 addr, |
1da177e4 | 485 | unsigned short flags, char read_write, u8 command, |
3fb21c64 | 486 | int size, union i2c_smbus_data *data) |
1da177e4 | 487 | { |
e8aac4a9 | 488 | int hwpec; |
1da177e4 LT |
489 | int block = 0; |
490 | int ret, xact = 0; | |
0cd96eb0 | 491 | struct i801_priv *priv = i2c_get_adapdata(adap); |
1da177e4 | 492 | |
0cd96eb0 | 493 | hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) |
e8aac4a9 JD |
494 | && size != I2C_SMBUS_QUICK |
495 | && size != I2C_SMBUS_I2C_BLOCK_DATA; | |
1da177e4 LT |
496 | |
497 | switch (size) { | |
498 | case I2C_SMBUS_QUICK: | |
499 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 500 | SMBHSTADD(priv)); |
1da177e4 LT |
501 | xact = I801_QUICK; |
502 | break; | |
503 | case I2C_SMBUS_BYTE: | |
504 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 505 | SMBHSTADD(priv)); |
1da177e4 | 506 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 507 | outb_p(command, SMBHSTCMD(priv)); |
1da177e4 LT |
508 | xact = I801_BYTE; |
509 | break; | |
510 | case I2C_SMBUS_BYTE_DATA: | |
511 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
512 | SMBHSTADD(priv)); |
513 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 514 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 515 | outb_p(data->byte, SMBHSTDAT0(priv)); |
1da177e4 LT |
516 | xact = I801_BYTE_DATA; |
517 | break; | |
518 | case I2C_SMBUS_WORD_DATA: | |
519 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
520 | SMBHSTADD(priv)); |
521 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 522 | if (read_write == I2C_SMBUS_WRITE) { |
0cd96eb0 DW |
523 | outb_p(data->word & 0xff, SMBHSTDAT0(priv)); |
524 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); | |
1da177e4 LT |
525 | } |
526 | xact = I801_WORD_DATA; | |
527 | break; | |
528 | case I2C_SMBUS_BLOCK_DATA: | |
1da177e4 | 529 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
0cd96eb0 DW |
530 | SMBHSTADD(priv)); |
531 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 LT |
532 | block = 1; |
533 | break; | |
6342064c JD |
534 | case I2C_SMBUS_I2C_BLOCK_DATA: |
535 | /* NB: page 240 of ICH5 datasheet shows that the R/#W | |
536 | * bit should be cleared here, even when reading */ | |
0cd96eb0 | 537 | outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); |
6342064c JD |
538 | if (read_write == I2C_SMBUS_READ) { |
539 | /* NB: page 240 of ICH5 datasheet also shows | |
540 | * that DATA1 is the cmd field when reading */ | |
0cd96eb0 | 541 | outb_p(command, SMBHSTDAT1(priv)); |
6342064c | 542 | } else |
0cd96eb0 | 543 | outb_p(command, SMBHSTCMD(priv)); |
6342064c JD |
544 | block = 1; |
545 | break; | |
1da177e4 | 546 | default: |
0cd96eb0 DW |
547 | dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", |
548 | size); | |
97140342 | 549 | return -EOPNOTSUPP; |
1da177e4 LT |
550 | } |
551 | ||
ca8b9e32 | 552 | if (hwpec) /* enable/disable hardware PEC */ |
0cd96eb0 | 553 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); |
ca8b9e32 | 554 | else |
0cd96eb0 DW |
555 | outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), |
556 | SMBAUXCTL(priv)); | |
e8aac4a9 | 557 | |
3fb21c64 | 558 | if (block) |
0cd96eb0 DW |
559 | ret = i801_block_transaction(priv, data, read_write, size, |
560 | hwpec); | |
7edcb9ab | 561 | else |
0cd96eb0 | 562 | ret = i801_transaction(priv, xact | ENABLE_INT9); |
1da177e4 | 563 | |
c79cfbac | 564 | /* Some BIOSes don't like it when PEC is enabled at reboot or resume |
7edcb9ab OR |
565 | time, so we forcibly disable it after every transaction. Turn off |
566 | E32B for the same reason. */ | |
a0921b6c | 567 | if (hwpec || block) |
0cd96eb0 DW |
568 | outb_p(inb_p(SMBAUXCTL(priv)) & |
569 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
c79cfbac | 570 | |
3fb21c64 | 571 | if (block) |
1da177e4 | 572 | return ret; |
3fb21c64 | 573 | if (ret) |
97140342 | 574 | return ret; |
1da177e4 LT |
575 | if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) |
576 | return 0; | |
577 | ||
578 | switch (xact & 0x7f) { | |
579 | case I801_BYTE: /* Result put in SMBHSTDAT0 */ | |
580 | case I801_BYTE_DATA: | |
0cd96eb0 | 581 | data->byte = inb_p(SMBHSTDAT0(priv)); |
1da177e4 LT |
582 | break; |
583 | case I801_WORD_DATA: | |
0cd96eb0 DW |
584 | data->word = inb_p(SMBHSTDAT0(priv)) + |
585 | (inb_p(SMBHSTDAT1(priv)) << 8); | |
1da177e4 LT |
586 | break; |
587 | } | |
588 | return 0; | |
589 | } | |
590 | ||
591 | ||
592 | static u32 i801_func(struct i2c_adapter *adapter) | |
593 | { | |
0cd96eb0 DW |
594 | struct i801_priv *priv = i2c_get_adapdata(adapter); |
595 | ||
1da177e4 | 596 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | |
369f6f4a JD |
597 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | |
598 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | | |
0cd96eb0 DW |
599 | ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | |
600 | ((priv->features & FEATURE_I2C_BLOCK_READ) ? | |
6342064c | 601 | I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); |
1da177e4 LT |
602 | } |
603 | ||
8f9082c5 | 604 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
605 | .smbus_xfer = i801_access, |
606 | .functionality = i801_func, | |
607 | }; | |
608 | ||
4111ecd2 | 609 | static const struct pci_device_id i801_ids[] = { |
1da177e4 LT |
610 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, |
611 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, | |
612 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, | |
613 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, | |
614 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, | |
615 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, | |
616 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, | |
617 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, | |
618 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, | |
b0a70b57 | 619 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, |
8254fc4a | 620 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, |
adbc2a10 | 621 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, |
cb04e95b | 622 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, |
d28dc711 GJ |
623 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, |
624 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, | |
cb04e95b SH |
625 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, |
626 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, | |
e30d9859 | 627 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, |
55fee8d7 DW |
628 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, |
629 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, | |
630 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, | |
662cda8a | 631 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, |
1da177e4 LT |
632 | { 0, } |
633 | }; | |
634 | ||
3fb21c64 | 635 | MODULE_DEVICE_TABLE(pci, i801_ids); |
1da177e4 | 636 | |
1561bfe5 JD |
637 | #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE |
638 | static unsigned char apanel_addr; | |
639 | ||
640 | /* Scan the system ROM for the signature "FJKEYINF" */ | |
641 | static __init const void __iomem *bios_signature(const void __iomem *bios) | |
642 | { | |
643 | ssize_t offset; | |
644 | const unsigned char signature[] = "FJKEYINF"; | |
645 | ||
646 | for (offset = 0; offset < 0x10000; offset += 0x10) { | |
647 | if (check_signature(bios + offset, signature, | |
648 | sizeof(signature)-1)) | |
649 | return bios + offset; | |
650 | } | |
651 | return NULL; | |
652 | } | |
653 | ||
654 | static void __init input_apanel_init(void) | |
655 | { | |
656 | void __iomem *bios; | |
657 | const void __iomem *p; | |
658 | ||
659 | bios = ioremap(0xF0000, 0x10000); /* Can't fail */ | |
660 | p = bios_signature(bios); | |
661 | if (p) { | |
662 | /* just use the first address */ | |
663 | apanel_addr = readb(p + 8 + 3) >> 1; | |
664 | } | |
665 | iounmap(bios); | |
666 | } | |
667 | #else | |
668 | static void __init input_apanel_init(void) {} | |
669 | #endif | |
670 | ||
fa5bfab7 HG |
671 | #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE |
672 | struct dmi_onboard_device_info { | |
673 | const char *name; | |
674 | u8 type; | |
675 | unsigned short i2c_addr; | |
676 | const char *i2c_type; | |
677 | }; | |
678 | ||
679 | static struct dmi_onboard_device_info __devinitdata dmi_devices[] = { | |
680 | { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, | |
681 | { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, | |
682 | { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, | |
683 | }; | |
684 | ||
685 | static void __devinit dmi_check_onboard_device(u8 type, const char *name, | |
686 | struct i2c_adapter *adap) | |
687 | { | |
688 | int i; | |
689 | struct i2c_board_info info; | |
690 | ||
691 | for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { | |
692 | /* & ~0x80, ignore enabled/disabled bit */ | |
693 | if ((type & ~0x80) != dmi_devices[i].type) | |
694 | continue; | |
faabd47f | 695 | if (strcasecmp(name, dmi_devices[i].name)) |
fa5bfab7 HG |
696 | continue; |
697 | ||
698 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
699 | info.addr = dmi_devices[i].i2c_addr; | |
700 | strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); | |
701 | i2c_new_device(adap, &info); | |
702 | break; | |
703 | } | |
704 | } | |
705 | ||
706 | /* We use our own function to check for onboard devices instead of | |
707 | dmi_find_device() as some buggy BIOS's have the devices we are interested | |
708 | in marked as disabled */ | |
709 | static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm, | |
710 | void *adap) | |
711 | { | |
712 | int i, count; | |
713 | ||
714 | if (dm->type != 10) | |
715 | return; | |
716 | ||
717 | count = (dm->length - sizeof(struct dmi_header)) / 2; | |
718 | for (i = 0; i < count; i++) { | |
719 | const u8 *d = (char *)(dm + 1) + (i * 2); | |
720 | const char *name = ((char *) dm) + dm->length; | |
721 | u8 type = d[0]; | |
722 | u8 s = d[1]; | |
723 | ||
724 | if (!s) | |
725 | continue; | |
726 | s--; | |
727 | while (s > 0 && name[0]) { | |
728 | name += strlen(name) + 1; | |
729 | s--; | |
730 | } | |
731 | if (name[0] == 0) /* Bogus string reference */ | |
732 | continue; | |
733 | ||
734 | dmi_check_onboard_device(type, name, adap); | |
735 | } | |
736 | } | |
737 | #endif | |
738 | ||
3fb21c64 IM |
739 | static int __devinit i801_probe(struct pci_dev *dev, |
740 | const struct pci_device_id *id) | |
1da177e4 | 741 | { |
02dd7ae2 | 742 | unsigned char temp; |
adff687d | 743 | int err, i; |
0cd96eb0 DW |
744 | struct i801_priv *priv; |
745 | ||
746 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
747 | if (!priv) | |
748 | return -ENOMEM; | |
749 | ||
750 | i2c_set_adapdata(&priv->adapter, priv); | |
751 | priv->adapter.owner = THIS_MODULE; | |
752 | priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
753 | priv->adapter.algo = &smbus_algorithm; | |
1da177e4 | 754 | |
0cd96eb0 | 755 | priv->pci_dev = dev; |
250d1bd3 | 756 | switch (dev->device) { |
e0e8398c | 757 | default: |
0cd96eb0 | 758 | priv->features |= FEATURE_I2C_BLOCK_READ; |
6342064c JD |
759 | /* fall through */ |
760 | case PCI_DEVICE_ID_INTEL_82801DB_3: | |
0cd96eb0 DW |
761 | priv->features |= FEATURE_SMBUS_PEC; |
762 | priv->features |= FEATURE_BLOCK_BUFFER; | |
e0e8398c JD |
763 | /* fall through */ |
764 | case PCI_DEVICE_ID_INTEL_82801CA_3: | |
765 | case PCI_DEVICE_ID_INTEL_82801BA_2: | |
766 | case PCI_DEVICE_ID_INTEL_82801AB_3: | |
767 | case PCI_DEVICE_ID_INTEL_82801AA_3: | |
250d1bd3 | 768 | break; |
250d1bd3 | 769 | } |
02dd7ae2 | 770 | |
adff687d JD |
771 | /* Disable features on user request */ |
772 | for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { | |
0cd96eb0 | 773 | if (priv->features & disable_features & (1 << i)) |
adff687d JD |
774 | dev_notice(&dev->dev, "%s disabled by user\n", |
775 | i801_feature_names[i]); | |
776 | } | |
0cd96eb0 | 777 | priv->features &= ~disable_features; |
adff687d | 778 | |
02dd7ae2 JD |
779 | err = pci_enable_device(dev); |
780 | if (err) { | |
781 | dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", | |
782 | err); | |
783 | goto exit; | |
784 | } | |
785 | ||
786 | /* Determine the address of the SMBus area */ | |
0cd96eb0 DW |
787 | priv->smba = pci_resource_start(dev, SMBBAR); |
788 | if (!priv->smba) { | |
02dd7ae2 JD |
789 | dev_err(&dev->dev, "SMBus base address uninitialized, " |
790 | "upgrade BIOS\n"); | |
791 | err = -ENODEV; | |
d6fcb3b9 | 792 | goto exit; |
02dd7ae2 JD |
793 | } |
794 | ||
54fb4a05 | 795 | err = acpi_check_resource_conflict(&dev->resource[SMBBAR]); |
18669eab JD |
796 | if (err) { |
797 | err = -ENODEV; | |
54fb4a05 | 798 | goto exit; |
18669eab | 799 | } |
54fb4a05 | 800 | |
02dd7ae2 JD |
801 | err = pci_request_region(dev, SMBBAR, i801_driver.name); |
802 | if (err) { | |
803 | dev_err(&dev->dev, "Failed to request SMBus region " | |
0cd96eb0 | 804 | "0x%lx-0x%Lx\n", priv->smba, |
598736c5 | 805 | (unsigned long long)pci_resource_end(dev, SMBBAR)); |
d6fcb3b9 | 806 | goto exit; |
02dd7ae2 JD |
807 | } |
808 | ||
0cd96eb0 DW |
809 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); |
810 | priv->original_hstcfg = temp; | |
02dd7ae2 JD |
811 | temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ |
812 | if (!(temp & SMBHSTCFG_HST_EN)) { | |
813 | dev_info(&dev->dev, "Enabling SMBus device\n"); | |
814 | temp |= SMBHSTCFG_HST_EN; | |
815 | } | |
0cd96eb0 | 816 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); |
02dd7ae2 JD |
817 | |
818 | if (temp & SMBHSTCFG_SMB_SMI_EN) | |
819 | dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); | |
820 | else | |
821 | dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n"); | |
1da177e4 | 822 | |
a0921b6c | 823 | /* Clear special mode bits */ |
0cd96eb0 DW |
824 | if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) |
825 | outb_p(inb_p(SMBAUXCTL(priv)) & | |
826 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
a0921b6c | 827 | |
405ae7d3 | 828 | /* set up the sysfs linkage to our parent device */ |
0cd96eb0 | 829 | priv->adapter.dev.parent = &dev->dev; |
1da177e4 | 830 | |
7e2193a8 | 831 | /* Retry up to 3 times on lost arbitration */ |
0cd96eb0 | 832 | priv->adapter.retries = 3; |
7e2193a8 | 833 | |
0cd96eb0 DW |
834 | snprintf(priv->adapter.name, sizeof(priv->adapter.name), |
835 | "SMBus I801 adapter at %04lx", priv->smba); | |
836 | err = i2c_add_adapter(&priv->adapter); | |
02dd7ae2 JD |
837 | if (err) { |
838 | dev_err(&dev->dev, "Failed to add SMBus adapter\n"); | |
d6fcb3b9 | 839 | goto exit_release; |
02dd7ae2 | 840 | } |
1561bfe5 JD |
841 | |
842 | /* Register optional slaves */ | |
843 | #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE | |
844 | if (apanel_addr) { | |
845 | struct i2c_board_info info; | |
846 | ||
847 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
848 | info.addr = apanel_addr; | |
849 | strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); | |
0cd96eb0 | 850 | i2c_new_device(&priv->adapter, &info); |
1561bfe5 JD |
851 | } |
852 | #endif | |
fa5bfab7 | 853 | #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE |
faabd47f | 854 | if (dmi_name_in_vendors("FUJITSU")) |
0cd96eb0 | 855 | dmi_walk(dmi_check_onboard_devices, &priv->adapter); |
fa5bfab7 | 856 | #endif |
1561bfe5 | 857 | |
0cd96eb0 | 858 | pci_set_drvdata(dev, priv); |
d6fcb3b9 | 859 | return 0; |
02dd7ae2 | 860 | |
d6fcb3b9 DR |
861 | exit_release: |
862 | pci_release_region(dev, SMBBAR); | |
02dd7ae2 | 863 | exit: |
0cd96eb0 | 864 | kfree(priv); |
02dd7ae2 | 865 | return err; |
1da177e4 LT |
866 | } |
867 | ||
868 | static void __devexit i801_remove(struct pci_dev *dev) | |
869 | { | |
0cd96eb0 DW |
870 | struct i801_priv *priv = pci_get_drvdata(dev); |
871 | ||
872 | i2c_del_adapter(&priv->adapter); | |
873 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); | |
6dcc19df | 874 | pci_release_region(dev, SMBBAR); |
0cd96eb0 DW |
875 | pci_set_drvdata(dev, NULL); |
876 | kfree(priv); | |
d6fcb3b9 DR |
877 | /* |
878 | * do not call pci_disable_device(dev) since it can cause hard hangs on | |
879 | * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) | |
880 | */ | |
1da177e4 LT |
881 | } |
882 | ||
a5aaea37 JD |
883 | #ifdef CONFIG_PM |
884 | static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) | |
885 | { | |
0cd96eb0 DW |
886 | struct i801_priv *priv = pci_get_drvdata(dev); |
887 | ||
a5aaea37 | 888 | pci_save_state(dev); |
0cd96eb0 | 889 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); |
a5aaea37 JD |
890 | pci_set_power_state(dev, pci_choose_state(dev, mesg)); |
891 | return 0; | |
892 | } | |
893 | ||
894 | static int i801_resume(struct pci_dev *dev) | |
895 | { | |
896 | pci_set_power_state(dev, PCI_D0); | |
897 | pci_restore_state(dev); | |
898 | return pci_enable_device(dev); | |
899 | } | |
900 | #else | |
901 | #define i801_suspend NULL | |
902 | #define i801_resume NULL | |
903 | #endif | |
904 | ||
1da177e4 LT |
905 | static struct pci_driver i801_driver = { |
906 | .name = "i801_smbus", | |
907 | .id_table = i801_ids, | |
908 | .probe = i801_probe, | |
909 | .remove = __devexit_p(i801_remove), | |
a5aaea37 JD |
910 | .suspend = i801_suspend, |
911 | .resume = i801_resume, | |
1da177e4 LT |
912 | }; |
913 | ||
914 | static int __init i2c_i801_init(void) | |
915 | { | |
1561bfe5 | 916 | input_apanel_init(); |
1da177e4 LT |
917 | return pci_register_driver(&i801_driver); |
918 | } | |
919 | ||
920 | static void __exit i2c_i801_exit(void) | |
921 | { | |
922 | pci_unregister_driver(&i801_driver); | |
923 | } | |
924 | ||
6342064c JD |
925 | MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, " |
926 | "Jean Delvare <khali@linux-fr.org>"); | |
1da177e4 LT |
927 | MODULE_DESCRIPTION("I801 SMBus driver"); |
928 | MODULE_LICENSE("GPL"); | |
929 | ||
930 | module_init(i2c_i801_init); | |
931 | module_exit(i2c_i801_exit); |