Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
455f3323 | 2 | i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware |
1da177e4 LT |
3 | monitoring |
4 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, | |
5 | Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker | |
6 | <mdsxyz123@yahoo.com> | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | SUPPORTED DEVICES PCI ID | |
ca8b9e32 OR |
25 | 82801AA 2413 |
26 | 82801AB 2423 | |
27 | 82801BA 2443 | |
28 | 82801CA/CAM 2483 | |
7edcb9ab OR |
29 | 82801DB 24C3 (HW PEC supported) |
30 | 82801EB 24D3 (HW PEC supported) | |
1da177e4 LT |
31 | 6300ESB 25A4 |
32 | ICH6 266A | |
33 | ICH7 27DA | |
b0a70b57 | 34 | ESB2 269B |
8254fc4a | 35 | ICH8 283E |
adbc2a10 | 36 | ICH9 2930 |
1da177e4 LT |
37 | This driver supports several versions of Intel's I/O Controller Hubs (ICH). |
38 | For SMBus support, they are similar to the PIIX4 and are part | |
39 | of Intel's '810' and other chipsets. | |
455f3323 | 40 | See the file Documentation/i2c/busses/i2c-i801 for details. |
1da177e4 LT |
41 | I2C Block Read and Process Call are not supported. |
42 | */ | |
43 | ||
44 | /* Note: we assume there can only be one I801, with one SMBus interface */ | |
45 | ||
1da177e4 LT |
46 | #include <linux/module.h> |
47 | #include <linux/pci.h> | |
48 | #include <linux/kernel.h> | |
49 | #include <linux/stddef.h> | |
50 | #include <linux/delay.h> | |
1da177e4 LT |
51 | #include <linux/ioport.h> |
52 | #include <linux/init.h> | |
53 | #include <linux/i2c.h> | |
54 | #include <asm/io.h> | |
55 | ||
1da177e4 LT |
56 | /* I801 SMBus address offsets */ |
57 | #define SMBHSTSTS (0 + i801_smba) | |
58 | #define SMBHSTCNT (2 + i801_smba) | |
59 | #define SMBHSTCMD (3 + i801_smba) | |
60 | #define SMBHSTADD (4 + i801_smba) | |
61 | #define SMBHSTDAT0 (5 + i801_smba) | |
62 | #define SMBHSTDAT1 (6 + i801_smba) | |
63 | #define SMBBLKDAT (7 + i801_smba) | |
64 | #define SMBPEC (8 + i801_smba) /* ICH4 only */ | |
65 | #define SMBAUXSTS (12 + i801_smba) /* ICH4 only */ | |
66 | #define SMBAUXCTL (13 + i801_smba) /* ICH4 only */ | |
67 | ||
68 | /* PCI Address Constants */ | |
6dcc19df | 69 | #define SMBBAR 4 |
1da177e4 | 70 | #define SMBHSTCFG 0x040 |
1da177e4 LT |
71 | |
72 | /* Host configuration bits for SMBHSTCFG */ | |
73 | #define SMBHSTCFG_HST_EN 1 | |
74 | #define SMBHSTCFG_SMB_SMI_EN 2 | |
75 | #define SMBHSTCFG_I2C_EN 4 | |
76 | ||
ca8b9e32 OR |
77 | /* Auxillary control register bits, ICH4+ only */ |
78 | #define SMBAUXCTL_CRC 1 | |
79 | #define SMBAUXCTL_E32B 2 | |
80 | ||
81 | /* kill bit for SMBHSTCNT */ | |
82 | #define SMBHSTCNT_KILL 2 | |
83 | ||
1da177e4 LT |
84 | /* Other settings */ |
85 | #define MAX_TIMEOUT 100 | |
86 | #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */ | |
87 | ||
88 | /* I801 command constants */ | |
89 | #define I801_QUICK 0x00 | |
90 | #define I801_BYTE 0x04 | |
91 | #define I801_BYTE_DATA 0x08 | |
92 | #define I801_WORD_DATA 0x0C | |
93 | #define I801_PROC_CALL 0x10 /* later chips only, unimplemented */ | |
94 | #define I801_BLOCK_DATA 0x14 | |
95 | #define I801_I2C_BLOCK_DATA 0x18 /* unimplemented */ | |
96 | #define I801_BLOCK_LAST 0x34 | |
97 | #define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */ | |
98 | #define I801_START 0x40 | |
99 | #define I801_PEC_EN 0x80 /* ICH4 only */ | |
100 | ||
ca8b9e32 OR |
101 | /* I801 Hosts Status register bits */ |
102 | #define SMBHSTSTS_BYTE_DONE 0x80 | |
103 | #define SMBHSTSTS_INUSE_STS 0x40 | |
104 | #define SMBHSTSTS_SMBALERT_STS 0x20 | |
105 | #define SMBHSTSTS_FAILED 0x10 | |
106 | #define SMBHSTSTS_BUS_ERR 0x08 | |
107 | #define SMBHSTSTS_DEV_ERR 0x04 | |
108 | #define SMBHSTSTS_INTR 0x02 | |
109 | #define SMBHSTSTS_HOST_BUSY 0x01 | |
1da177e4 | 110 | |
6dcc19df | 111 | static unsigned long i801_smba; |
a5aaea37 | 112 | static unsigned char i801_original_hstcfg; |
d6072f84 | 113 | static struct pci_driver i801_driver; |
1da177e4 LT |
114 | static struct pci_dev *I801_dev; |
115 | static int isich4; | |
116 | ||
7edcb9ab | 117 | static int i801_transaction(int xact) |
1da177e4 LT |
118 | { |
119 | int temp; | |
120 | int result = 0; | |
121 | int timeout = 0; | |
122 | ||
368609c5 | 123 | dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x, " |
1da177e4 LT |
124 | "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), |
125 | inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), | |
126 | inb_p(SMBHSTDAT1)); | |
127 | ||
128 | /* Make sure the SMBus host is ready to start transmitting */ | |
129 | /* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */ | |
130 | if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) { | |
541e6a02 | 131 | dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting...\n", |
1da177e4 LT |
132 | temp); |
133 | outb_p(temp, SMBHSTSTS); | |
134 | if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) { | |
135 | dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp); | |
136 | return -1; | |
137 | } else { | |
fcdd96ec | 138 | dev_dbg(&I801_dev->dev, "Successful!\n"); |
1da177e4 LT |
139 | } |
140 | } | |
141 | ||
7edcb9ab OR |
142 | /* the current contents of SMBHSTCNT can be overwritten, since PEC, |
143 | * INTREN, SMBSCMD are passed in xact */ | |
144 | outb_p(xact | I801_START, SMBHSTCNT); | |
1da177e4 LT |
145 | |
146 | /* We will always wait for a fraction of a second! */ | |
147 | do { | |
148 | msleep(1); | |
149 | temp = inb_p(SMBHSTSTS); | |
ca8b9e32 | 150 | } while ((temp & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT)); |
1da177e4 LT |
151 | |
152 | /* If the SMBus is still busy, we give up */ | |
153 | if (timeout >= MAX_TIMEOUT) { | |
154 | dev_dbg(&I801_dev->dev, "SMBus Timeout!\n"); | |
155 | result = -1; | |
ca8b9e32 OR |
156 | /* try to stop the current command */ |
157 | dev_dbg(&I801_dev->dev, "Terminating the current operation\n"); | |
158 | outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT); | |
159 | msleep(1); | |
160 | outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT); | |
1da177e4 LT |
161 | } |
162 | ||
ca8b9e32 | 163 | if (temp & SMBHSTSTS_FAILED) { |
1da177e4 LT |
164 | result = -1; |
165 | dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n"); | |
166 | } | |
167 | ||
ca8b9e32 | 168 | if (temp & SMBHSTSTS_BUS_ERR) { |
1da177e4 LT |
169 | result = -1; |
170 | dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked " | |
171 | "until next hard reset. (sorry!)\n"); | |
172 | /* Clock stops and slave is stuck in mid-transmission */ | |
173 | } | |
174 | ||
ca8b9e32 | 175 | if (temp & SMBHSTSTS_DEV_ERR) { |
1da177e4 LT |
176 | result = -1; |
177 | dev_dbg(&I801_dev->dev, "Error: no response!\n"); | |
178 | } | |
179 | ||
180 | if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00) | |
181 | outb_p(inb(SMBHSTSTS), SMBHSTSTS); | |
182 | ||
183 | if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) { | |
368609c5 | 184 | dev_dbg(&I801_dev->dev, "Failed reset at end of transaction " |
1da177e4 LT |
185 | "(%02x)\n", temp); |
186 | } | |
187 | dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, " | |
188 | "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), | |
189 | inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), | |
190 | inb_p(SMBHSTDAT1)); | |
191 | return result; | |
192 | } | |
193 | ||
ca8b9e32 OR |
194 | /* wait for INTR bit as advised by Intel */ |
195 | static void i801_wait_hwpec(void) | |
196 | { | |
197 | int timeout = 0; | |
198 | int temp; | |
199 | ||
200 | do { | |
201 | msleep(1); | |
202 | temp = inb_p(SMBHSTSTS); | |
203 | } while ((!(temp & SMBHSTSTS_INTR)) | |
204 | && (timeout++ < MAX_TIMEOUT)); | |
205 | ||
206 | if (timeout >= MAX_TIMEOUT) { | |
207 | dev_dbg(&I801_dev->dev, "PEC Timeout!\n"); | |
208 | } | |
209 | outb_p(temp, SMBHSTSTS); | |
210 | } | |
211 | ||
7edcb9ab OR |
212 | static int i801_block_transaction_by_block(union i2c_smbus_data *data, |
213 | char read_write, int hwpec) | |
214 | { | |
215 | int i, len; | |
216 | ||
217 | inb_p(SMBHSTCNT); /* reset the data buffer index */ | |
218 | ||
219 | /* Use 32-byte buffer to process this transaction */ | |
220 | if (read_write == I2C_SMBUS_WRITE) { | |
221 | len = data->block[0]; | |
222 | outb_p(len, SMBHSTDAT0); | |
223 | for (i = 0; i < len; i++) | |
224 | outb_p(data->block[i+1], SMBBLKDAT); | |
225 | } | |
226 | ||
227 | if (i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 | | |
228 | I801_PEC_EN * hwpec)) | |
229 | return -1; | |
230 | ||
231 | if (read_write == I2C_SMBUS_READ) { | |
232 | len = inb_p(SMBHSTDAT0); | |
233 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) | |
234 | return -1; | |
235 | ||
236 | data->block[0] = len; | |
237 | for (i = 0; i < len; i++) | |
238 | data->block[i + 1] = inb_p(SMBBLKDAT); | |
239 | } | |
240 | return 0; | |
241 | } | |
242 | ||
243 | static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data, | |
244 | char read_write, int hwpec) | |
1da177e4 LT |
245 | { |
246 | int i, len; | |
247 | int smbcmd; | |
248 | int temp; | |
249 | int result = 0; | |
250 | int timeout; | |
7edcb9ab | 251 | unsigned char errmask; |
1da177e4 | 252 | |
7edcb9ab | 253 | len = data->block[0]; |
1da177e4 LT |
254 | |
255 | if (read_write == I2C_SMBUS_WRITE) { | |
1da177e4 LT |
256 | outb_p(len, SMBHSTDAT0); |
257 | outb_p(data->block[1], SMBBLKDAT); | |
1da177e4 LT |
258 | } |
259 | ||
260 | for (i = 1; i <= len; i++) { | |
261 | if (i == len && read_write == I2C_SMBUS_READ) | |
262 | smbcmd = I801_BLOCK_LAST; | |
263 | else | |
264 | smbcmd = I801_BLOCK_DATA; | |
265 | outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT); | |
266 | ||
267 | dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, " | |
268 | "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i, | |
269 | inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD), | |
270 | inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT)); | |
271 | ||
272 | /* Make sure the SMBus host is ready to start transmitting */ | |
273 | temp = inb_p(SMBHSTSTS); | |
274 | if (i == 1) { | |
ca8b9e32 | 275 | /* Erronenous conditions before transaction: |
1da177e4 | 276 | * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */ |
ca8b9e32 | 277 | errmask = 0x9f; |
1da177e4 | 278 | } else { |
ca8b9e32 | 279 | /* Erronenous conditions during transaction: |
1da177e4 | 280 | * Failed, Bus_Err, Dev_Err, Intr */ |
ca8b9e32 | 281 | errmask = 0x1e; |
1da177e4 LT |
282 | } |
283 | if (temp & errmask) { | |
284 | dev_dbg(&I801_dev->dev, "SMBus busy (%02x). " | |
541e6a02 | 285 | "Resetting...\n", temp); |
1da177e4 LT |
286 | outb_p(temp, SMBHSTSTS); |
287 | if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) { | |
288 | dev_err(&I801_dev->dev, | |
289 | "Reset failed! (%02x)\n", temp); | |
7edcb9ab | 290 | return -1; |
1da177e4 | 291 | } |
7edcb9ab | 292 | if (i != 1) |
1da177e4 | 293 | /* if die in middle of block transaction, fail */ |
7edcb9ab | 294 | return -1; |
1da177e4 LT |
295 | } |
296 | ||
297 | if (i == 1) | |
298 | outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT); | |
299 | ||
300 | /* We will always wait for a fraction of a second! */ | |
301 | timeout = 0; | |
302 | do { | |
1da177e4 | 303 | msleep(1); |
397e2f66 | 304 | temp = inb_p(SMBHSTSTS); |
1da177e4 | 305 | } |
ca8b9e32 OR |
306 | while ((!(temp & SMBHSTSTS_BYTE_DONE)) |
307 | && (timeout++ < MAX_TIMEOUT)); | |
1da177e4 LT |
308 | |
309 | /* If the SMBus is still busy, we give up */ | |
310 | if (timeout >= MAX_TIMEOUT) { | |
ca8b9e32 OR |
311 | /* try to stop the current command */ |
312 | dev_dbg(&I801_dev->dev, "Terminating the current " | |
313 | "operation\n"); | |
314 | outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT); | |
315 | msleep(1); | |
316 | outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), | |
317 | SMBHSTCNT); | |
1da177e4 LT |
318 | result = -1; |
319 | dev_dbg(&I801_dev->dev, "SMBus Timeout!\n"); | |
320 | } | |
321 | ||
ca8b9e32 | 322 | if (temp & SMBHSTSTS_FAILED) { |
1da177e4 LT |
323 | result = -1; |
324 | dev_dbg(&I801_dev->dev, | |
325 | "Error: Failed bus transaction\n"); | |
ca8b9e32 | 326 | } else if (temp & SMBHSTSTS_BUS_ERR) { |
1da177e4 LT |
327 | result = -1; |
328 | dev_err(&I801_dev->dev, "Bus collision!\n"); | |
ca8b9e32 | 329 | } else if (temp & SMBHSTSTS_DEV_ERR) { |
1da177e4 LT |
330 | result = -1; |
331 | dev_dbg(&I801_dev->dev, "Error: no response!\n"); | |
332 | } | |
333 | ||
334 | if (i == 1 && read_write == I2C_SMBUS_READ) { | |
335 | len = inb_p(SMBHSTDAT0); | |
7edcb9ab OR |
336 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) |
337 | return -1; | |
1da177e4 LT |
338 | data->block[0] = len; |
339 | } | |
340 | ||
341 | /* Retrieve/store value in SMBBLKDAT */ | |
342 | if (read_write == I2C_SMBUS_READ) | |
343 | data->block[i] = inb_p(SMBBLKDAT); | |
344 | if (read_write == I2C_SMBUS_WRITE && i+1 <= len) | |
345 | outb_p(data->block[i+1], SMBBLKDAT); | |
346 | if ((temp & 0x9e) != 0x00) | |
347 | outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */ | |
348 | ||
349 | if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) { | |
350 | dev_dbg(&I801_dev->dev, | |
351 | "Bad status (%02x) at end of transaction\n", | |
352 | temp); | |
353 | } | |
354 | dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, " | |
355 | "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i, | |
356 | inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD), | |
357 | inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT)); | |
358 | ||
359 | if (result < 0) | |
7edcb9ab | 360 | return result; |
1da177e4 | 361 | } |
7edcb9ab OR |
362 | return result; |
363 | } | |
1da177e4 | 364 | |
7edcb9ab OR |
365 | static int i801_set_block_buffer_mode(void) |
366 | { | |
367 | outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL); | |
368 | if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0) | |
369 | return -1; | |
370 | return 0; | |
371 | } | |
372 | ||
373 | /* Block transaction function */ | |
374 | static int i801_block_transaction(union i2c_smbus_data *data, char read_write, | |
375 | int command, int hwpec) | |
376 | { | |
377 | int result = 0; | |
378 | unsigned char hostc; | |
379 | ||
380 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
381 | if (read_write == I2C_SMBUS_WRITE) { | |
382 | /* set I2C_EN bit in configuration register */ | |
383 | pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc); | |
384 | pci_write_config_byte(I801_dev, SMBHSTCFG, | |
385 | hostc | SMBHSTCFG_I2C_EN); | |
386 | } else { | |
387 | dev_err(&I801_dev->dev, | |
388 | "I2C_SMBUS_I2C_BLOCK_READ not DB!\n"); | |
389 | return -1; | |
390 | } | |
391 | } | |
392 | ||
393 | if (read_write == I2C_SMBUS_WRITE) { | |
394 | if (data->block[0] < 1) | |
395 | data->block[0] = 1; | |
396 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) | |
397 | data->block[0] = I2C_SMBUS_BLOCK_MAX; | |
398 | } else { | |
399 | data->block[0] = 32; /* max for reads */ | |
400 | } | |
401 | ||
402 | if (isich4 && i801_set_block_buffer_mode() == 0 ) | |
403 | result = i801_block_transaction_by_block(data, read_write, | |
404 | hwpec); | |
405 | else | |
406 | result = i801_block_transaction_byte_by_byte(data, read_write, | |
407 | hwpec); | |
408 | ||
409 | if (result == 0 && hwpec) | |
ca8b9e32 | 410 | i801_wait_hwpec(); |
1da177e4 | 411 | |
1da177e4 LT |
412 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { |
413 | /* restore saved configuration register value */ | |
414 | pci_write_config_byte(I801_dev, SMBHSTCFG, hostc); | |
415 | } | |
416 | return result; | |
417 | } | |
418 | ||
419 | /* Return -1 on error. */ | |
420 | static s32 i801_access(struct i2c_adapter * adap, u16 addr, | |
421 | unsigned short flags, char read_write, u8 command, | |
422 | int size, union i2c_smbus_data * data) | |
423 | { | |
e8aac4a9 | 424 | int hwpec; |
1da177e4 LT |
425 | int block = 0; |
426 | int ret, xact = 0; | |
427 | ||
e8aac4a9 JD |
428 | hwpec = isich4 && (flags & I2C_CLIENT_PEC) |
429 | && size != I2C_SMBUS_QUICK | |
430 | && size != I2C_SMBUS_I2C_BLOCK_DATA; | |
1da177e4 LT |
431 | |
432 | switch (size) { | |
433 | case I2C_SMBUS_QUICK: | |
434 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
435 | SMBHSTADD); | |
436 | xact = I801_QUICK; | |
437 | break; | |
438 | case I2C_SMBUS_BYTE: | |
439 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
440 | SMBHSTADD); | |
441 | if (read_write == I2C_SMBUS_WRITE) | |
442 | outb_p(command, SMBHSTCMD); | |
443 | xact = I801_BYTE; | |
444 | break; | |
445 | case I2C_SMBUS_BYTE_DATA: | |
446 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
447 | SMBHSTADD); | |
448 | outb_p(command, SMBHSTCMD); | |
449 | if (read_write == I2C_SMBUS_WRITE) | |
450 | outb_p(data->byte, SMBHSTDAT0); | |
451 | xact = I801_BYTE_DATA; | |
452 | break; | |
453 | case I2C_SMBUS_WORD_DATA: | |
454 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
455 | SMBHSTADD); | |
456 | outb_p(command, SMBHSTCMD); | |
457 | if (read_write == I2C_SMBUS_WRITE) { | |
458 | outb_p(data->word & 0xff, SMBHSTDAT0); | |
459 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); | |
460 | } | |
461 | xact = I801_WORD_DATA; | |
462 | break; | |
463 | case I2C_SMBUS_BLOCK_DATA: | |
464 | case I2C_SMBUS_I2C_BLOCK_DATA: | |
1da177e4 LT |
465 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
466 | SMBHSTADD); | |
467 | outb_p(command, SMBHSTCMD); | |
468 | block = 1; | |
469 | break; | |
470 | case I2C_SMBUS_PROC_CALL: | |
471 | default: | |
472 | dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size); | |
473 | return -1; | |
474 | } | |
475 | ||
ca8b9e32 OR |
476 | if (hwpec) /* enable/disable hardware PEC */ |
477 | outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL); | |
478 | else | |
479 | outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL); | |
e8aac4a9 | 480 | |
1da177e4 | 481 | if(block) |
585b3160 | 482 | ret = i801_block_transaction(data, read_write, size, hwpec); |
7edcb9ab OR |
483 | else |
484 | ret = i801_transaction(xact | ENABLE_INT9); | |
1da177e4 | 485 | |
c79cfbac | 486 | /* Some BIOSes don't like it when PEC is enabled at reboot or resume |
7edcb9ab OR |
487 | time, so we forcibly disable it after every transaction. Turn off |
488 | E32B for the same reason. */ | |
c79cfbac | 489 | if (hwpec) |
7edcb9ab OR |
490 | outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), |
491 | SMBAUXCTL); | |
c79cfbac | 492 | |
1da177e4 LT |
493 | if(block) |
494 | return ret; | |
495 | if(ret) | |
496 | return -1; | |
497 | if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) | |
498 | return 0; | |
499 | ||
500 | switch (xact & 0x7f) { | |
501 | case I801_BYTE: /* Result put in SMBHSTDAT0 */ | |
502 | case I801_BYTE_DATA: | |
503 | data->byte = inb_p(SMBHSTDAT0); | |
504 | break; | |
505 | case I801_WORD_DATA: | |
506 | data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); | |
507 | break; | |
508 | } | |
509 | return 0; | |
510 | } | |
511 | ||
512 | ||
513 | static u32 i801_func(struct i2c_adapter *adapter) | |
514 | { | |
515 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | | |
516 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | | |
517 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | |
b8095544 | 518 | | (isich4 ? I2C_FUNC_SMBUS_HWPEC_CALC : 0); |
1da177e4 LT |
519 | } |
520 | ||
8f9082c5 | 521 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
522 | .smbus_xfer = i801_access, |
523 | .functionality = i801_func, | |
524 | }; | |
525 | ||
526 | static struct i2c_adapter i801_adapter = { | |
527 | .owner = THIS_MODULE, | |
9ace555d | 528 | .id = I2C_HW_SMBUS_I801, |
1da177e4 LT |
529 | .class = I2C_CLASS_HWMON, |
530 | .algo = &smbus_algorithm, | |
1da177e4 LT |
531 | }; |
532 | ||
533 | static struct pci_device_id i801_ids[] = { | |
534 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, | |
535 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, | |
536 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, | |
537 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, | |
538 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, | |
539 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, | |
540 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, | |
541 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, | |
542 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, | |
b0a70b57 | 543 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, |
8254fc4a | 544 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, |
adbc2a10 | 545 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, |
1da177e4 LT |
546 | { 0, } |
547 | }; | |
548 | ||
549 | MODULE_DEVICE_TABLE (pci, i801_ids); | |
550 | ||
551 | static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
552 | { | |
02dd7ae2 | 553 | unsigned char temp; |
455f3323 | 554 | int err; |
1da177e4 | 555 | |
02dd7ae2 | 556 | I801_dev = dev; |
250d1bd3 JD |
557 | switch (dev->device) { |
558 | case PCI_DEVICE_ID_INTEL_82801DB_3: | |
559 | case PCI_DEVICE_ID_INTEL_82801EB_3: | |
560 | case PCI_DEVICE_ID_INTEL_ESB_4: | |
561 | case PCI_DEVICE_ID_INTEL_ICH6_16: | |
562 | case PCI_DEVICE_ID_INTEL_ICH7_17: | |
563 | case PCI_DEVICE_ID_INTEL_ESB2_17: | |
564 | case PCI_DEVICE_ID_INTEL_ICH8_5: | |
565 | case PCI_DEVICE_ID_INTEL_ICH9_6: | |
02dd7ae2 | 566 | isich4 = 1; |
250d1bd3 JD |
567 | break; |
568 | default: | |
02dd7ae2 | 569 | isich4 = 0; |
250d1bd3 | 570 | } |
02dd7ae2 JD |
571 | |
572 | err = pci_enable_device(dev); | |
573 | if (err) { | |
574 | dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", | |
575 | err); | |
576 | goto exit; | |
577 | } | |
578 | ||
579 | /* Determine the address of the SMBus area */ | |
580 | i801_smba = pci_resource_start(dev, SMBBAR); | |
581 | if (!i801_smba) { | |
582 | dev_err(&dev->dev, "SMBus base address uninitialized, " | |
583 | "upgrade BIOS\n"); | |
584 | err = -ENODEV; | |
d6fcb3b9 | 585 | goto exit; |
02dd7ae2 JD |
586 | } |
587 | ||
588 | err = pci_request_region(dev, SMBBAR, i801_driver.name); | |
589 | if (err) { | |
590 | dev_err(&dev->dev, "Failed to request SMBus region " | |
598736c5 AM |
591 | "0x%lx-0x%Lx\n", i801_smba, |
592 | (unsigned long long)pci_resource_end(dev, SMBBAR)); | |
d6fcb3b9 | 593 | goto exit; |
02dd7ae2 JD |
594 | } |
595 | ||
596 | pci_read_config_byte(I801_dev, SMBHSTCFG, &temp); | |
a5aaea37 | 597 | i801_original_hstcfg = temp; |
02dd7ae2 JD |
598 | temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ |
599 | if (!(temp & SMBHSTCFG_HST_EN)) { | |
600 | dev_info(&dev->dev, "Enabling SMBus device\n"); | |
601 | temp |= SMBHSTCFG_HST_EN; | |
602 | } | |
603 | pci_write_config_byte(I801_dev, SMBHSTCFG, temp); | |
604 | ||
605 | if (temp & SMBHSTCFG_SMB_SMI_EN) | |
606 | dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); | |
607 | else | |
608 | dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n"); | |
1da177e4 | 609 | |
405ae7d3 | 610 | /* set up the sysfs linkage to our parent device */ |
1da177e4 LT |
611 | i801_adapter.dev.parent = &dev->dev; |
612 | ||
2096b956 | 613 | snprintf(i801_adapter.name, sizeof(i801_adapter.name), |
6dcc19df | 614 | "SMBus I801 adapter at %04lx", i801_smba); |
02dd7ae2 JD |
615 | err = i2c_add_adapter(&i801_adapter); |
616 | if (err) { | |
617 | dev_err(&dev->dev, "Failed to add SMBus adapter\n"); | |
d6fcb3b9 | 618 | goto exit_release; |
02dd7ae2 | 619 | } |
d6fcb3b9 | 620 | return 0; |
02dd7ae2 | 621 | |
d6fcb3b9 DR |
622 | exit_release: |
623 | pci_release_region(dev, SMBBAR); | |
02dd7ae2 JD |
624 | exit: |
625 | return err; | |
1da177e4 LT |
626 | } |
627 | ||
628 | static void __devexit i801_remove(struct pci_dev *dev) | |
629 | { | |
630 | i2c_del_adapter(&i801_adapter); | |
a5aaea37 | 631 | pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg); |
6dcc19df | 632 | pci_release_region(dev, SMBBAR); |
d6fcb3b9 DR |
633 | /* |
634 | * do not call pci_disable_device(dev) since it can cause hard hangs on | |
635 | * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) | |
636 | */ | |
1da177e4 LT |
637 | } |
638 | ||
a5aaea37 JD |
639 | #ifdef CONFIG_PM |
640 | static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) | |
641 | { | |
642 | pci_save_state(dev); | |
643 | pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg); | |
644 | pci_set_power_state(dev, pci_choose_state(dev, mesg)); | |
645 | return 0; | |
646 | } | |
647 | ||
648 | static int i801_resume(struct pci_dev *dev) | |
649 | { | |
650 | pci_set_power_state(dev, PCI_D0); | |
651 | pci_restore_state(dev); | |
652 | return pci_enable_device(dev); | |
653 | } | |
654 | #else | |
655 | #define i801_suspend NULL | |
656 | #define i801_resume NULL | |
657 | #endif | |
658 | ||
1da177e4 LT |
659 | static struct pci_driver i801_driver = { |
660 | .name = "i801_smbus", | |
661 | .id_table = i801_ids, | |
662 | .probe = i801_probe, | |
663 | .remove = __devexit_p(i801_remove), | |
a5aaea37 JD |
664 | .suspend = i801_suspend, |
665 | .resume = i801_resume, | |
1da177e4 LT |
666 | }; |
667 | ||
668 | static int __init i2c_i801_init(void) | |
669 | { | |
670 | return pci_register_driver(&i801_driver); | |
671 | } | |
672 | ||
673 | static void __exit i2c_i801_exit(void) | |
674 | { | |
675 | pci_unregister_driver(&i801_driver); | |
676 | } | |
677 | ||
678 | MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, " | |
679 | "Philip Edelbrock <phil@netroedge.com>, " | |
680 | "and Mark D. Studebaker <mdsxyz123@yahoo.com>"); | |
681 | MODULE_DESCRIPTION("I801 SMBus driver"); | |
682 | MODULE_LICENSE("GPL"); | |
683 | ||
684 | module_init(i2c_i801_init); | |
685 | module_exit(i2c_i801_exit); |