Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, |
3 | Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker | |
4 | <mdsxyz123@yahoo.com> | |
b3b8df97 | 5 | Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> |
0cd96eb0 DW |
6 | Copyright (C) 2010 Intel Corporation, |
7 | David Woodhouse <dwmw2@infradead.org> | |
1da177e4 LT |
8 | |
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
1da177e4 LT |
18 | */ |
19 | ||
20 | /* | |
ce316110 JD |
21 | * Supports the following Intel I/O Controller Hubs (ICH): |
22 | * | |
23 | * I/O Block I2C | |
24 | * region SMBus Block proc. block | |
25 | * Chip name PCI ID size PEC buffer call read | |
26 | * --------------------------------------------------------------------------- | |
27 | * 82801AA (ICH) 0x2413 16 no no no no | |
28 | * 82801AB (ICH0) 0x2423 16 no no no no | |
29 | * 82801BA (ICH2) 0x2443 16 no no no no | |
30 | * 82801CA (ICH3) 0x2483 32 soft no no no | |
31 | * 82801DB (ICH4) 0x24c3 32 hard yes no no | |
32 | * 82801E (ICH5) 0x24d3 32 hard yes yes yes | |
33 | * 6300ESB 0x25a4 32 hard yes yes yes | |
34 | * 82801F (ICH6) 0x266a 32 hard yes yes yes | |
35 | * 6310ESB/6320ESB 0x269b 32 hard yes yes yes | |
36 | * 82801G (ICH7) 0x27da 32 hard yes yes yes | |
37 | * 82801H (ICH8) 0x283e 32 hard yes yes yes | |
38 | * 82801I (ICH9) 0x2930 32 hard yes yes yes | |
39 | * EP80579 (Tolapai) 0x5032 32 hard yes yes yes | |
40 | * ICH10 0x3a30 32 hard yes yes yes | |
41 | * ICH10 0x3a60 32 hard yes yes yes | |
42 | * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes | |
43 | * 6 Series (PCH) 0x1c22 32 hard yes yes yes | |
44 | * Patsburg (PCH) 0x1d22 32 hard yes yes yes | |
45 | * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes | |
46 | * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes | |
47 | * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes | |
48 | * DH89xxCC (PCH) 0x2330 32 hard yes yes yes | |
49 | * Panther Point (PCH) 0x1e22 32 hard yes yes yes | |
50 | * Lynx Point (PCH) 0x8c22 32 hard yes yes yes | |
51 | * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes | |
52 | * Avoton (SOC) 0x1f3c 32 hard yes yes yes | |
53 | * Wellsburg (PCH) 0x8d22 32 hard yes yes yes | |
54 | * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes | |
55 | * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes | |
56 | * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes | |
57 | * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes | |
b299de83 | 58 | * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes |
ce316110 JD |
59 | * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes |
60 | * BayTrail (SOC) 0x0f12 32 hard yes yes yes | |
3e27a844 | 61 | * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes |
ce316110 JD |
62 | * |
63 | * Features supported by this driver: | |
64 | * Software PEC no | |
65 | * Hardware PEC yes | |
66 | * Block buffer yes | |
67 | * Block process call transaction no | |
68 | * I2C block read transaction yes (doesn't use the block buffer) | |
69 | * Slave mode no | |
70 | * Interrupt processing yes | |
71 | * | |
72 | * See the file Documentation/i2c/busses/i2c-i801 for details. | |
73 | */ | |
1da177e4 | 74 | |
636752bc | 75 | #include <linux/interrupt.h> |
1da177e4 LT |
76 | #include <linux/module.h> |
77 | #include <linux/pci.h> | |
78 | #include <linux/kernel.h> | |
79 | #include <linux/stddef.h> | |
80 | #include <linux/delay.h> | |
1da177e4 LT |
81 | #include <linux/ioport.h> |
82 | #include <linux/init.h> | |
83 | #include <linux/i2c.h> | |
54fb4a05 | 84 | #include <linux/acpi.h> |
1561bfe5 | 85 | #include <linux/io.h> |
fa5bfab7 | 86 | #include <linux/dmi.h> |
665a96b7 | 87 | #include <linux/slab.h> |
636752bc | 88 | #include <linux/wait.h> |
3ad7ea18 JD |
89 | #include <linux/err.h> |
90 | ||
79e3e5b8 JD |
91 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
92 | defined CONFIG_DMI | |
3ad7ea18 JD |
93 | #include <linux/gpio.h> |
94 | #include <linux/i2c-mux-gpio.h> | |
95 | #include <linux/platform_device.h> | |
96 | #endif | |
1da177e4 | 97 | |
1da177e4 | 98 | /* I801 SMBus address offsets */ |
0cd96eb0 DW |
99 | #define SMBHSTSTS(p) (0 + (p)->smba) |
100 | #define SMBHSTCNT(p) (2 + (p)->smba) | |
101 | #define SMBHSTCMD(p) (3 + (p)->smba) | |
102 | #define SMBHSTADD(p) (4 + (p)->smba) | |
103 | #define SMBHSTDAT0(p) (5 + (p)->smba) | |
104 | #define SMBHSTDAT1(p) (6 + (p)->smba) | |
105 | #define SMBBLKDAT(p) (7 + (p)->smba) | |
106 | #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ | |
107 | #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ | |
108 | #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ | |
1da177e4 LT |
109 | |
110 | /* PCI Address Constants */ | |
6dcc19df | 111 | #define SMBBAR 4 |
636752bc | 112 | #define SMBPCISTS 0x006 |
1da177e4 | 113 | #define SMBHSTCFG 0x040 |
1da177e4 | 114 | |
636752bc DK |
115 | /* Host status bits for SMBPCISTS */ |
116 | #define SMBPCISTS_INTS 0x08 | |
117 | ||
1da177e4 LT |
118 | /* Host configuration bits for SMBHSTCFG */ |
119 | #define SMBHSTCFG_HST_EN 1 | |
120 | #define SMBHSTCFG_SMB_SMI_EN 2 | |
121 | #define SMBHSTCFG_I2C_EN 4 | |
122 | ||
25985edc | 123 | /* Auxiliary control register bits, ICH4+ only */ |
ca8b9e32 OR |
124 | #define SMBAUXCTL_CRC 1 |
125 | #define SMBAUXCTL_E32B 2 | |
126 | ||
1da177e4 | 127 | /* Other settings */ |
84c1af4c | 128 | #define MAX_RETRIES 400 |
1da177e4 LT |
129 | |
130 | /* I801 command constants */ | |
131 | #define I801_QUICK 0x00 | |
132 | #define I801_BYTE 0x04 | |
133 | #define I801_BYTE_DATA 0x08 | |
134 | #define I801_WORD_DATA 0x0C | |
ae7b0497 | 135 | #define I801_PROC_CALL 0x10 /* unimplemented */ |
1da177e4 | 136 | #define I801_BLOCK_DATA 0x14 |
6342064c | 137 | #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ |
edbeea63 DK |
138 | |
139 | /* I801 Host Control register bits */ | |
140 | #define SMBHSTCNT_INTREN 0x01 | |
141 | #define SMBHSTCNT_KILL 0x02 | |
142 | #define SMBHSTCNT_LAST_BYTE 0x20 | |
143 | #define SMBHSTCNT_START 0x40 | |
144 | #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */ | |
1da177e4 | 145 | |
ca8b9e32 OR |
146 | /* I801 Hosts Status register bits */ |
147 | #define SMBHSTSTS_BYTE_DONE 0x80 | |
148 | #define SMBHSTSTS_INUSE_STS 0x40 | |
149 | #define SMBHSTSTS_SMBALERT_STS 0x20 | |
150 | #define SMBHSTSTS_FAILED 0x10 | |
151 | #define SMBHSTSTS_BUS_ERR 0x08 | |
152 | #define SMBHSTSTS_DEV_ERR 0x04 | |
153 | #define SMBHSTSTS_INTR 0x02 | |
154 | #define SMBHSTSTS_HOST_BUSY 0x01 | |
1da177e4 | 155 | |
70a1cc19 DK |
156 | #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ |
157 | SMBHSTSTS_DEV_ERR) | |
158 | ||
159 | #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ | |
160 | STATUS_ERROR_FLAGS) | |
cf898dc5 | 161 | |
a6e5e2be | 162 | /* Older devices have their ID defined in <linux/pci_ids.h> */ |
ce316110 | 163 | #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 |
39e8e30e | 164 | #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 |
ce316110 JD |
165 | #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 |
166 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 | |
55fee8d7 | 167 | /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ |
ce316110 JD |
168 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 |
169 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 | |
170 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 | |
171 | #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 | |
172 | #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c | |
173 | #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 | |
174 | #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 | |
175 | #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 | |
176 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 | |
b299de83 | 177 | #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 |
ce316110 JD |
178 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 |
179 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d | |
180 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e | |
181 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f | |
182 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 | |
afc65924 | 183 | #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 |
3e27a844 | 184 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 |
55fee8d7 | 185 | |
3ad7ea18 JD |
186 | struct i801_mux_config { |
187 | char *gpio_chip; | |
188 | unsigned values[3]; | |
189 | int n_values; | |
190 | unsigned classes[3]; | |
191 | unsigned gpios[2]; /* Relative to gpio_chip->base */ | |
192 | int n_gpios; | |
193 | }; | |
194 | ||
0cd96eb0 DW |
195 | struct i801_priv { |
196 | struct i2c_adapter adapter; | |
197 | unsigned long smba; | |
198 | unsigned char original_hstcfg; | |
199 | struct pci_dev *pci_dev; | |
200 | unsigned int features; | |
636752bc DK |
201 | |
202 | /* isr processing */ | |
203 | wait_queue_head_t waitq; | |
204 | u8 status; | |
d3ff6ce4 DK |
205 | |
206 | /* Command state used by isr for byte-by-byte block transactions */ | |
207 | u8 cmd; | |
208 | bool is_read; | |
209 | int count; | |
210 | int len; | |
211 | u8 *data; | |
3ad7ea18 | 212 | |
79e3e5b8 JD |
213 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
214 | defined CONFIG_DMI | |
3ad7ea18 | 215 | const struct i801_mux_config *mux_drvdata; |
3ad7ea18 JD |
216 | struct platform_device *mux_pdev; |
217 | #endif | |
0cd96eb0 DW |
218 | }; |
219 | ||
d6072f84 | 220 | static struct pci_driver i801_driver; |
369f6f4a JD |
221 | |
222 | #define FEATURE_SMBUS_PEC (1 << 0) | |
223 | #define FEATURE_BLOCK_BUFFER (1 << 1) | |
224 | #define FEATURE_BLOCK_PROC (1 << 2) | |
225 | #define FEATURE_I2C_BLOCK_READ (1 << 3) | |
636752bc | 226 | #define FEATURE_IRQ (1 << 4) |
e7198fbf JD |
227 | /* Not really a feature, but it's convenient to handle it as such */ |
228 | #define FEATURE_IDF (1 << 15) | |
1da177e4 | 229 | |
adff687d JD |
230 | static const char *i801_feature_names[] = { |
231 | "SMBus PEC", | |
232 | "Block buffer", | |
233 | "Block process call", | |
234 | "I2C block read", | |
636752bc | 235 | "Interrupt", |
adff687d JD |
236 | }; |
237 | ||
238 | static unsigned int disable_features; | |
239 | module_param(disable_features, uint, S_IRUGO | S_IWUSR); | |
53229345 JD |
240 | MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" |
241 | "\t\t 0x01 disable SMBus PEC\n" | |
242 | "\t\t 0x02 disable the block buffer\n" | |
243 | "\t\t 0x08 disable the I2C block read functionality\n" | |
244 | "\t\t 0x10 don't use interrupts "); | |
adff687d | 245 | |
cf898dc5 JD |
246 | /* Make sure the SMBus host is ready to start transmitting. |
247 | Return 0 if it is, -EBUSY if it is not. */ | |
0cd96eb0 | 248 | static int i801_check_pre(struct i801_priv *priv) |
1da177e4 | 249 | { |
2b73809d | 250 | int status; |
1da177e4 | 251 | |
0cd96eb0 | 252 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 | 253 | if (status & SMBHSTSTS_HOST_BUSY) { |
0cd96eb0 | 254 | dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); |
cf898dc5 JD |
255 | return -EBUSY; |
256 | } | |
257 | ||
258 | status &= STATUS_FLAGS; | |
259 | if (status) { | |
0cd96eb0 | 260 | dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", |
2b73809d | 261 | status); |
0cd96eb0 DW |
262 | outb_p(status, SMBHSTSTS(priv)); |
263 | status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; | |
cf898dc5 | 264 | if (status) { |
0cd96eb0 | 265 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
266 | "Failed clearing status flags (%02x)\n", |
267 | status); | |
97140342 | 268 | return -EBUSY; |
1da177e4 LT |
269 | } |
270 | } | |
271 | ||
cf898dc5 JD |
272 | return 0; |
273 | } | |
1da177e4 | 274 | |
6cad93c4 JD |
275 | /* |
276 | * Convert the status register to an error code, and clear it. | |
277 | * Note that status only contains the bits we want to clear, not the | |
278 | * actual register value. | |
279 | */ | |
280 | static int i801_check_post(struct i801_priv *priv, int status) | |
cf898dc5 JD |
281 | { |
282 | int result = 0; | |
1da177e4 | 283 | |
636752bc DK |
284 | /* |
285 | * If the SMBus is still busy, we give up | |
286 | * Note: This timeout condition only happens when using polling | |
287 | * transactions. For interrupt operation, NAK/timeout is indicated by | |
288 | * DEV_ERR. | |
289 | */ | |
6cad93c4 | 290 | if (unlikely(status < 0)) { |
0cd96eb0 | 291 | dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); |
ca8b9e32 | 292 | /* try to stop the current command */ |
0cd96eb0 DW |
293 | dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); |
294 | outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, | |
295 | SMBHSTCNT(priv)); | |
84c1af4c | 296 | usleep_range(1000, 2000); |
0cd96eb0 DW |
297 | outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), |
298 | SMBHSTCNT(priv)); | |
cf898dc5 JD |
299 | |
300 | /* Check if it worked */ | |
0cd96eb0 | 301 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 JD |
302 | if ((status & SMBHSTSTS_HOST_BUSY) || |
303 | !(status & SMBHSTSTS_FAILED)) | |
0cd96eb0 | 304 | dev_err(&priv->pci_dev->dev, |
cf898dc5 | 305 | "Failed terminating the transaction\n"); |
0cd96eb0 | 306 | outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); |
cf898dc5 | 307 | return -ETIMEDOUT; |
1da177e4 LT |
308 | } |
309 | ||
2b73809d | 310 | if (status & SMBHSTSTS_FAILED) { |
97140342 | 311 | result = -EIO; |
0cd96eb0 | 312 | dev_err(&priv->pci_dev->dev, "Transaction failed\n"); |
cf898dc5 JD |
313 | } |
314 | if (status & SMBHSTSTS_DEV_ERR) { | |
315 | result = -ENXIO; | |
0cd96eb0 | 316 | dev_dbg(&priv->pci_dev->dev, "No response\n"); |
1da177e4 | 317 | } |
2b73809d | 318 | if (status & SMBHSTSTS_BUS_ERR) { |
dcb5c923 | 319 | result = -EAGAIN; |
0cd96eb0 | 320 | dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); |
1da177e4 LT |
321 | } |
322 | ||
6cad93c4 JD |
323 | /* Clear status flags except BYTE_DONE, to be cleared by caller */ |
324 | outb_p(status, SMBHSTSTS(priv)); | |
1da177e4 | 325 | |
1da177e4 LT |
326 | return result; |
327 | } | |
328 | ||
6cad93c4 JD |
329 | /* Wait for BUSY being cleared and either INTR or an error flag being set */ |
330 | static int i801_wait_intr(struct i801_priv *priv) | |
cf898dc5 | 331 | { |
cf898dc5 | 332 | int timeout = 0; |
6cad93c4 | 333 | int status; |
cf898dc5 JD |
334 | |
335 | /* We will always wait for a fraction of a second! */ | |
336 | do { | |
84c1af4c | 337 | usleep_range(250, 500); |
0cd96eb0 | 338 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
339 | } while (((status & SMBHSTSTS_HOST_BUSY) || |
340 | !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && | |
341 | (timeout++ < MAX_RETRIES)); | |
cf898dc5 | 342 | |
6cad93c4 JD |
343 | if (timeout > MAX_RETRIES) { |
344 | dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); | |
345 | return -ETIMEDOUT; | |
346 | } | |
347 | return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); | |
cf898dc5 JD |
348 | } |
349 | ||
6cad93c4 JD |
350 | /* Wait for either BYTE_DONE or an error flag being set */ |
351 | static int i801_wait_byte_done(struct i801_priv *priv) | |
ca8b9e32 OR |
352 | { |
353 | int timeout = 0; | |
2b73809d | 354 | int status; |
ca8b9e32 | 355 | |
6cad93c4 | 356 | /* We will always wait for a fraction of a second! */ |
ca8b9e32 | 357 | do { |
84c1af4c | 358 | usleep_range(250, 500); |
0cd96eb0 | 359 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
360 | } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && |
361 | (timeout++ < MAX_RETRIES)); | |
362 | ||
363 | if (timeout > MAX_RETRIES) { | |
364 | dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); | |
365 | return -ETIMEDOUT; | |
366 | } | |
367 | return status & STATUS_ERROR_FLAGS; | |
368 | } | |
369 | ||
370 | static int i801_transaction(struct i801_priv *priv, int xact) | |
371 | { | |
372 | int status; | |
373 | int result; | |
b3b8df97 | 374 | const struct i2c_adapter *adap = &priv->adapter; |
ca8b9e32 | 375 | |
6cad93c4 JD |
376 | result = i801_check_pre(priv); |
377 | if (result < 0) | |
378 | return result; | |
4ccc28f7 | 379 | |
636752bc DK |
380 | if (priv->features & FEATURE_IRQ) { |
381 | outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, | |
382 | SMBHSTCNT(priv)); | |
b3b8df97 JD |
383 | result = wait_event_timeout(priv->waitq, |
384 | (status = priv->status), | |
385 | adap->timeout); | |
386 | if (!result) { | |
387 | status = -ETIMEDOUT; | |
388 | dev_warn(&priv->pci_dev->dev, | |
389 | "Timeout waiting for interrupt!\n"); | |
390 | } | |
636752bc DK |
391 | priv->status = 0; |
392 | return i801_check_post(priv, status); | |
393 | } | |
394 | ||
6cad93c4 JD |
395 | /* the current contents of SMBHSTCNT can be overwritten, since PEC, |
396 | * SMBSCMD are passed in xact */ | |
397 | outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); | |
398 | ||
399 | status = i801_wait_intr(priv); | |
400 | return i801_check_post(priv, status); | |
ca8b9e32 OR |
401 | } |
402 | ||
0cd96eb0 DW |
403 | static int i801_block_transaction_by_block(struct i801_priv *priv, |
404 | union i2c_smbus_data *data, | |
7edcb9ab OR |
405 | char read_write, int hwpec) |
406 | { | |
407 | int i, len; | |
97140342 | 408 | int status; |
7edcb9ab | 409 | |
0cd96eb0 | 410 | inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ |
7edcb9ab OR |
411 | |
412 | /* Use 32-byte buffer to process this transaction */ | |
413 | if (read_write == I2C_SMBUS_WRITE) { | |
414 | len = data->block[0]; | |
0cd96eb0 | 415 | outb_p(len, SMBHSTDAT0(priv)); |
7edcb9ab | 416 | for (i = 0; i < len; i++) |
0cd96eb0 | 417 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
7edcb9ab OR |
418 | } |
419 | ||
37af8711 | 420 | status = i801_transaction(priv, I801_BLOCK_DATA | |
edbeea63 | 421 | (hwpec ? SMBHSTCNT_PEC_EN : 0)); |
97140342 DB |
422 | if (status) |
423 | return status; | |
7edcb9ab OR |
424 | |
425 | if (read_write == I2C_SMBUS_READ) { | |
0cd96eb0 | 426 | len = inb_p(SMBHSTDAT0(priv)); |
7edcb9ab | 427 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) |
97140342 | 428 | return -EPROTO; |
7edcb9ab OR |
429 | |
430 | data->block[0] = len; | |
431 | for (i = 0; i < len; i++) | |
0cd96eb0 | 432 | data->block[i + 1] = inb_p(SMBBLKDAT(priv)); |
7edcb9ab OR |
433 | } |
434 | return 0; | |
435 | } | |
436 | ||
d3ff6ce4 DK |
437 | static void i801_isr_byte_done(struct i801_priv *priv) |
438 | { | |
439 | if (priv->is_read) { | |
440 | /* For SMBus block reads, length is received with first byte */ | |
441 | if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && | |
442 | (priv->count == 0)) { | |
443 | priv->len = inb_p(SMBHSTDAT0(priv)); | |
444 | if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { | |
445 | dev_err(&priv->pci_dev->dev, | |
446 | "Illegal SMBus block read size %d\n", | |
447 | priv->len); | |
448 | /* FIXME: Recover */ | |
449 | priv->len = I2C_SMBUS_BLOCK_MAX; | |
450 | } else { | |
451 | dev_dbg(&priv->pci_dev->dev, | |
452 | "SMBus block read size is %d\n", | |
453 | priv->len); | |
454 | } | |
455 | priv->data[-1] = priv->len; | |
456 | } | |
457 | ||
458 | /* Read next byte */ | |
459 | if (priv->count < priv->len) | |
460 | priv->data[priv->count++] = inb(SMBBLKDAT(priv)); | |
461 | else | |
462 | dev_dbg(&priv->pci_dev->dev, | |
463 | "Discarding extra byte on block read\n"); | |
464 | ||
465 | /* Set LAST_BYTE for last byte of read transaction */ | |
466 | if (priv->count == priv->len - 1) | |
467 | outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, | |
468 | SMBHSTCNT(priv)); | |
469 | } else if (priv->count < priv->len - 1) { | |
470 | /* Write next byte, except for IRQ after last byte */ | |
471 | outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); | |
472 | } | |
473 | ||
474 | /* Clear BYTE_DONE to continue with next byte */ | |
475 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); | |
476 | } | |
477 | ||
636752bc | 478 | /* |
d3ff6ce4 DK |
479 | * There are two kinds of interrupts: |
480 | * | |
481 | * 1) i801 signals transaction completion with one of these interrupts: | |
482 | * INTR - Success | |
483 | * DEV_ERR - Invalid command, NAK or communication timeout | |
484 | * BUS_ERR - SMI# transaction collision | |
485 | * FAILED - transaction was canceled due to a KILL request | |
486 | * When any of these occur, update ->status and wake up the waitq. | |
487 | * ->status must be cleared before kicking off the next transaction. | |
488 | * | |
489 | * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt | |
490 | * occurs for each byte of a byte-by-byte to prepare the next byte. | |
636752bc DK |
491 | */ |
492 | static irqreturn_t i801_isr(int irq, void *dev_id) | |
493 | { | |
494 | struct i801_priv *priv = dev_id; | |
495 | u16 pcists; | |
496 | u8 status; | |
497 | ||
498 | /* Confirm this is our interrupt */ | |
499 | pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); | |
500 | if (!(pcists & SMBPCISTS_INTS)) | |
501 | return IRQ_NONE; | |
502 | ||
503 | status = inb_p(SMBHSTSTS(priv)); | |
504 | if (status != 0x42) | |
505 | dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status); | |
506 | ||
d3ff6ce4 DK |
507 | if (status & SMBHSTSTS_BYTE_DONE) |
508 | i801_isr_byte_done(priv); | |
509 | ||
636752bc DK |
510 | /* |
511 | * Clear irq sources and report transaction result. | |
512 | * ->status must be cleared before the next transaction is started. | |
513 | */ | |
514 | status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; | |
515 | if (status) { | |
516 | outb_p(status, SMBHSTSTS(priv)); | |
517 | priv->status |= status; | |
518 | wake_up(&priv->waitq); | |
519 | } | |
520 | ||
521 | return IRQ_HANDLED; | |
522 | } | |
523 | ||
efa3cb15 DK |
524 | /* |
525 | * For "byte-by-byte" block transactions: | |
526 | * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 | |
527 | * I2C read uses cmd=I801_I2C_BLOCK_DATA | |
528 | */ | |
0cd96eb0 DW |
529 | static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, |
530 | union i2c_smbus_data *data, | |
6342064c JD |
531 | char read_write, int command, |
532 | int hwpec) | |
1da177e4 LT |
533 | { |
534 | int i, len; | |
535 | int smbcmd; | |
2b73809d | 536 | int status; |
cf898dc5 | 537 | int result; |
b3b8df97 | 538 | const struct i2c_adapter *adap = &priv->adapter; |
cf898dc5 | 539 | |
0cd96eb0 | 540 | result = i801_check_pre(priv); |
cf898dc5 JD |
541 | if (result < 0) |
542 | return result; | |
1da177e4 | 543 | |
7edcb9ab | 544 | len = data->block[0]; |
1da177e4 LT |
545 | |
546 | if (read_write == I2C_SMBUS_WRITE) { | |
0cd96eb0 DW |
547 | outb_p(len, SMBHSTDAT0(priv)); |
548 | outb_p(data->block[1], SMBBLKDAT(priv)); | |
1da177e4 LT |
549 | } |
550 | ||
efa3cb15 DK |
551 | if (command == I2C_SMBUS_I2C_BLOCK_DATA && |
552 | read_write == I2C_SMBUS_READ) | |
553 | smbcmd = I801_I2C_BLOCK_DATA; | |
554 | else | |
555 | smbcmd = I801_BLOCK_DATA; | |
556 | ||
d3ff6ce4 DK |
557 | if (priv->features & FEATURE_IRQ) { |
558 | priv->is_read = (read_write == I2C_SMBUS_READ); | |
559 | if (len == 1 && priv->is_read) | |
560 | smbcmd |= SMBHSTCNT_LAST_BYTE; | |
561 | priv->cmd = smbcmd | SMBHSTCNT_INTREN; | |
562 | priv->len = len; | |
563 | priv->count = 0; | |
564 | priv->data = &data->block[1]; | |
565 | ||
566 | outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); | |
b3b8df97 JD |
567 | result = wait_event_timeout(priv->waitq, |
568 | (status = priv->status), | |
569 | adap->timeout); | |
570 | if (!result) { | |
571 | status = -ETIMEDOUT; | |
572 | dev_warn(&priv->pci_dev->dev, | |
573 | "Timeout waiting for interrupt!\n"); | |
574 | } | |
d3ff6ce4 DK |
575 | priv->status = 0; |
576 | return i801_check_post(priv, status); | |
577 | } | |
578 | ||
1da177e4 | 579 | for (i = 1; i <= len; i++) { |
efa3cb15 | 580 | if (i == len && read_write == I2C_SMBUS_READ) |
edbeea63 | 581 | smbcmd |= SMBHSTCNT_LAST_BYTE; |
37af8711 | 582 | outb_p(smbcmd, SMBHSTCNT(priv)); |
1da177e4 | 583 | |
1da177e4 | 584 | if (i == 1) |
edbeea63 | 585 | outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, |
0cd96eb0 | 586 | SMBHSTCNT(priv)); |
1da177e4 | 587 | |
6cad93c4 JD |
588 | status = i801_wait_byte_done(priv); |
589 | if (status) | |
590 | goto exit; | |
1da177e4 | 591 | |
6342064c JD |
592 | if (i == 1 && read_write == I2C_SMBUS_READ |
593 | && command != I2C_SMBUS_I2C_BLOCK_DATA) { | |
0cd96eb0 | 594 | len = inb_p(SMBHSTDAT0(priv)); |
cf898dc5 | 595 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { |
0cd96eb0 | 596 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
597 | "Illegal SMBus block read size %d\n", |
598 | len); | |
599 | /* Recover */ | |
0cd96eb0 DW |
600 | while (inb_p(SMBHSTSTS(priv)) & |
601 | SMBHSTSTS_HOST_BUSY) | |
602 | outb_p(SMBHSTSTS_BYTE_DONE, | |
603 | SMBHSTSTS(priv)); | |
604 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); | |
97140342 | 605 | return -EPROTO; |
cf898dc5 | 606 | } |
1da177e4 LT |
607 | data->block[0] = len; |
608 | } | |
609 | ||
610 | /* Retrieve/store value in SMBBLKDAT */ | |
611 | if (read_write == I2C_SMBUS_READ) | |
0cd96eb0 | 612 | data->block[i] = inb_p(SMBBLKDAT(priv)); |
1da177e4 | 613 | if (read_write == I2C_SMBUS_WRITE && i+1 <= len) |
0cd96eb0 | 614 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
1da177e4 | 615 | |
cf898dc5 | 616 | /* signals SMBBLKDAT ready */ |
6cad93c4 | 617 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); |
1da177e4 | 618 | } |
cf898dc5 | 619 | |
6cad93c4 JD |
620 | status = i801_wait_intr(priv); |
621 | exit: | |
622 | return i801_check_post(priv, status); | |
7edcb9ab | 623 | } |
1da177e4 | 624 | |
0cd96eb0 | 625 | static int i801_set_block_buffer_mode(struct i801_priv *priv) |
7edcb9ab | 626 | { |
0cd96eb0 DW |
627 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); |
628 | if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) | |
97140342 | 629 | return -EIO; |
7edcb9ab OR |
630 | return 0; |
631 | } | |
632 | ||
633 | /* Block transaction function */ | |
0cd96eb0 DW |
634 | static int i801_block_transaction(struct i801_priv *priv, |
635 | union i2c_smbus_data *data, char read_write, | |
7edcb9ab OR |
636 | int command, int hwpec) |
637 | { | |
638 | int result = 0; | |
639 | unsigned char hostc; | |
640 | ||
641 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
642 | if (read_write == I2C_SMBUS_WRITE) { | |
643 | /* set I2C_EN bit in configuration register */ | |
0cd96eb0 DW |
644 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); |
645 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, | |
7edcb9ab | 646 | hostc | SMBHSTCFG_I2C_EN); |
0cd96eb0 DW |
647 | } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { |
648 | dev_err(&priv->pci_dev->dev, | |
6342064c | 649 | "I2C block read is unsupported!\n"); |
97140342 | 650 | return -EOPNOTSUPP; |
7edcb9ab OR |
651 | } |
652 | } | |
653 | ||
6342064c JD |
654 | if (read_write == I2C_SMBUS_WRITE |
655 | || command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
7edcb9ab OR |
656 | if (data->block[0] < 1) |
657 | data->block[0] = 1; | |
658 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) | |
659 | data->block[0] = I2C_SMBUS_BLOCK_MAX; | |
660 | } else { | |
6342064c | 661 | data->block[0] = 32; /* max for SMBus block reads */ |
7edcb9ab OR |
662 | } |
663 | ||
c074c39d JD |
664 | /* Experience has shown that the block buffer can only be used for |
665 | SMBus (not I2C) block transactions, even though the datasheet | |
666 | doesn't mention this limitation. */ | |
0cd96eb0 | 667 | if ((priv->features & FEATURE_BLOCK_BUFFER) |
c074c39d | 668 | && command != I2C_SMBUS_I2C_BLOCK_DATA |
0cd96eb0 DW |
669 | && i801_set_block_buffer_mode(priv) == 0) |
670 | result = i801_block_transaction_by_block(priv, data, | |
671 | read_write, hwpec); | |
7edcb9ab | 672 | else |
0cd96eb0 DW |
673 | result = i801_block_transaction_byte_by_byte(priv, data, |
674 | read_write, | |
6342064c | 675 | command, hwpec); |
7edcb9ab | 676 | |
6342064c JD |
677 | if (command == I2C_SMBUS_I2C_BLOCK_DATA |
678 | && read_write == I2C_SMBUS_WRITE) { | |
1da177e4 | 679 | /* restore saved configuration register value */ |
0cd96eb0 | 680 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); |
1da177e4 LT |
681 | } |
682 | return result; | |
683 | } | |
684 | ||
97140342 | 685 | /* Return negative errno on error. */ |
3fb21c64 | 686 | static s32 i801_access(struct i2c_adapter *adap, u16 addr, |
1da177e4 | 687 | unsigned short flags, char read_write, u8 command, |
3fb21c64 | 688 | int size, union i2c_smbus_data *data) |
1da177e4 | 689 | { |
e8aac4a9 | 690 | int hwpec; |
1da177e4 LT |
691 | int block = 0; |
692 | int ret, xact = 0; | |
0cd96eb0 | 693 | struct i801_priv *priv = i2c_get_adapdata(adap); |
1da177e4 | 694 | |
0cd96eb0 | 695 | hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) |
e8aac4a9 JD |
696 | && size != I2C_SMBUS_QUICK |
697 | && size != I2C_SMBUS_I2C_BLOCK_DATA; | |
1da177e4 LT |
698 | |
699 | switch (size) { | |
700 | case I2C_SMBUS_QUICK: | |
701 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 702 | SMBHSTADD(priv)); |
1da177e4 LT |
703 | xact = I801_QUICK; |
704 | break; | |
705 | case I2C_SMBUS_BYTE: | |
706 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 707 | SMBHSTADD(priv)); |
1da177e4 | 708 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 709 | outb_p(command, SMBHSTCMD(priv)); |
1da177e4 LT |
710 | xact = I801_BYTE; |
711 | break; | |
712 | case I2C_SMBUS_BYTE_DATA: | |
713 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
714 | SMBHSTADD(priv)); |
715 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 716 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 717 | outb_p(data->byte, SMBHSTDAT0(priv)); |
1da177e4 LT |
718 | xact = I801_BYTE_DATA; |
719 | break; | |
720 | case I2C_SMBUS_WORD_DATA: | |
721 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
722 | SMBHSTADD(priv)); |
723 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 724 | if (read_write == I2C_SMBUS_WRITE) { |
0cd96eb0 DW |
725 | outb_p(data->word & 0xff, SMBHSTDAT0(priv)); |
726 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); | |
1da177e4 LT |
727 | } |
728 | xact = I801_WORD_DATA; | |
729 | break; | |
730 | case I2C_SMBUS_BLOCK_DATA: | |
1da177e4 | 731 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
0cd96eb0 DW |
732 | SMBHSTADD(priv)); |
733 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 LT |
734 | block = 1; |
735 | break; | |
6342064c JD |
736 | case I2C_SMBUS_I2C_BLOCK_DATA: |
737 | /* NB: page 240 of ICH5 datasheet shows that the R/#W | |
738 | * bit should be cleared here, even when reading */ | |
0cd96eb0 | 739 | outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); |
6342064c JD |
740 | if (read_write == I2C_SMBUS_READ) { |
741 | /* NB: page 240 of ICH5 datasheet also shows | |
742 | * that DATA1 is the cmd field when reading */ | |
0cd96eb0 | 743 | outb_p(command, SMBHSTDAT1(priv)); |
6342064c | 744 | } else |
0cd96eb0 | 745 | outb_p(command, SMBHSTCMD(priv)); |
6342064c JD |
746 | block = 1; |
747 | break; | |
1da177e4 | 748 | default: |
0cd96eb0 DW |
749 | dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", |
750 | size); | |
97140342 | 751 | return -EOPNOTSUPP; |
1da177e4 LT |
752 | } |
753 | ||
ca8b9e32 | 754 | if (hwpec) /* enable/disable hardware PEC */ |
0cd96eb0 | 755 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); |
ca8b9e32 | 756 | else |
0cd96eb0 DW |
757 | outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), |
758 | SMBAUXCTL(priv)); | |
e8aac4a9 | 759 | |
3fb21c64 | 760 | if (block) |
0cd96eb0 DW |
761 | ret = i801_block_transaction(priv, data, read_write, size, |
762 | hwpec); | |
7edcb9ab | 763 | else |
37af8711 | 764 | ret = i801_transaction(priv, xact); |
1da177e4 | 765 | |
c79cfbac | 766 | /* Some BIOSes don't like it when PEC is enabled at reboot or resume |
7edcb9ab OR |
767 | time, so we forcibly disable it after every transaction. Turn off |
768 | E32B for the same reason. */ | |
a0921b6c | 769 | if (hwpec || block) |
0cd96eb0 DW |
770 | outb_p(inb_p(SMBAUXCTL(priv)) & |
771 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
c79cfbac | 772 | |
3fb21c64 | 773 | if (block) |
1da177e4 | 774 | return ret; |
3fb21c64 | 775 | if (ret) |
97140342 | 776 | return ret; |
1da177e4 LT |
777 | if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) |
778 | return 0; | |
779 | ||
780 | switch (xact & 0x7f) { | |
781 | case I801_BYTE: /* Result put in SMBHSTDAT0 */ | |
782 | case I801_BYTE_DATA: | |
0cd96eb0 | 783 | data->byte = inb_p(SMBHSTDAT0(priv)); |
1da177e4 LT |
784 | break; |
785 | case I801_WORD_DATA: | |
0cd96eb0 DW |
786 | data->word = inb_p(SMBHSTDAT0(priv)) + |
787 | (inb_p(SMBHSTDAT1(priv)) << 8); | |
1da177e4 LT |
788 | break; |
789 | } | |
790 | return 0; | |
791 | } | |
792 | ||
793 | ||
794 | static u32 i801_func(struct i2c_adapter *adapter) | |
795 | { | |
0cd96eb0 DW |
796 | struct i801_priv *priv = i2c_get_adapdata(adapter); |
797 | ||
1da177e4 | 798 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | |
369f6f4a JD |
799 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | |
800 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | | |
0cd96eb0 DW |
801 | ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | |
802 | ((priv->features & FEATURE_I2C_BLOCK_READ) ? | |
6342064c | 803 | I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); |
1da177e4 LT |
804 | } |
805 | ||
8f9082c5 | 806 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
807 | .smbus_xfer = i801_access, |
808 | .functionality = i801_func, | |
809 | }; | |
810 | ||
392debf1 | 811 | static const struct pci_device_id i801_ids[] = { |
1da177e4 LT |
812 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, |
813 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, | |
814 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, | |
815 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, | |
816 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, | |
817 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, | |
818 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, | |
819 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, | |
820 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, | |
b0a70b57 | 821 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, |
8254fc4a | 822 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, |
adbc2a10 | 823 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, |
cb04e95b | 824 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, |
d28dc711 GJ |
825 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, |
826 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, | |
cb04e95b SH |
827 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, |
828 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, | |
e30d9859 | 829 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, |
55fee8d7 DW |
830 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, |
831 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, | |
832 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, | |
662cda8a | 833 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, |
6e2a851e | 834 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, |
062737fb | 835 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, |
4a8f1ddd | 836 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, |
c2db409c | 837 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, |
a3fc0ff0 JR |
838 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, |
839 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, | |
840 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, | |
841 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, | |
f39901c1 | 842 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, |
b299de83 | 843 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, |
afc65924 | 844 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, |
1b31e9b7 | 845 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, |
39e8e30e | 846 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, |
3e27a844 | 847 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, |
1da177e4 LT |
848 | { 0, } |
849 | }; | |
850 | ||
3fb21c64 | 851 | MODULE_DEVICE_TABLE(pci, i801_ids); |
1da177e4 | 852 | |
8eacfceb | 853 | #if defined CONFIG_X86 && defined CONFIG_DMI |
1561bfe5 JD |
854 | static unsigned char apanel_addr; |
855 | ||
856 | /* Scan the system ROM for the signature "FJKEYINF" */ | |
857 | static __init const void __iomem *bios_signature(const void __iomem *bios) | |
858 | { | |
859 | ssize_t offset; | |
860 | const unsigned char signature[] = "FJKEYINF"; | |
861 | ||
862 | for (offset = 0; offset < 0x10000; offset += 0x10) { | |
863 | if (check_signature(bios + offset, signature, | |
864 | sizeof(signature)-1)) | |
865 | return bios + offset; | |
866 | } | |
867 | return NULL; | |
868 | } | |
869 | ||
870 | static void __init input_apanel_init(void) | |
871 | { | |
872 | void __iomem *bios; | |
873 | const void __iomem *p; | |
874 | ||
875 | bios = ioremap(0xF0000, 0x10000); /* Can't fail */ | |
876 | p = bios_signature(bios); | |
877 | if (p) { | |
878 | /* just use the first address */ | |
879 | apanel_addr = readb(p + 8 + 3) >> 1; | |
880 | } | |
881 | iounmap(bios); | |
882 | } | |
1561bfe5 | 883 | |
fa5bfab7 HG |
884 | struct dmi_onboard_device_info { |
885 | const char *name; | |
886 | u8 type; | |
887 | unsigned short i2c_addr; | |
888 | const char *i2c_type; | |
889 | }; | |
890 | ||
0b255e92 | 891 | static const struct dmi_onboard_device_info dmi_devices[] = { |
fa5bfab7 HG |
892 | { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, |
893 | { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, | |
894 | { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, | |
895 | }; | |
896 | ||
0b255e92 BP |
897 | static void dmi_check_onboard_device(u8 type, const char *name, |
898 | struct i2c_adapter *adap) | |
fa5bfab7 HG |
899 | { |
900 | int i; | |
901 | struct i2c_board_info info; | |
902 | ||
903 | for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { | |
904 | /* & ~0x80, ignore enabled/disabled bit */ | |
905 | if ((type & ~0x80) != dmi_devices[i].type) | |
906 | continue; | |
faabd47f | 907 | if (strcasecmp(name, dmi_devices[i].name)) |
fa5bfab7 HG |
908 | continue; |
909 | ||
910 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
911 | info.addr = dmi_devices[i].i2c_addr; | |
912 | strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); | |
913 | i2c_new_device(adap, &info); | |
914 | break; | |
915 | } | |
916 | } | |
917 | ||
918 | /* We use our own function to check for onboard devices instead of | |
919 | dmi_find_device() as some buggy BIOS's have the devices we are interested | |
920 | in marked as disabled */ | |
0b255e92 | 921 | static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) |
fa5bfab7 HG |
922 | { |
923 | int i, count; | |
924 | ||
925 | if (dm->type != 10) | |
926 | return; | |
927 | ||
928 | count = (dm->length - sizeof(struct dmi_header)) / 2; | |
929 | for (i = 0; i < count; i++) { | |
930 | const u8 *d = (char *)(dm + 1) + (i * 2); | |
931 | const char *name = ((char *) dm) + dm->length; | |
932 | u8 type = d[0]; | |
933 | u8 s = d[1]; | |
934 | ||
935 | if (!s) | |
936 | continue; | |
937 | s--; | |
938 | while (s > 0 && name[0]) { | |
939 | name += strlen(name) + 1; | |
940 | s--; | |
941 | } | |
942 | if (name[0] == 0) /* Bogus string reference */ | |
943 | continue; | |
944 | ||
945 | dmi_check_onboard_device(type, name, adap); | |
946 | } | |
947 | } | |
fa5bfab7 | 948 | |
e7198fbf | 949 | /* Register optional slaves */ |
0b255e92 | 950 | static void i801_probe_optional_slaves(struct i801_priv *priv) |
e7198fbf JD |
951 | { |
952 | /* Only register slaves on main SMBus channel */ | |
953 | if (priv->features & FEATURE_IDF) | |
954 | return; | |
955 | ||
e7198fbf JD |
956 | if (apanel_addr) { |
957 | struct i2c_board_info info; | |
958 | ||
959 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
960 | info.addr = apanel_addr; | |
961 | strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); | |
962 | i2c_new_device(&priv->adapter, &info); | |
963 | } | |
8eacfceb | 964 | |
e7198fbf JD |
965 | if (dmi_name_in_vendors("FUJITSU")) |
966 | dmi_walk(dmi_check_onboard_devices, &priv->adapter); | |
e7198fbf | 967 | } |
8eacfceb JD |
968 | #else |
969 | static void __init input_apanel_init(void) {} | |
0b255e92 | 970 | static void i801_probe_optional_slaves(struct i801_priv *priv) {} |
8eacfceb | 971 | #endif /* CONFIG_X86 && CONFIG_DMI */ |
e7198fbf | 972 | |
79e3e5b8 JD |
973 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
974 | defined CONFIG_DMI | |
3ad7ea18 JD |
975 | static struct i801_mux_config i801_mux_config_asus_z8_d12 = { |
976 | .gpio_chip = "gpio_ich", | |
977 | .values = { 0x02, 0x03 }, | |
978 | .n_values = 2, | |
979 | .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, | |
980 | .gpios = { 52, 53 }, | |
981 | .n_gpios = 2, | |
982 | }; | |
983 | ||
984 | static struct i801_mux_config i801_mux_config_asus_z8_d18 = { | |
985 | .gpio_chip = "gpio_ich", | |
986 | .values = { 0x02, 0x03, 0x01 }, | |
987 | .n_values = 3, | |
988 | .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, | |
989 | .gpios = { 52, 53 }, | |
990 | .n_gpios = 2, | |
991 | }; | |
992 | ||
0b255e92 | 993 | static const struct dmi_system_id mux_dmi_table[] = { |
3ad7ea18 JD |
994 | { |
995 | .matches = { | |
996 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
997 | DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), | |
998 | }, | |
999 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1000 | }, | |
1001 | { | |
1002 | .matches = { | |
1003 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1004 | DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), | |
1005 | }, | |
1006 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1007 | }, | |
1008 | { | |
1009 | .matches = { | |
1010 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1011 | DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), | |
1012 | }, | |
1013 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1014 | }, | |
1015 | { | |
1016 | .matches = { | |
1017 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1018 | DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), | |
1019 | }, | |
1020 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1021 | }, | |
1022 | { | |
1023 | .matches = { | |
1024 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1025 | DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), | |
1026 | }, | |
1027 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1028 | }, | |
1029 | { | |
1030 | .matches = { | |
1031 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1032 | DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), | |
1033 | }, | |
1034 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1035 | }, | |
1036 | { | |
1037 | .matches = { | |
1038 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1039 | DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), | |
1040 | }, | |
1041 | .driver_data = &i801_mux_config_asus_z8_d18, | |
1042 | }, | |
1043 | { | |
1044 | .matches = { | |
1045 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1046 | DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), | |
1047 | }, | |
1048 | .driver_data = &i801_mux_config_asus_z8_d18, | |
1049 | }, | |
1050 | { | |
1051 | .matches = { | |
1052 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1053 | DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), | |
1054 | }, | |
1055 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1056 | }, | |
1057 | { } | |
1058 | }; | |
1059 | ||
3ad7ea18 | 1060 | /* Setup multiplexing if needed */ |
0b255e92 | 1061 | static int i801_add_mux(struct i801_priv *priv) |
3ad7ea18 JD |
1062 | { |
1063 | struct device *dev = &priv->adapter.dev; | |
1064 | const struct i801_mux_config *mux_config; | |
3ad7ea18 | 1065 | struct i2c_mux_gpio_platform_data gpio_data; |
f82b8626 | 1066 | int err; |
3ad7ea18 JD |
1067 | |
1068 | if (!priv->mux_drvdata) | |
1069 | return 0; | |
1070 | mux_config = priv->mux_drvdata; | |
1071 | ||
3ad7ea18 JD |
1072 | /* Prepare the platform data */ |
1073 | memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); | |
1074 | gpio_data.parent = priv->adapter.nr; | |
1075 | gpio_data.values = mux_config->values; | |
1076 | gpio_data.n_values = mux_config->n_values; | |
1077 | gpio_data.classes = mux_config->classes; | |
f82b8626 JD |
1078 | gpio_data.gpio_chip = mux_config->gpio_chip; |
1079 | gpio_data.gpios = mux_config->gpios; | |
3ad7ea18 JD |
1080 | gpio_data.n_gpios = mux_config->n_gpios; |
1081 | gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; | |
1082 | ||
1083 | /* Register the mux device */ | |
1084 | priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", | |
f82b8626 | 1085 | PLATFORM_DEVID_AUTO, &gpio_data, |
3ad7ea18 JD |
1086 | sizeof(struct i2c_mux_gpio_platform_data)); |
1087 | if (IS_ERR(priv->mux_pdev)) { | |
1088 | err = PTR_ERR(priv->mux_pdev); | |
1089 | priv->mux_pdev = NULL; | |
1090 | dev_err(dev, "Failed to register i2c-mux-gpio device\n"); | |
1091 | return err; | |
1092 | } | |
1093 | ||
1094 | return 0; | |
1095 | } | |
1096 | ||
0b255e92 | 1097 | static void i801_del_mux(struct i801_priv *priv) |
3ad7ea18 JD |
1098 | { |
1099 | if (priv->mux_pdev) | |
1100 | platform_device_unregister(priv->mux_pdev); | |
1101 | } | |
1102 | ||
0b255e92 | 1103 | static unsigned int i801_get_adapter_class(struct i801_priv *priv) |
3ad7ea18 JD |
1104 | { |
1105 | const struct dmi_system_id *id; | |
1106 | const struct i801_mux_config *mux_config; | |
1107 | unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1108 | int i; | |
1109 | ||
1110 | id = dmi_first_match(mux_dmi_table); | |
1111 | if (id) { | |
28901f57 | 1112 | /* Remove branch classes from trunk */ |
3ad7ea18 JD |
1113 | mux_config = id->driver_data; |
1114 | for (i = 0; i < mux_config->n_values; i++) | |
1115 | class &= ~mux_config->classes[i]; | |
1116 | ||
1117 | /* Remember for later */ | |
1118 | priv->mux_drvdata = mux_config; | |
1119 | } | |
1120 | ||
1121 | return class; | |
1122 | } | |
1123 | #else | |
1124 | static inline int i801_add_mux(struct i801_priv *priv) { return 0; } | |
1125 | static inline void i801_del_mux(struct i801_priv *priv) { } | |
1126 | ||
1127 | static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) | |
1128 | { | |
1129 | return I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1130 | } | |
1131 | #endif | |
1132 | ||
0b255e92 | 1133 | static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) |
1da177e4 | 1134 | { |
02dd7ae2 | 1135 | unsigned char temp; |
adff687d | 1136 | int err, i; |
0cd96eb0 DW |
1137 | struct i801_priv *priv; |
1138 | ||
1139 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
1140 | if (!priv) | |
1141 | return -ENOMEM; | |
1142 | ||
1143 | i2c_set_adapdata(&priv->adapter, priv); | |
1144 | priv->adapter.owner = THIS_MODULE; | |
3ad7ea18 | 1145 | priv->adapter.class = i801_get_adapter_class(priv); |
0cd96eb0 | 1146 | priv->adapter.algo = &smbus_algorithm; |
1da177e4 | 1147 | |
0cd96eb0 | 1148 | priv->pci_dev = dev; |
250d1bd3 | 1149 | switch (dev->device) { |
e7198fbf JD |
1150 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: |
1151 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: | |
1152 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: | |
a3fc0ff0 JR |
1153 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: |
1154 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: | |
1155 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: | |
e7198fbf JD |
1156 | priv->features |= FEATURE_IDF; |
1157 | /* fall through */ | |
e0e8398c | 1158 | default: |
0cd96eb0 | 1159 | priv->features |= FEATURE_I2C_BLOCK_READ; |
6676a847 | 1160 | priv->features |= FEATURE_IRQ; |
6342064c JD |
1161 | /* fall through */ |
1162 | case PCI_DEVICE_ID_INTEL_82801DB_3: | |
0cd96eb0 DW |
1163 | priv->features |= FEATURE_SMBUS_PEC; |
1164 | priv->features |= FEATURE_BLOCK_BUFFER; | |
e0e8398c JD |
1165 | /* fall through */ |
1166 | case PCI_DEVICE_ID_INTEL_82801CA_3: | |
1167 | case PCI_DEVICE_ID_INTEL_82801BA_2: | |
1168 | case PCI_DEVICE_ID_INTEL_82801AB_3: | |
1169 | case PCI_DEVICE_ID_INTEL_82801AA_3: | |
250d1bd3 | 1170 | break; |
250d1bd3 | 1171 | } |
02dd7ae2 | 1172 | |
adff687d JD |
1173 | /* Disable features on user request */ |
1174 | for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { | |
0cd96eb0 | 1175 | if (priv->features & disable_features & (1 << i)) |
adff687d JD |
1176 | dev_notice(&dev->dev, "%s disabled by user\n", |
1177 | i801_feature_names[i]); | |
1178 | } | |
0cd96eb0 | 1179 | priv->features &= ~disable_features; |
adff687d | 1180 | |
02dd7ae2 JD |
1181 | err = pci_enable_device(dev); |
1182 | if (err) { | |
1183 | dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", | |
1184 | err); | |
1185 | goto exit; | |
1186 | } | |
1187 | ||
1188 | /* Determine the address of the SMBus area */ | |
0cd96eb0 DW |
1189 | priv->smba = pci_resource_start(dev, SMBBAR); |
1190 | if (!priv->smba) { | |
02dd7ae2 JD |
1191 | dev_err(&dev->dev, "SMBus base address uninitialized, " |
1192 | "upgrade BIOS\n"); | |
1193 | err = -ENODEV; | |
d6fcb3b9 | 1194 | goto exit; |
02dd7ae2 JD |
1195 | } |
1196 | ||
54fb4a05 | 1197 | err = acpi_check_resource_conflict(&dev->resource[SMBBAR]); |
18669eab JD |
1198 | if (err) { |
1199 | err = -ENODEV; | |
54fb4a05 | 1200 | goto exit; |
18669eab | 1201 | } |
54fb4a05 | 1202 | |
02dd7ae2 JD |
1203 | err = pci_request_region(dev, SMBBAR, i801_driver.name); |
1204 | if (err) { | |
1205 | dev_err(&dev->dev, "Failed to request SMBus region " | |
0cd96eb0 | 1206 | "0x%lx-0x%Lx\n", priv->smba, |
598736c5 | 1207 | (unsigned long long)pci_resource_end(dev, SMBBAR)); |
d6fcb3b9 | 1208 | goto exit; |
02dd7ae2 JD |
1209 | } |
1210 | ||
0cd96eb0 DW |
1211 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); |
1212 | priv->original_hstcfg = temp; | |
02dd7ae2 JD |
1213 | temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ |
1214 | if (!(temp & SMBHSTCFG_HST_EN)) { | |
1215 | dev_info(&dev->dev, "Enabling SMBus device\n"); | |
1216 | temp |= SMBHSTCFG_HST_EN; | |
1217 | } | |
0cd96eb0 | 1218 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); |
02dd7ae2 | 1219 | |
636752bc | 1220 | if (temp & SMBHSTCFG_SMB_SMI_EN) { |
02dd7ae2 | 1221 | dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); |
636752bc DK |
1222 | /* Disable SMBus interrupt feature if SMBus using SMI# */ |
1223 | priv->features &= ~FEATURE_IRQ; | |
636752bc | 1224 | } |
1da177e4 | 1225 | |
a0921b6c | 1226 | /* Clear special mode bits */ |
0cd96eb0 DW |
1227 | if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) |
1228 | outb_p(inb_p(SMBAUXCTL(priv)) & | |
1229 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
a0921b6c | 1230 | |
b3b8df97 JD |
1231 | /* Default timeout in interrupt mode: 200 ms */ |
1232 | priv->adapter.timeout = HZ / 5; | |
1233 | ||
636752bc DK |
1234 | if (priv->features & FEATURE_IRQ) { |
1235 | init_waitqueue_head(&priv->waitq); | |
1236 | ||
1237 | err = request_irq(dev->irq, i801_isr, IRQF_SHARED, | |
1238 | i801_driver.name, priv); | |
1239 | if (err) { | |
1240 | dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", | |
1241 | dev->irq, err); | |
ae944717 | 1242 | priv->features &= ~FEATURE_IRQ; |
636752bc DK |
1243 | } |
1244 | } | |
ae944717 JD |
1245 | dev_info(&dev->dev, "SMBus using %s\n", |
1246 | priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); | |
636752bc | 1247 | |
405ae7d3 | 1248 | /* set up the sysfs linkage to our parent device */ |
0cd96eb0 | 1249 | priv->adapter.dev.parent = &dev->dev; |
1da177e4 | 1250 | |
7e2193a8 | 1251 | /* Retry up to 3 times on lost arbitration */ |
0cd96eb0 | 1252 | priv->adapter.retries = 3; |
7e2193a8 | 1253 | |
0cd96eb0 DW |
1254 | snprintf(priv->adapter.name, sizeof(priv->adapter.name), |
1255 | "SMBus I801 adapter at %04lx", priv->smba); | |
1256 | err = i2c_add_adapter(&priv->adapter); | |
02dd7ae2 JD |
1257 | if (err) { |
1258 | dev_err(&dev->dev, "Failed to add SMBus adapter\n"); | |
636752bc | 1259 | goto exit_free_irq; |
02dd7ae2 | 1260 | } |
1561bfe5 | 1261 | |
e7198fbf | 1262 | i801_probe_optional_slaves(priv); |
3ad7ea18 JD |
1263 | /* We ignore errors - multiplexing is optional */ |
1264 | i801_add_mux(priv); | |
1561bfe5 | 1265 | |
0cd96eb0 | 1266 | pci_set_drvdata(dev, priv); |
636752bc | 1267 | |
d6fcb3b9 | 1268 | return 0; |
02dd7ae2 | 1269 | |
636752bc DK |
1270 | exit_free_irq: |
1271 | if (priv->features & FEATURE_IRQ) | |
1272 | free_irq(dev->irq, priv); | |
d6fcb3b9 | 1273 | pci_release_region(dev, SMBBAR); |
02dd7ae2 | 1274 | exit: |
0cd96eb0 | 1275 | kfree(priv); |
02dd7ae2 | 1276 | return err; |
1da177e4 LT |
1277 | } |
1278 | ||
0b255e92 | 1279 | static void i801_remove(struct pci_dev *dev) |
1da177e4 | 1280 | { |
0cd96eb0 DW |
1281 | struct i801_priv *priv = pci_get_drvdata(dev); |
1282 | ||
3ad7ea18 | 1283 | i801_del_mux(priv); |
0cd96eb0 DW |
1284 | i2c_del_adapter(&priv->adapter); |
1285 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); | |
636752bc DK |
1286 | |
1287 | if (priv->features & FEATURE_IRQ) | |
1288 | free_irq(dev->irq, priv); | |
6dcc19df | 1289 | pci_release_region(dev, SMBBAR); |
636752bc | 1290 | |
0cd96eb0 | 1291 | kfree(priv); |
d6fcb3b9 DR |
1292 | /* |
1293 | * do not call pci_disable_device(dev) since it can cause hard hangs on | |
1294 | * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) | |
1295 | */ | |
1da177e4 LT |
1296 | } |
1297 | ||
a5aaea37 JD |
1298 | #ifdef CONFIG_PM |
1299 | static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) | |
1300 | { | |
0cd96eb0 DW |
1301 | struct i801_priv *priv = pci_get_drvdata(dev); |
1302 | ||
a5aaea37 | 1303 | pci_save_state(dev); |
0cd96eb0 | 1304 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); |
a5aaea37 JD |
1305 | pci_set_power_state(dev, pci_choose_state(dev, mesg)); |
1306 | return 0; | |
1307 | } | |
1308 | ||
1309 | static int i801_resume(struct pci_dev *dev) | |
1310 | { | |
1311 | pci_set_power_state(dev, PCI_D0); | |
1312 | pci_restore_state(dev); | |
1313 | return pci_enable_device(dev); | |
1314 | } | |
1315 | #else | |
1316 | #define i801_suspend NULL | |
1317 | #define i801_resume NULL | |
1318 | #endif | |
1319 | ||
1da177e4 LT |
1320 | static struct pci_driver i801_driver = { |
1321 | .name = "i801_smbus", | |
1322 | .id_table = i801_ids, | |
1323 | .probe = i801_probe, | |
0b255e92 | 1324 | .remove = i801_remove, |
a5aaea37 JD |
1325 | .suspend = i801_suspend, |
1326 | .resume = i801_resume, | |
1da177e4 LT |
1327 | }; |
1328 | ||
1329 | static int __init i2c_i801_init(void) | |
1330 | { | |
6aa1464d JD |
1331 | if (dmi_name_in_vendors("FUJITSU")) |
1332 | input_apanel_init(); | |
1da177e4 LT |
1333 | return pci_register_driver(&i801_driver); |
1334 | } | |
1335 | ||
1336 | static void __exit i2c_i801_exit(void) | |
1337 | { | |
1338 | pci_unregister_driver(&i801_driver); | |
1339 | } | |
1340 | ||
7c81c60f | 1341 | MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>"); |
1da177e4 LT |
1342 | MODULE_DESCRIPTION("I801 SMBus driver"); |
1343 | MODULE_LICENSE("GPL"); | |
1344 | ||
1345 | module_init(i2c_i801_init); | |
1346 | module_exit(i2c_i801_exit); |