Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, |
3 | Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker | |
4 | <mdsxyz123@yahoo.com> | |
cf898dc5 | 5 | Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org> |
1da177e4 LT |
6 | |
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | */ | |
21 | ||
22 | /* | |
ae7b0497 JD |
23 | Supports the following Intel I/O Controller Hubs (ICH): |
24 | ||
25 | I/O Block I2C | |
26 | region SMBus Block proc. block | |
27 | Chip name PCI ID size PEC buffer call read | |
28 | ---------------------------------------------------------------------- | |
29 | 82801AA (ICH) 0x2413 16 no no no no | |
30 | 82801AB (ICH0) 0x2423 16 no no no no | |
31 | 82801BA (ICH2) 0x2443 16 no no no no | |
32 | 82801CA (ICH3) 0x2483 32 soft no no no | |
33 | 82801DB (ICH4) 0x24c3 32 hard yes no no | |
34 | 82801E (ICH5) 0x24d3 32 hard yes yes yes | |
35 | 6300ESB 0x25a4 32 hard yes yes yes | |
36 | 82801F (ICH6) 0x266a 32 hard yes yes yes | |
37 | 6310ESB/6320ESB 0x269b 32 hard yes yes yes | |
38 | 82801G (ICH7) 0x27da 32 hard yes yes yes | |
39 | 82801H (ICH8) 0x283e 32 hard yes yes yes | |
40 | 82801I (ICH9) 0x2930 32 hard yes yes yes | |
d28dc711 GJ |
41 | Tolapai 0x5032 32 hard yes yes yes |
42 | ICH10 0x3a30 32 hard yes yes yes | |
43 | ICH10 0x3a60 32 hard yes yes yes | |
c429a247 | 44 | PCH 0x3b30 32 hard yes yes yes |
ae7b0497 JD |
45 | |
46 | Features supported by this driver: | |
47 | Software PEC no | |
48 | Hardware PEC yes | |
49 | Block buffer yes | |
50 | Block process call transaction no | |
6342064c | 51 | I2C block read transaction yes (doesn't use the block buffer) |
ae7b0497 JD |
52 | |
53 | See the file Documentation/i2c/busses/i2c-i801 for details. | |
1da177e4 LT |
54 | */ |
55 | ||
56 | /* Note: we assume there can only be one I801, with one SMBus interface */ | |
57 | ||
1da177e4 LT |
58 | #include <linux/module.h> |
59 | #include <linux/pci.h> | |
60 | #include <linux/kernel.h> | |
61 | #include <linux/stddef.h> | |
62 | #include <linux/delay.h> | |
1da177e4 LT |
63 | #include <linux/ioport.h> |
64 | #include <linux/init.h> | |
65 | #include <linux/i2c.h> | |
54fb4a05 | 66 | #include <linux/acpi.h> |
1561bfe5 | 67 | #include <linux/io.h> |
fa5bfab7 | 68 | #include <linux/dmi.h> |
1da177e4 | 69 | |
1da177e4 LT |
70 | /* I801 SMBus address offsets */ |
71 | #define SMBHSTSTS (0 + i801_smba) | |
72 | #define SMBHSTCNT (2 + i801_smba) | |
73 | #define SMBHSTCMD (3 + i801_smba) | |
74 | #define SMBHSTADD (4 + i801_smba) | |
75 | #define SMBHSTDAT0 (5 + i801_smba) | |
76 | #define SMBHSTDAT1 (6 + i801_smba) | |
77 | #define SMBBLKDAT (7 + i801_smba) | |
ae7b0497 JD |
78 | #define SMBPEC (8 + i801_smba) /* ICH3 and later */ |
79 | #define SMBAUXSTS (12 + i801_smba) /* ICH4 and later */ | |
80 | #define SMBAUXCTL (13 + i801_smba) /* ICH4 and later */ | |
1da177e4 LT |
81 | |
82 | /* PCI Address Constants */ | |
6dcc19df | 83 | #define SMBBAR 4 |
1da177e4 | 84 | #define SMBHSTCFG 0x040 |
1da177e4 LT |
85 | |
86 | /* Host configuration bits for SMBHSTCFG */ | |
87 | #define SMBHSTCFG_HST_EN 1 | |
88 | #define SMBHSTCFG_SMB_SMI_EN 2 | |
89 | #define SMBHSTCFG_I2C_EN 4 | |
90 | ||
ca8b9e32 OR |
91 | /* Auxillary control register bits, ICH4+ only */ |
92 | #define SMBAUXCTL_CRC 1 | |
93 | #define SMBAUXCTL_E32B 2 | |
94 | ||
95 | /* kill bit for SMBHSTCNT */ | |
96 | #define SMBHSTCNT_KILL 2 | |
97 | ||
1da177e4 LT |
98 | /* Other settings */ |
99 | #define MAX_TIMEOUT 100 | |
100 | #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */ | |
101 | ||
102 | /* I801 command constants */ | |
103 | #define I801_QUICK 0x00 | |
104 | #define I801_BYTE 0x04 | |
105 | #define I801_BYTE_DATA 0x08 | |
106 | #define I801_WORD_DATA 0x0C | |
ae7b0497 | 107 | #define I801_PROC_CALL 0x10 /* unimplemented */ |
1da177e4 | 108 | #define I801_BLOCK_DATA 0x14 |
6342064c | 109 | #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ |
1da177e4 | 110 | #define I801_BLOCK_LAST 0x34 |
6342064c | 111 | #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */ |
1da177e4 | 112 | #define I801_START 0x40 |
ae7b0497 | 113 | #define I801_PEC_EN 0x80 /* ICH3 and later */ |
1da177e4 | 114 | |
ca8b9e32 OR |
115 | /* I801 Hosts Status register bits */ |
116 | #define SMBHSTSTS_BYTE_DONE 0x80 | |
117 | #define SMBHSTSTS_INUSE_STS 0x40 | |
118 | #define SMBHSTSTS_SMBALERT_STS 0x20 | |
119 | #define SMBHSTSTS_FAILED 0x10 | |
120 | #define SMBHSTSTS_BUS_ERR 0x08 | |
121 | #define SMBHSTSTS_DEV_ERR 0x04 | |
122 | #define SMBHSTSTS_INTR 0x02 | |
123 | #define SMBHSTSTS_HOST_BUSY 0x01 | |
1da177e4 | 124 | |
cf898dc5 JD |
125 | #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \ |
126 | SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \ | |
127 | SMBHSTSTS_INTR) | |
128 | ||
6dcc19df | 129 | static unsigned long i801_smba; |
a5aaea37 | 130 | static unsigned char i801_original_hstcfg; |
d6072f84 | 131 | static struct pci_driver i801_driver; |
1da177e4 | 132 | static struct pci_dev *I801_dev; |
369f6f4a JD |
133 | |
134 | #define FEATURE_SMBUS_PEC (1 << 0) | |
135 | #define FEATURE_BLOCK_BUFFER (1 << 1) | |
136 | #define FEATURE_BLOCK_PROC (1 << 2) | |
137 | #define FEATURE_I2C_BLOCK_READ (1 << 3) | |
138 | static unsigned int i801_features; | |
1da177e4 | 139 | |
cf898dc5 JD |
140 | /* Make sure the SMBus host is ready to start transmitting. |
141 | Return 0 if it is, -EBUSY if it is not. */ | |
142 | static int i801_check_pre(void) | |
1da177e4 | 143 | { |
2b73809d | 144 | int status; |
1da177e4 | 145 | |
cf898dc5 JD |
146 | status = inb_p(SMBHSTSTS); |
147 | if (status & SMBHSTSTS_HOST_BUSY) { | |
148 | dev_err(&I801_dev->dev, "SMBus is busy, can't use it!\n"); | |
149 | return -EBUSY; | |
150 | } | |
151 | ||
152 | status &= STATUS_FLAGS; | |
153 | if (status) { | |
154 | dev_dbg(&I801_dev->dev, "Clearing status flags (%02x)\n", | |
2b73809d JD |
155 | status); |
156 | outb_p(status, SMBHSTSTS); | |
cf898dc5 JD |
157 | status = inb_p(SMBHSTSTS) & STATUS_FLAGS; |
158 | if (status) { | |
159 | dev_err(&I801_dev->dev, | |
160 | "Failed clearing status flags (%02x)\n", | |
161 | status); | |
97140342 | 162 | return -EBUSY; |
1da177e4 LT |
163 | } |
164 | } | |
165 | ||
cf898dc5 JD |
166 | return 0; |
167 | } | |
1da177e4 | 168 | |
cf898dc5 JD |
169 | /* Convert the status register to an error code, and clear it. */ |
170 | static int i801_check_post(int status, int timeout) | |
171 | { | |
172 | int result = 0; | |
1da177e4 LT |
173 | |
174 | /* If the SMBus is still busy, we give up */ | |
cf898dc5 JD |
175 | if (timeout) { |
176 | dev_err(&I801_dev->dev, "Transaction timeout\n"); | |
ca8b9e32 OR |
177 | /* try to stop the current command */ |
178 | dev_dbg(&I801_dev->dev, "Terminating the current operation\n"); | |
179 | outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT); | |
180 | msleep(1); | |
181 | outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT); | |
cf898dc5 JD |
182 | |
183 | /* Check if it worked */ | |
184 | status = inb_p(SMBHSTSTS); | |
185 | if ((status & SMBHSTSTS_HOST_BUSY) || | |
186 | !(status & SMBHSTSTS_FAILED)) | |
187 | dev_err(&I801_dev->dev, | |
188 | "Failed terminating the transaction\n"); | |
189 | outb_p(STATUS_FLAGS, SMBHSTSTS); | |
190 | return -ETIMEDOUT; | |
1da177e4 LT |
191 | } |
192 | ||
2b73809d | 193 | if (status & SMBHSTSTS_FAILED) { |
97140342 | 194 | result = -EIO; |
cf898dc5 JD |
195 | dev_err(&I801_dev->dev, "Transaction failed\n"); |
196 | } | |
197 | if (status & SMBHSTSTS_DEV_ERR) { | |
198 | result = -ENXIO; | |
199 | dev_dbg(&I801_dev->dev, "No response\n"); | |
1da177e4 | 200 | } |
2b73809d | 201 | if (status & SMBHSTSTS_BUS_ERR) { |
dcb5c923 JD |
202 | result = -EAGAIN; |
203 | dev_dbg(&I801_dev->dev, "Lost arbitration\n"); | |
1da177e4 LT |
204 | } |
205 | ||
cf898dc5 JD |
206 | if (result) { |
207 | /* Clear error flags */ | |
208 | outb_p(status & STATUS_FLAGS, SMBHSTSTS); | |
209 | status = inb_p(SMBHSTSTS) & STATUS_FLAGS; | |
210 | if (status) { | |
211 | dev_warn(&I801_dev->dev, "Failed clearing status " | |
212 | "flags at end of transaction (%02x)\n", | |
213 | status); | |
214 | } | |
1da177e4 LT |
215 | } |
216 | ||
1da177e4 LT |
217 | return result; |
218 | } | |
219 | ||
cf898dc5 JD |
220 | static int i801_transaction(int xact) |
221 | { | |
222 | int status; | |
223 | int result; | |
224 | int timeout = 0; | |
225 | ||
226 | result = i801_check_pre(); | |
227 | if (result < 0) | |
228 | return result; | |
229 | ||
230 | /* the current contents of SMBHSTCNT can be overwritten, since PEC, | |
231 | * INTREN, SMBSCMD are passed in xact */ | |
232 | outb_p(xact | I801_START, SMBHSTCNT); | |
233 | ||
234 | /* We will always wait for a fraction of a second! */ | |
235 | do { | |
236 | msleep(1); | |
237 | status = inb_p(SMBHSTSTS); | |
238 | } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT)); | |
239 | ||
240 | result = i801_check_post(status, timeout >= MAX_TIMEOUT); | |
241 | if (result < 0) | |
242 | return result; | |
243 | ||
244 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS); | |
245 | return 0; | |
246 | } | |
247 | ||
ca8b9e32 OR |
248 | /* wait for INTR bit as advised by Intel */ |
249 | static void i801_wait_hwpec(void) | |
250 | { | |
251 | int timeout = 0; | |
2b73809d | 252 | int status; |
ca8b9e32 OR |
253 | |
254 | do { | |
255 | msleep(1); | |
2b73809d JD |
256 | status = inb_p(SMBHSTSTS); |
257 | } while ((!(status & SMBHSTSTS_INTR)) | |
ca8b9e32 OR |
258 | && (timeout++ < MAX_TIMEOUT)); |
259 | ||
260 | if (timeout >= MAX_TIMEOUT) { | |
261 | dev_dbg(&I801_dev->dev, "PEC Timeout!\n"); | |
262 | } | |
2b73809d | 263 | outb_p(status, SMBHSTSTS); |
ca8b9e32 OR |
264 | } |
265 | ||
7edcb9ab OR |
266 | static int i801_block_transaction_by_block(union i2c_smbus_data *data, |
267 | char read_write, int hwpec) | |
268 | { | |
269 | int i, len; | |
97140342 | 270 | int status; |
7edcb9ab OR |
271 | |
272 | inb_p(SMBHSTCNT); /* reset the data buffer index */ | |
273 | ||
274 | /* Use 32-byte buffer to process this transaction */ | |
275 | if (read_write == I2C_SMBUS_WRITE) { | |
276 | len = data->block[0]; | |
277 | outb_p(len, SMBHSTDAT0); | |
278 | for (i = 0; i < len; i++) | |
279 | outb_p(data->block[i+1], SMBBLKDAT); | |
280 | } | |
281 | ||
97140342 DB |
282 | status = i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 | |
283 | I801_PEC_EN * hwpec); | |
284 | if (status) | |
285 | return status; | |
7edcb9ab OR |
286 | |
287 | if (read_write == I2C_SMBUS_READ) { | |
288 | len = inb_p(SMBHSTDAT0); | |
289 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) | |
97140342 | 290 | return -EPROTO; |
7edcb9ab OR |
291 | |
292 | data->block[0] = len; | |
293 | for (i = 0; i < len; i++) | |
294 | data->block[i + 1] = inb_p(SMBBLKDAT); | |
295 | } | |
296 | return 0; | |
297 | } | |
298 | ||
299 | static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data, | |
6342064c JD |
300 | char read_write, int command, |
301 | int hwpec) | |
1da177e4 LT |
302 | { |
303 | int i, len; | |
304 | int smbcmd; | |
2b73809d | 305 | int status; |
cf898dc5 | 306 | int result; |
1da177e4 | 307 | int timeout; |
cf898dc5 JD |
308 | |
309 | result = i801_check_pre(); | |
310 | if (result < 0) | |
311 | return result; | |
1da177e4 | 312 | |
7edcb9ab | 313 | len = data->block[0]; |
1da177e4 LT |
314 | |
315 | if (read_write == I2C_SMBUS_WRITE) { | |
1da177e4 LT |
316 | outb_p(len, SMBHSTDAT0); |
317 | outb_p(data->block[1], SMBBLKDAT); | |
1da177e4 LT |
318 | } |
319 | ||
320 | for (i = 1; i <= len; i++) { | |
6342064c JD |
321 | if (i == len && read_write == I2C_SMBUS_READ) { |
322 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) | |
323 | smbcmd = I801_I2C_BLOCK_LAST; | |
324 | else | |
325 | smbcmd = I801_BLOCK_LAST; | |
326 | } else { | |
327 | if (command == I2C_SMBUS_I2C_BLOCK_DATA | |
328 | && read_write == I2C_SMBUS_READ) | |
329 | smbcmd = I801_I2C_BLOCK_DATA; | |
330 | else | |
331 | smbcmd = I801_BLOCK_DATA; | |
332 | } | |
1da177e4 LT |
333 | outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT); |
334 | ||
1da177e4 LT |
335 | if (i == 1) |
336 | outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT); | |
337 | ||
338 | /* We will always wait for a fraction of a second! */ | |
339 | timeout = 0; | |
340 | do { | |
1da177e4 | 341 | msleep(1); |
2b73809d | 342 | status = inb_p(SMBHSTSTS); |
1da177e4 | 343 | } |
2b73809d | 344 | while ((!(status & SMBHSTSTS_BYTE_DONE)) |
ca8b9e32 | 345 | && (timeout++ < MAX_TIMEOUT)); |
1da177e4 | 346 | |
cf898dc5 JD |
347 | result = i801_check_post(status, timeout >= MAX_TIMEOUT); |
348 | if (result < 0) | |
349 | return result; | |
1da177e4 | 350 | |
6342064c JD |
351 | if (i == 1 && read_write == I2C_SMBUS_READ |
352 | && command != I2C_SMBUS_I2C_BLOCK_DATA) { | |
1da177e4 | 353 | len = inb_p(SMBHSTDAT0); |
cf898dc5 JD |
354 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { |
355 | dev_err(&I801_dev->dev, | |
356 | "Illegal SMBus block read size %d\n", | |
357 | len); | |
358 | /* Recover */ | |
359 | while (inb_p(SMBHSTSTS) & SMBHSTSTS_HOST_BUSY) | |
360 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS); | |
361 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS); | |
97140342 | 362 | return -EPROTO; |
cf898dc5 | 363 | } |
1da177e4 LT |
364 | data->block[0] = len; |
365 | } | |
366 | ||
367 | /* Retrieve/store value in SMBBLKDAT */ | |
368 | if (read_write == I2C_SMBUS_READ) | |
369 | data->block[i] = inb_p(SMBBLKDAT); | |
370 | if (read_write == I2C_SMBUS_WRITE && i+1 <= len) | |
371 | outb_p(data->block[i+1], SMBBLKDAT); | |
1da177e4 | 372 | |
cf898dc5 JD |
373 | /* signals SMBBLKDAT ready */ |
374 | outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS); | |
1da177e4 | 375 | } |
cf898dc5 JD |
376 | |
377 | return 0; | |
7edcb9ab | 378 | } |
1da177e4 | 379 | |
7edcb9ab OR |
380 | static int i801_set_block_buffer_mode(void) |
381 | { | |
382 | outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL); | |
383 | if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0) | |
97140342 | 384 | return -EIO; |
7edcb9ab OR |
385 | return 0; |
386 | } | |
387 | ||
388 | /* Block transaction function */ | |
389 | static int i801_block_transaction(union i2c_smbus_data *data, char read_write, | |
390 | int command, int hwpec) | |
391 | { | |
392 | int result = 0; | |
393 | unsigned char hostc; | |
394 | ||
395 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
396 | if (read_write == I2C_SMBUS_WRITE) { | |
397 | /* set I2C_EN bit in configuration register */ | |
398 | pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc); | |
399 | pci_write_config_byte(I801_dev, SMBHSTCFG, | |
400 | hostc | SMBHSTCFG_I2C_EN); | |
6342064c | 401 | } else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) { |
7edcb9ab | 402 | dev_err(&I801_dev->dev, |
6342064c | 403 | "I2C block read is unsupported!\n"); |
97140342 | 404 | return -EOPNOTSUPP; |
7edcb9ab OR |
405 | } |
406 | } | |
407 | ||
6342064c JD |
408 | if (read_write == I2C_SMBUS_WRITE |
409 | || command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
7edcb9ab OR |
410 | if (data->block[0] < 1) |
411 | data->block[0] = 1; | |
412 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) | |
413 | data->block[0] = I2C_SMBUS_BLOCK_MAX; | |
414 | } else { | |
6342064c | 415 | data->block[0] = 32; /* max for SMBus block reads */ |
7edcb9ab OR |
416 | } |
417 | ||
369f6f4a | 418 | if ((i801_features & FEATURE_BLOCK_BUFFER) |
6342064c JD |
419 | && !(command == I2C_SMBUS_I2C_BLOCK_DATA |
420 | && read_write == I2C_SMBUS_READ) | |
369f6f4a | 421 | && i801_set_block_buffer_mode() == 0) |
7edcb9ab OR |
422 | result = i801_block_transaction_by_block(data, read_write, |
423 | hwpec); | |
424 | else | |
425 | result = i801_block_transaction_byte_by_byte(data, read_write, | |
6342064c | 426 | command, hwpec); |
7edcb9ab OR |
427 | |
428 | if (result == 0 && hwpec) | |
ca8b9e32 | 429 | i801_wait_hwpec(); |
1da177e4 | 430 | |
6342064c JD |
431 | if (command == I2C_SMBUS_I2C_BLOCK_DATA |
432 | && read_write == I2C_SMBUS_WRITE) { | |
1da177e4 LT |
433 | /* restore saved configuration register value */ |
434 | pci_write_config_byte(I801_dev, SMBHSTCFG, hostc); | |
435 | } | |
436 | return result; | |
437 | } | |
438 | ||
97140342 | 439 | /* Return negative errno on error. */ |
1da177e4 LT |
440 | static s32 i801_access(struct i2c_adapter * adap, u16 addr, |
441 | unsigned short flags, char read_write, u8 command, | |
442 | int size, union i2c_smbus_data * data) | |
443 | { | |
e8aac4a9 | 444 | int hwpec; |
1da177e4 LT |
445 | int block = 0; |
446 | int ret, xact = 0; | |
447 | ||
369f6f4a | 448 | hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) |
e8aac4a9 JD |
449 | && size != I2C_SMBUS_QUICK |
450 | && size != I2C_SMBUS_I2C_BLOCK_DATA; | |
1da177e4 LT |
451 | |
452 | switch (size) { | |
453 | case I2C_SMBUS_QUICK: | |
454 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
455 | SMBHSTADD); | |
456 | xact = I801_QUICK; | |
457 | break; | |
458 | case I2C_SMBUS_BYTE: | |
459 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
460 | SMBHSTADD); | |
461 | if (read_write == I2C_SMBUS_WRITE) | |
462 | outb_p(command, SMBHSTCMD); | |
463 | xact = I801_BYTE; | |
464 | break; | |
465 | case I2C_SMBUS_BYTE_DATA: | |
466 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
467 | SMBHSTADD); | |
468 | outb_p(command, SMBHSTCMD); | |
469 | if (read_write == I2C_SMBUS_WRITE) | |
470 | outb_p(data->byte, SMBHSTDAT0); | |
471 | xact = I801_BYTE_DATA; | |
472 | break; | |
473 | case I2C_SMBUS_WORD_DATA: | |
474 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
475 | SMBHSTADD); | |
476 | outb_p(command, SMBHSTCMD); | |
477 | if (read_write == I2C_SMBUS_WRITE) { | |
478 | outb_p(data->word & 0xff, SMBHSTDAT0); | |
479 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); | |
480 | } | |
481 | xact = I801_WORD_DATA; | |
482 | break; | |
483 | case I2C_SMBUS_BLOCK_DATA: | |
1da177e4 LT |
484 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
485 | SMBHSTADD); | |
486 | outb_p(command, SMBHSTCMD); | |
487 | block = 1; | |
488 | break; | |
6342064c JD |
489 | case I2C_SMBUS_I2C_BLOCK_DATA: |
490 | /* NB: page 240 of ICH5 datasheet shows that the R/#W | |
491 | * bit should be cleared here, even when reading */ | |
492 | outb_p((addr & 0x7f) << 1, SMBHSTADD); | |
493 | if (read_write == I2C_SMBUS_READ) { | |
494 | /* NB: page 240 of ICH5 datasheet also shows | |
495 | * that DATA1 is the cmd field when reading */ | |
496 | outb_p(command, SMBHSTDAT1); | |
497 | } else | |
498 | outb_p(command, SMBHSTCMD); | |
499 | block = 1; | |
500 | break; | |
1da177e4 LT |
501 | default: |
502 | dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size); | |
97140342 | 503 | return -EOPNOTSUPP; |
1da177e4 LT |
504 | } |
505 | ||
ca8b9e32 OR |
506 | if (hwpec) /* enable/disable hardware PEC */ |
507 | outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL); | |
508 | else | |
509 | outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL); | |
e8aac4a9 | 510 | |
1da177e4 | 511 | if(block) |
585b3160 | 512 | ret = i801_block_transaction(data, read_write, size, hwpec); |
7edcb9ab OR |
513 | else |
514 | ret = i801_transaction(xact | ENABLE_INT9); | |
1da177e4 | 515 | |
c79cfbac | 516 | /* Some BIOSes don't like it when PEC is enabled at reboot or resume |
7edcb9ab OR |
517 | time, so we forcibly disable it after every transaction. Turn off |
518 | E32B for the same reason. */ | |
a0921b6c | 519 | if (hwpec || block) |
7edcb9ab OR |
520 | outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), |
521 | SMBAUXCTL); | |
c79cfbac | 522 | |
1da177e4 LT |
523 | if(block) |
524 | return ret; | |
525 | if(ret) | |
97140342 | 526 | return ret; |
1da177e4 LT |
527 | if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) |
528 | return 0; | |
529 | ||
530 | switch (xact & 0x7f) { | |
531 | case I801_BYTE: /* Result put in SMBHSTDAT0 */ | |
532 | case I801_BYTE_DATA: | |
533 | data->byte = inb_p(SMBHSTDAT0); | |
534 | break; | |
535 | case I801_WORD_DATA: | |
536 | data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); | |
537 | break; | |
538 | } | |
539 | return 0; | |
540 | } | |
541 | ||
542 | ||
543 | static u32 i801_func(struct i2c_adapter *adapter) | |
544 | { | |
545 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | | |
369f6f4a JD |
546 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | |
547 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | | |
6342064c JD |
548 | ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | |
549 | ((i801_features & FEATURE_I2C_BLOCK_READ) ? | |
550 | I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); | |
1da177e4 LT |
551 | } |
552 | ||
8f9082c5 | 553 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
554 | .smbus_xfer = i801_access, |
555 | .functionality = i801_func, | |
556 | }; | |
557 | ||
558 | static struct i2c_adapter i801_adapter = { | |
559 | .owner = THIS_MODULE, | |
3401b2ff | 560 | .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, |
1da177e4 | 561 | .algo = &smbus_algorithm, |
1da177e4 LT |
562 | }; |
563 | ||
564 | static struct pci_device_id i801_ids[] = { | |
565 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, | |
566 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, | |
567 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, | |
568 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, | |
569 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, | |
570 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, | |
571 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, | |
572 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, | |
573 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, | |
b0a70b57 | 574 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, |
8254fc4a | 575 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, |
adbc2a10 | 576 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, |
e07bc679 | 577 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TOLAPAI_1) }, |
d28dc711 GJ |
578 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, |
579 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, | |
c429a247 | 580 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PCH_SMBUS) }, |
1da177e4 LT |
581 | { 0, } |
582 | }; | |
583 | ||
584 | MODULE_DEVICE_TABLE (pci, i801_ids); | |
585 | ||
1561bfe5 JD |
586 | #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE |
587 | static unsigned char apanel_addr; | |
588 | ||
589 | /* Scan the system ROM for the signature "FJKEYINF" */ | |
590 | static __init const void __iomem *bios_signature(const void __iomem *bios) | |
591 | { | |
592 | ssize_t offset; | |
593 | const unsigned char signature[] = "FJKEYINF"; | |
594 | ||
595 | for (offset = 0; offset < 0x10000; offset += 0x10) { | |
596 | if (check_signature(bios + offset, signature, | |
597 | sizeof(signature)-1)) | |
598 | return bios + offset; | |
599 | } | |
600 | return NULL; | |
601 | } | |
602 | ||
603 | static void __init input_apanel_init(void) | |
604 | { | |
605 | void __iomem *bios; | |
606 | const void __iomem *p; | |
607 | ||
608 | bios = ioremap(0xF0000, 0x10000); /* Can't fail */ | |
609 | p = bios_signature(bios); | |
610 | if (p) { | |
611 | /* just use the first address */ | |
612 | apanel_addr = readb(p + 8 + 3) >> 1; | |
613 | } | |
614 | iounmap(bios); | |
615 | } | |
616 | #else | |
617 | static void __init input_apanel_init(void) {} | |
618 | #endif | |
619 | ||
fa5bfab7 HG |
620 | #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE |
621 | struct dmi_onboard_device_info { | |
622 | const char *name; | |
623 | u8 type; | |
624 | unsigned short i2c_addr; | |
625 | const char *i2c_type; | |
626 | }; | |
627 | ||
628 | static struct dmi_onboard_device_info __devinitdata dmi_devices[] = { | |
629 | { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, | |
630 | { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, | |
631 | { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, | |
632 | }; | |
633 | ||
634 | static void __devinit dmi_check_onboard_device(u8 type, const char *name, | |
635 | struct i2c_adapter *adap) | |
636 | { | |
637 | int i; | |
638 | struct i2c_board_info info; | |
639 | ||
640 | for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { | |
641 | /* & ~0x80, ignore enabled/disabled bit */ | |
642 | if ((type & ~0x80) != dmi_devices[i].type) | |
643 | continue; | |
644 | if (strcmp(name, dmi_devices[i].name)) | |
645 | continue; | |
646 | ||
647 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
648 | info.addr = dmi_devices[i].i2c_addr; | |
649 | strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); | |
650 | i2c_new_device(adap, &info); | |
651 | break; | |
652 | } | |
653 | } | |
654 | ||
655 | /* We use our own function to check for onboard devices instead of | |
656 | dmi_find_device() as some buggy BIOS's have the devices we are interested | |
657 | in marked as disabled */ | |
658 | static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm, | |
659 | void *adap) | |
660 | { | |
661 | int i, count; | |
662 | ||
663 | if (dm->type != 10) | |
664 | return; | |
665 | ||
666 | count = (dm->length - sizeof(struct dmi_header)) / 2; | |
667 | for (i = 0; i < count; i++) { | |
668 | const u8 *d = (char *)(dm + 1) + (i * 2); | |
669 | const char *name = ((char *) dm) + dm->length; | |
670 | u8 type = d[0]; | |
671 | u8 s = d[1]; | |
672 | ||
673 | if (!s) | |
674 | continue; | |
675 | s--; | |
676 | while (s > 0 && name[0]) { | |
677 | name += strlen(name) + 1; | |
678 | s--; | |
679 | } | |
680 | if (name[0] == 0) /* Bogus string reference */ | |
681 | continue; | |
682 | ||
683 | dmi_check_onboard_device(type, name, adap); | |
684 | } | |
685 | } | |
686 | #endif | |
687 | ||
1da177e4 LT |
688 | static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id) |
689 | { | |
02dd7ae2 | 690 | unsigned char temp; |
455f3323 | 691 | int err; |
fa5bfab7 HG |
692 | #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE |
693 | const char *vendor; | |
694 | #endif | |
1da177e4 | 695 | |
02dd7ae2 | 696 | I801_dev = dev; |
369f6f4a | 697 | i801_features = 0; |
250d1bd3 | 698 | switch (dev->device) { |
250d1bd3 JD |
699 | case PCI_DEVICE_ID_INTEL_82801EB_3: |
700 | case PCI_DEVICE_ID_INTEL_ESB_4: | |
701 | case PCI_DEVICE_ID_INTEL_ICH6_16: | |
702 | case PCI_DEVICE_ID_INTEL_ICH7_17: | |
703 | case PCI_DEVICE_ID_INTEL_ESB2_17: | |
704 | case PCI_DEVICE_ID_INTEL_ICH8_5: | |
705 | case PCI_DEVICE_ID_INTEL_ICH9_6: | |
d28dc711 GJ |
706 | case PCI_DEVICE_ID_INTEL_TOLAPAI_1: |
707 | case PCI_DEVICE_ID_INTEL_ICH10_4: | |
708 | case PCI_DEVICE_ID_INTEL_ICH10_5: | |
c429a247 | 709 | case PCI_DEVICE_ID_INTEL_PCH_SMBUS: |
6342064c JD |
710 | i801_features |= FEATURE_I2C_BLOCK_READ; |
711 | /* fall through */ | |
712 | case PCI_DEVICE_ID_INTEL_82801DB_3: | |
369f6f4a JD |
713 | i801_features |= FEATURE_SMBUS_PEC; |
714 | i801_features |= FEATURE_BLOCK_BUFFER; | |
250d1bd3 | 715 | break; |
250d1bd3 | 716 | } |
02dd7ae2 JD |
717 | |
718 | err = pci_enable_device(dev); | |
719 | if (err) { | |
720 | dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", | |
721 | err); | |
722 | goto exit; | |
723 | } | |
724 | ||
725 | /* Determine the address of the SMBus area */ | |
726 | i801_smba = pci_resource_start(dev, SMBBAR); | |
727 | if (!i801_smba) { | |
728 | dev_err(&dev->dev, "SMBus base address uninitialized, " | |
729 | "upgrade BIOS\n"); | |
730 | err = -ENODEV; | |
d6fcb3b9 | 731 | goto exit; |
02dd7ae2 JD |
732 | } |
733 | ||
54fb4a05 JD |
734 | err = acpi_check_resource_conflict(&dev->resource[SMBBAR]); |
735 | if (err) | |
736 | goto exit; | |
737 | ||
02dd7ae2 JD |
738 | err = pci_request_region(dev, SMBBAR, i801_driver.name); |
739 | if (err) { | |
740 | dev_err(&dev->dev, "Failed to request SMBus region " | |
598736c5 AM |
741 | "0x%lx-0x%Lx\n", i801_smba, |
742 | (unsigned long long)pci_resource_end(dev, SMBBAR)); | |
d6fcb3b9 | 743 | goto exit; |
02dd7ae2 JD |
744 | } |
745 | ||
746 | pci_read_config_byte(I801_dev, SMBHSTCFG, &temp); | |
a5aaea37 | 747 | i801_original_hstcfg = temp; |
02dd7ae2 JD |
748 | temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ |
749 | if (!(temp & SMBHSTCFG_HST_EN)) { | |
750 | dev_info(&dev->dev, "Enabling SMBus device\n"); | |
751 | temp |= SMBHSTCFG_HST_EN; | |
752 | } | |
753 | pci_write_config_byte(I801_dev, SMBHSTCFG, temp); | |
754 | ||
755 | if (temp & SMBHSTCFG_SMB_SMI_EN) | |
756 | dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); | |
757 | else | |
758 | dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n"); | |
1da177e4 | 759 | |
a0921b6c JD |
760 | /* Clear special mode bits */ |
761 | if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) | |
762 | outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), | |
763 | SMBAUXCTL); | |
764 | ||
405ae7d3 | 765 | /* set up the sysfs linkage to our parent device */ |
1da177e4 LT |
766 | i801_adapter.dev.parent = &dev->dev; |
767 | ||
2096b956 | 768 | snprintf(i801_adapter.name, sizeof(i801_adapter.name), |
6dcc19df | 769 | "SMBus I801 adapter at %04lx", i801_smba); |
02dd7ae2 JD |
770 | err = i2c_add_adapter(&i801_adapter); |
771 | if (err) { | |
772 | dev_err(&dev->dev, "Failed to add SMBus adapter\n"); | |
d6fcb3b9 | 773 | goto exit_release; |
02dd7ae2 | 774 | } |
1561bfe5 JD |
775 | |
776 | /* Register optional slaves */ | |
777 | #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE | |
778 | if (apanel_addr) { | |
779 | struct i2c_board_info info; | |
780 | ||
781 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
782 | info.addr = apanel_addr; | |
783 | strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); | |
784 | i2c_new_device(&i801_adapter, &info); | |
785 | } | |
786 | #endif | |
fa5bfab7 HG |
787 | #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE |
788 | vendor = dmi_get_system_info(DMI_BOARD_VENDOR); | |
789 | if (vendor && !strcmp(vendor, "FUJITSU SIEMENS")) | |
790 | dmi_walk(dmi_check_onboard_devices, &i801_adapter); | |
791 | #endif | |
1561bfe5 | 792 | |
d6fcb3b9 | 793 | return 0; |
02dd7ae2 | 794 | |
d6fcb3b9 DR |
795 | exit_release: |
796 | pci_release_region(dev, SMBBAR); | |
02dd7ae2 JD |
797 | exit: |
798 | return err; | |
1da177e4 LT |
799 | } |
800 | ||
801 | static void __devexit i801_remove(struct pci_dev *dev) | |
802 | { | |
803 | i2c_del_adapter(&i801_adapter); | |
a5aaea37 | 804 | pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg); |
6dcc19df | 805 | pci_release_region(dev, SMBBAR); |
d6fcb3b9 DR |
806 | /* |
807 | * do not call pci_disable_device(dev) since it can cause hard hangs on | |
808 | * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) | |
809 | */ | |
1da177e4 LT |
810 | } |
811 | ||
a5aaea37 JD |
812 | #ifdef CONFIG_PM |
813 | static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) | |
814 | { | |
815 | pci_save_state(dev); | |
816 | pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg); | |
817 | pci_set_power_state(dev, pci_choose_state(dev, mesg)); | |
818 | return 0; | |
819 | } | |
820 | ||
821 | static int i801_resume(struct pci_dev *dev) | |
822 | { | |
823 | pci_set_power_state(dev, PCI_D0); | |
824 | pci_restore_state(dev); | |
825 | return pci_enable_device(dev); | |
826 | } | |
827 | #else | |
828 | #define i801_suspend NULL | |
829 | #define i801_resume NULL | |
830 | #endif | |
831 | ||
1da177e4 LT |
832 | static struct pci_driver i801_driver = { |
833 | .name = "i801_smbus", | |
834 | .id_table = i801_ids, | |
835 | .probe = i801_probe, | |
836 | .remove = __devexit_p(i801_remove), | |
a5aaea37 JD |
837 | .suspend = i801_suspend, |
838 | .resume = i801_resume, | |
1da177e4 LT |
839 | }; |
840 | ||
841 | static int __init i2c_i801_init(void) | |
842 | { | |
1561bfe5 | 843 | input_apanel_init(); |
1da177e4 LT |
844 | return pci_register_driver(&i801_driver); |
845 | } | |
846 | ||
847 | static void __exit i2c_i801_exit(void) | |
848 | { | |
849 | pci_unregister_driver(&i801_driver); | |
850 | } | |
851 | ||
6342064c JD |
852 | MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, " |
853 | "Jean Delvare <khali@linux-fr.org>"); | |
1da177e4 LT |
854 | MODULE_DESCRIPTION("I801 SMBus driver"); |
855 | MODULE_LICENSE("GPL"); | |
856 | ||
857 | module_init(i2c_i801_init); | |
858 | module_exit(i2c_i801_exit); |