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aa11e38c DA |
1 | /* |
2 | * Copyright (C) 2002 Motorola GSG-China | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version 2 | |
7 | * of the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, | |
17 | * USA. | |
18 | * | |
19 | * Author: | |
20 | * Darius Augulis, Teltonika Inc. | |
21 | * | |
22 | * Desc.: | |
23 | * Implementation of I2C Adapter/Algorithm Driver | |
24 | * for I2C Bus integrated in Freescale i.MX/MXC processors | |
25 | * | |
26 | * Derived from Motorola GSG China I2C example driver | |
27 | * | |
28 | * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de | |
29 | * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de | |
30 | * Copyright (C) 2007 RightHand Technologies, Inc. | |
31 | * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> | |
32 | * | |
d533f049 JL |
33 | * Copyright 2013 Freescale Semiconductor, Inc. |
34 | * | |
aa11e38c DA |
35 | */ |
36 | ||
37 | /** Includes ******************************************************************* | |
38 | *******************************************************************************/ | |
39 | ||
40 | #include <linux/init.h> | |
41 | #include <linux/kernel.h> | |
42 | #include <linux/module.h> | |
43 | #include <linux/errno.h> | |
44 | #include <linux/err.h> | |
45 | #include <linux/interrupt.h> | |
46 | #include <linux/delay.h> | |
47 | #include <linux/i2c.h> | |
48 | #include <linux/io.h> | |
49 | #include <linux/sched.h> | |
50 | #include <linux/platform_device.h> | |
51 | #include <linux/clk.h> | |
5a0e3ad6 | 52 | #include <linux/slab.h> |
dfcd04b1 SG |
53 | #include <linux/of.h> |
54 | #include <linux/of_device.h> | |
55 | #include <linux/of_i2c.h> | |
82906b13 | 56 | #include <linux/platform_data/i2c-imx.h> |
aa11e38c DA |
57 | |
58 | /** Defines ******************************************************************** | |
59 | *******************************************************************************/ | |
60 | ||
61 | /* This will be the driver name the kernel reports */ | |
62 | #define DRIVER_NAME "imx-i2c" | |
63 | ||
64 | /* Default value */ | |
65 | #define IMX_I2C_BIT_RATE 100000 /* 100kHz */ | |
66 | ||
8cc7331f JL |
67 | /* IMX I2C registers: |
68 | * the I2C register offset is different between SoCs, | |
69 | * to provid support for all these chips, split the | |
70 | * register offset into a fixed base address and a | |
71 | * variable shift value, then the full register offset | |
72 | * will be calculated by | |
73 | * reg_off = ( reg_base_addr << reg_shift) | |
74 | */ | |
aa11e38c | 75 | #define IMX_I2C_IADR 0x00 /* i2c slave address */ |
8cc7331f JL |
76 | #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ |
77 | #define IMX_I2C_I2CR 0x02 /* i2c control */ | |
78 | #define IMX_I2C_I2SR 0x03 /* i2c status */ | |
79 | #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ | |
80 | ||
81 | #define IMX_I2C_REGSHIFT 2 | |
aa11e38c DA |
82 | |
83 | /* Bits of IMX I2C registers */ | |
84 | #define I2SR_RXAK 0x01 | |
85 | #define I2SR_IIF 0x02 | |
86 | #define I2SR_SRW 0x04 | |
87 | #define I2SR_IAL 0x10 | |
88 | #define I2SR_IBB 0x20 | |
89 | #define I2SR_IAAS 0x40 | |
90 | #define I2SR_ICF 0x80 | |
91 | #define I2CR_RSTA 0x04 | |
92 | #define I2CR_TXAK 0x08 | |
93 | #define I2CR_MTX 0x10 | |
94 | #define I2CR_MSTA 0x20 | |
95 | #define I2CR_IIEN 0x40 | |
96 | #define I2CR_IEN 0x80 | |
97 | ||
171408c2 JL |
98 | /* register bits different operating codes definition: |
99 | * 1) I2SR: Interrupt flags clear operation differ between SoCs: | |
100 | * - write zero to clear(w0c) INT flag on i.MX, | |
101 | * - but write one to clear(w1c) INT flag on Vybrid. | |
102 | * 2) I2CR: I2C module enable operation also differ between SoCs: | |
103 | * - set I2CR_IEN bit enable the module on i.MX, | |
104 | * - but clear I2CR_IEN bit enable the module on Vybrid. | |
105 | */ | |
106 | #define I2SR_CLR_OPCODE_W0C 0x0 | |
107 | #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) | |
108 | #define I2CR_IEN_OPCODE_0 0x0 | |
109 | #define I2CR_IEN_OPCODE_1 I2CR_IEN | |
110 | ||
111 | #define IMX_I2SR_CLR_OPCODE I2SR_CLR_OPCODE_W0C | |
112 | #define IMX_I2CR_IEN_OPCODE I2CR_IEN_OPCODE_1 | |
113 | ||
aa11e38c DA |
114 | /** Variables ****************************************************************** |
115 | *******************************************************************************/ | |
116 | ||
aa11e38c DA |
117 | /* |
118 | * sorted list of clock divider, register value pairs | |
119 | * taken from table 26-5, p.26-9, Freescale i.MX | |
120 | * Integrated Portable System Processor Reference Manual | |
121 | * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 | |
122 | * | |
123 | * Duplicated divider values removed from list | |
124 | */ | |
d533f049 JL |
125 | struct imx_i2c_clk_pair { |
126 | u16 div; | |
127 | u16 val; | |
128 | }; | |
aa11e38c | 129 | |
d533f049 | 130 | static struct imx_i2c_clk_pair __initdata i2c_clk_div[] = { |
aa11e38c DA |
131 | { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, |
132 | { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, | |
133 | { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, | |
134 | { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, | |
135 | { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, | |
136 | { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, | |
137 | { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, | |
138 | { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, | |
139 | { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, | |
140 | { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, | |
141 | { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, | |
142 | { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, | |
143 | { 3072, 0x1E }, { 3840, 0x1F } | |
144 | }; | |
145 | ||
5bdfba29 SG |
146 | enum imx_i2c_type { |
147 | IMX1_I2C, | |
148 | IMX21_I2C, | |
149 | }; | |
150 | ||
aa11e38c DA |
151 | struct imx_i2c_struct { |
152 | struct i2c_adapter adapter; | |
aa11e38c DA |
153 | struct clk *clk; |
154 | void __iomem *base; | |
aa11e38c DA |
155 | wait_queue_head_t queue; |
156 | unsigned long i2csr; | |
65de394d | 157 | unsigned int disable_delay; |
43309f3b | 158 | int stopped; |
db3a3d4e | 159 | unsigned int ifdr; /* IMX_I2C_IFDR */ |
5bdfba29 SG |
160 | enum imx_i2c_type devtype; |
161 | }; | |
162 | ||
163 | static struct platform_device_id imx_i2c_devtype[] = { | |
164 | { | |
165 | .name = "imx1-i2c", | |
166 | .driver_data = IMX1_I2C, | |
167 | }, { | |
168 | .name = "imx21-i2c", | |
169 | .driver_data = IMX21_I2C, | |
170 | }, { | |
171 | /* sentinel */ | |
172 | } | |
aa11e38c | 173 | }; |
5bdfba29 | 174 | MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); |
aa11e38c | 175 | |
dfcd04b1 | 176 | static const struct of_device_id i2c_imx_dt_ids[] = { |
5bdfba29 SG |
177 | { .compatible = "fsl,imx1-i2c", .data = &imx_i2c_devtype[IMX1_I2C], }, |
178 | { .compatible = "fsl,imx21-i2c", .data = &imx_i2c_devtype[IMX21_I2C], }, | |
dfcd04b1 SG |
179 | { /* sentinel */ } |
180 | }; | |
2f641a8b | 181 | MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); |
dfcd04b1 | 182 | |
5bdfba29 SG |
183 | static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) |
184 | { | |
185 | return i2c_imx->devtype == IMX1_I2C; | |
186 | } | |
187 | ||
1d5ef2a8 JL |
188 | static inline void imx_i2c_write_reg(unsigned int val, |
189 | struct imx_i2c_struct *i2c_imx, unsigned int reg) | |
190 | { | |
8cc7331f | 191 | writeb(val, i2c_imx->base + (reg << IMX_I2C_REGSHIFT)); |
1d5ef2a8 JL |
192 | } |
193 | ||
194 | static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, | |
195 | unsigned int reg) | |
196 | { | |
8cc7331f | 197 | return readb(i2c_imx->base + (reg << IMX_I2C_REGSHIFT)); |
1d5ef2a8 JL |
198 | } |
199 | ||
aa11e38c DA |
200 | /** Functions for IMX I2C adapter driver *************************************** |
201 | *******************************************************************************/ | |
202 | ||
43309f3b | 203 | static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy) |
aa11e38c DA |
204 | { |
205 | unsigned long orig_jiffies = jiffies; | |
43309f3b | 206 | unsigned int temp; |
aa11e38c DA |
207 | |
208 | dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); | |
209 | ||
43309f3b | 210 | while (1) { |
1d5ef2a8 | 211 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); |
43309f3b RZ |
212 | if (for_busy && (temp & I2SR_IBB)) |
213 | break; | |
214 | if (!for_busy && !(temp & I2SR_IBB)) | |
215 | break; | |
da9c99fc | 216 | if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { |
aa11e38c DA |
217 | dev_dbg(&i2c_imx->adapter.dev, |
218 | "<%s> I2C bus is busy\n", __func__); | |
da9c99fc | 219 | return -ETIMEDOUT; |
aa11e38c DA |
220 | } |
221 | schedule(); | |
222 | } | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
227 | static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx) | |
228 | { | |
e39428d5 | 229 | wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); |
aa11e38c | 230 | |
e39428d5 | 231 | if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { |
aa11e38c DA |
232 | dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); |
233 | return -ETIMEDOUT; | |
234 | } | |
235 | dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); | |
236 | i2c_imx->i2csr = 0; | |
237 | return 0; | |
238 | } | |
239 | ||
240 | static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) | |
241 | { | |
1d5ef2a8 | 242 | if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { |
aa11e38c DA |
243 | dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); |
244 | return -EIO; /* No ACK */ | |
245 | } | |
246 | ||
247 | dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); | |
248 | return 0; | |
249 | } | |
250 | ||
43309f3b | 251 | static int i2c_imx_start(struct imx_i2c_struct *i2c_imx) |
aa11e38c DA |
252 | { |
253 | unsigned int temp = 0; | |
43309f3b | 254 | int result; |
aa11e38c DA |
255 | |
256 | dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); | |
257 | ||
83914337 | 258 | clk_prepare_enable(i2c_imx->clk); |
1d5ef2a8 | 259 | imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); |
aa11e38c | 260 | /* Enable I2C controller */ |
171408c2 JL |
261 | imx_i2c_write_reg(IMX_I2SR_CLR_OPCODE, i2c_imx, IMX_I2C_I2SR); |
262 | imx_i2c_write_reg(IMX_I2CR_IEN_OPCODE, i2c_imx, IMX_I2C_I2CR); | |
43309f3b RZ |
263 | |
264 | /* Wait controller to be stable */ | |
265 | udelay(50); | |
266 | ||
aa11e38c | 267 | /* Start I2C transaction */ |
1d5ef2a8 | 268 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
aa11e38c | 269 | temp |= I2CR_MSTA; |
1d5ef2a8 | 270 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
43309f3b RZ |
271 | result = i2c_imx_bus_busy(i2c_imx, 1); |
272 | if (result) | |
273 | return result; | |
274 | i2c_imx->stopped = 0; | |
275 | ||
aa11e38c | 276 | temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; |
1d5ef2a8 | 277 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
43309f3b | 278 | return result; |
aa11e38c DA |
279 | } |
280 | ||
281 | static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) | |
282 | { | |
283 | unsigned int temp = 0; | |
284 | ||
43309f3b RZ |
285 | if (!i2c_imx->stopped) { |
286 | /* Stop I2C transaction */ | |
287 | dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); | |
1d5ef2a8 | 288 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
43309f3b | 289 | temp &= ~(I2CR_MSTA | I2CR_MTX); |
1d5ef2a8 | 290 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
43309f3b | 291 | } |
5bdfba29 | 292 | if (is_imx1_i2c(i2c_imx)) { |
a4094a76 RZ |
293 | /* |
294 | * This delay caused by an i.MXL hardware bug. | |
295 | * If no (or too short) delay, no "STOP" bit will be generated. | |
296 | */ | |
297 | udelay(i2c_imx->disable_delay); | |
298 | } | |
43309f3b | 299 | |
a1ee06b7 | 300 | if (!i2c_imx->stopped) { |
43309f3b | 301 | i2c_imx_bus_busy(i2c_imx, 0); |
a1ee06b7 VL |
302 | i2c_imx->stopped = 1; |
303 | } | |
43309f3b | 304 | |
aa11e38c | 305 | /* Disable I2C controller */ |
171408c2 | 306 | imx_i2c_write_reg(IMX_I2CR_IEN_OPCODE ^ I2CR_IEN, i2c_imx, IMX_I2C_I2CR); |
83914337 | 307 | clk_disable_unprepare(i2c_imx->clk); |
aa11e38c DA |
308 | } |
309 | ||
310 | static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, | |
311 | unsigned int rate) | |
312 | { | |
313 | unsigned int i2c_clk_rate; | |
314 | unsigned int div; | |
315 | int i; | |
316 | ||
317 | /* Divider value calculation */ | |
318 | i2c_clk_rate = clk_get_rate(i2c_imx->clk); | |
319 | div = (i2c_clk_rate + rate - 1) / rate; | |
d533f049 | 320 | if (div < i2c_clk_div[0].div) |
aa11e38c | 321 | i = 0; |
d533f049 | 322 | else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1].div) |
aa11e38c DA |
323 | i = ARRAY_SIZE(i2c_clk_div) - 1; |
324 | else | |
d533f049 | 325 | for (i = 0; i2c_clk_div[i].div < div; i++); |
aa11e38c | 326 | |
db3a3d4e | 327 | /* Store divider value */ |
d533f049 | 328 | i2c_imx->ifdr = i2c_clk_div[i].val; |
aa11e38c DA |
329 | |
330 | /* | |
331 | * There dummy delay is calculated. | |
332 | * It should be about one I2C clock period long. | |
333 | * This delay is used in I2C bus disable function | |
334 | * to fix chip hardware bug. | |
335 | */ | |
d533f049 | 336 | i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div |
aa11e38c DA |
337 | + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2); |
338 | ||
339 | /* dev_dbg() can't be used, because adapter is not yet registered */ | |
340 | #ifdef CONFIG_I2C_DEBUG_BUS | |
002f002d | 341 | dev_dbg(&i2c_imx->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n", |
aa11e38c | 342 | __func__, i2c_clk_rate, div); |
002f002d | 343 | dev_dbg(&i2c_imx->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n", |
d533f049 | 344 | __func__, i2c_clk_div[i].val, i2c_clk_div[i].div); |
aa11e38c DA |
345 | #endif |
346 | } | |
347 | ||
348 | static irqreturn_t i2c_imx_isr(int irq, void *dev_id) | |
349 | { | |
350 | struct imx_i2c_struct *i2c_imx = dev_id; | |
351 | unsigned int temp; | |
352 | ||
1d5ef2a8 | 353 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); |
aa11e38c DA |
354 | if (temp & I2SR_IIF) { |
355 | /* save status register */ | |
356 | i2c_imx->i2csr = temp; | |
357 | temp &= ~I2SR_IIF; | |
171408c2 | 358 | temp |= (IMX_I2SR_CLR_OPCODE & I2SR_IIF); |
1d5ef2a8 | 359 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); |
e39428d5 | 360 | wake_up(&i2c_imx->queue); |
aa11e38c DA |
361 | return IRQ_HANDLED; |
362 | } | |
363 | ||
364 | return IRQ_NONE; | |
365 | } | |
366 | ||
367 | static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) | |
368 | { | |
369 | int i, result; | |
370 | ||
371 | dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", | |
372 | __func__, msgs->addr << 1); | |
373 | ||
374 | /* write slave address */ | |
1d5ef2a8 | 375 | imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR); |
aa11e38c DA |
376 | result = i2c_imx_trx_complete(i2c_imx); |
377 | if (result) | |
378 | return result; | |
379 | result = i2c_imx_acked(i2c_imx); | |
380 | if (result) | |
381 | return result; | |
382 | dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); | |
383 | ||
384 | /* write data */ | |
385 | for (i = 0; i < msgs->len; i++) { | |
386 | dev_dbg(&i2c_imx->adapter.dev, | |
387 | "<%s> write byte: B%d=0x%X\n", | |
388 | __func__, i, msgs->buf[i]); | |
1d5ef2a8 | 389 | imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); |
aa11e38c DA |
390 | result = i2c_imx_trx_complete(i2c_imx); |
391 | if (result) | |
392 | return result; | |
393 | result = i2c_imx_acked(i2c_imx); | |
394 | if (result) | |
395 | return result; | |
396 | } | |
397 | return 0; | |
398 | } | |
399 | ||
400 | static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) | |
401 | { | |
402 | int i, result; | |
403 | unsigned int temp; | |
404 | ||
405 | dev_dbg(&i2c_imx->adapter.dev, | |
406 | "<%s> write slave address: addr=0x%x\n", | |
407 | __func__, (msgs->addr << 1) | 0x01); | |
408 | ||
409 | /* write slave address */ | |
1d5ef2a8 | 410 | imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR); |
aa11e38c DA |
411 | result = i2c_imx_trx_complete(i2c_imx); |
412 | if (result) | |
413 | return result; | |
414 | result = i2c_imx_acked(i2c_imx); | |
415 | if (result) | |
416 | return result; | |
417 | ||
418 | dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); | |
419 | ||
420 | /* setup bus to read data */ | |
1d5ef2a8 | 421 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
aa11e38c DA |
422 | temp &= ~I2CR_MTX; |
423 | if (msgs->len - 1) | |
424 | temp &= ~I2CR_TXAK; | |
1d5ef2a8 JL |
425 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
426 | imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ | |
aa11e38c DA |
427 | |
428 | dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); | |
429 | ||
430 | /* read data */ | |
431 | for (i = 0; i < msgs->len; i++) { | |
432 | result = i2c_imx_trx_complete(i2c_imx); | |
433 | if (result) | |
434 | return result; | |
435 | if (i == (msgs->len - 1)) { | |
43309f3b RZ |
436 | /* It must generate STOP before read I2DR to prevent |
437 | controller from generating another clock cycle */ | |
aa11e38c DA |
438 | dev_dbg(&i2c_imx->adapter.dev, |
439 | "<%s> clear MSTA\n", __func__); | |
1d5ef2a8 | 440 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
43309f3b | 441 | temp &= ~(I2CR_MSTA | I2CR_MTX); |
1d5ef2a8 | 442 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
43309f3b RZ |
443 | i2c_imx_bus_busy(i2c_imx, 0); |
444 | i2c_imx->stopped = 1; | |
aa11e38c DA |
445 | } else if (i == (msgs->len - 2)) { |
446 | dev_dbg(&i2c_imx->adapter.dev, | |
447 | "<%s> set TXAK\n", __func__); | |
1d5ef2a8 | 448 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
aa11e38c | 449 | temp |= I2CR_TXAK; |
1d5ef2a8 | 450 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
aa11e38c | 451 | } |
1d5ef2a8 | 452 | msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); |
aa11e38c DA |
453 | dev_dbg(&i2c_imx->adapter.dev, |
454 | "<%s> read byte: B%d=0x%X\n", | |
455 | __func__, i, msgs->buf[i]); | |
456 | } | |
457 | return 0; | |
458 | } | |
459 | ||
460 | static int i2c_imx_xfer(struct i2c_adapter *adapter, | |
461 | struct i2c_msg *msgs, int num) | |
462 | { | |
463 | unsigned int i, temp; | |
464 | int result; | |
465 | struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); | |
466 | ||
467 | dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); | |
468 | ||
43309f3b RZ |
469 | /* Start I2C transfer */ |
470 | result = i2c_imx_start(i2c_imx); | |
aa11e38c DA |
471 | if (result) |
472 | goto fail0; | |
473 | ||
aa11e38c DA |
474 | /* read/write data */ |
475 | for (i = 0; i < num; i++) { | |
476 | if (i) { | |
477 | dev_dbg(&i2c_imx->adapter.dev, | |
478 | "<%s> repeated start\n", __func__); | |
1d5ef2a8 | 479 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
aa11e38c | 480 | temp |= I2CR_RSTA; |
1d5ef2a8 | 481 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
43309f3b RZ |
482 | result = i2c_imx_bus_busy(i2c_imx, 1); |
483 | if (result) | |
484 | goto fail0; | |
aa11e38c DA |
485 | } |
486 | dev_dbg(&i2c_imx->adapter.dev, | |
487 | "<%s> transfer message: %d\n", __func__, i); | |
488 | /* write/read data */ | |
489 | #ifdef CONFIG_I2C_DEBUG_BUS | |
1d5ef2a8 | 490 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
aa11e38c DA |
491 | dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, " |
492 | "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__, | |
493 | (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), | |
494 | (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), | |
495 | (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); | |
1d5ef2a8 | 496 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); |
aa11e38c DA |
497 | dev_dbg(&i2c_imx->adapter.dev, |
498 | "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, " | |
499 | "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__, | |
500 | (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), | |
501 | (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), | |
502 | (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), | |
503 | (temp & I2SR_RXAK ? 1 : 0)); | |
504 | #endif | |
505 | if (msgs[i].flags & I2C_M_RD) | |
506 | result = i2c_imx_read(i2c_imx, &msgs[i]); | |
507 | else | |
508 | result = i2c_imx_write(i2c_imx, &msgs[i]); | |
da9c99fc AP |
509 | if (result) |
510 | goto fail0; | |
aa11e38c DA |
511 | } |
512 | ||
513 | fail0: | |
514 | /* Stop I2C transfer */ | |
515 | i2c_imx_stop(i2c_imx); | |
516 | ||
517 | dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, | |
518 | (result < 0) ? "error" : "success msg", | |
519 | (result < 0) ? result : num); | |
520 | return (result < 0) ? result : num; | |
521 | } | |
522 | ||
523 | static u32 i2c_imx_func(struct i2c_adapter *adapter) | |
524 | { | |
525 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
526 | } | |
527 | ||
528 | static struct i2c_algorithm i2c_imx_algo = { | |
529 | .master_xfer = i2c_imx_xfer, | |
530 | .functionality = i2c_imx_func, | |
531 | }; | |
532 | ||
533 | static int __init i2c_imx_probe(struct platform_device *pdev) | |
534 | { | |
5bdfba29 SG |
535 | const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids, |
536 | &pdev->dev); | |
aa11e38c DA |
537 | struct imx_i2c_struct *i2c_imx; |
538 | struct resource *res; | |
593702c7 | 539 | struct imxi2c_platform_data *pdata = pdev->dev.platform_data; |
0fc1347a | 540 | const struct platform_device_id *imx_id; |
aa11e38c | 541 | void __iomem *base; |
8c88ab04 WS |
542 | int irq, ret; |
543 | u32 bitrate; | |
aa11e38c DA |
544 | |
545 | dev_dbg(&pdev->dev, "<%s>\n", __func__); | |
546 | ||
aa11e38c DA |
547 | irq = platform_get_irq(pdev, 0); |
548 | if (irq < 0) { | |
549 | dev_err(&pdev->dev, "can't get irq number\n"); | |
550 | return -ENOENT; | |
551 | } | |
552 | ||
3cc2d009 | 553 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
84dbf809 TR |
554 | base = devm_ioremap_resource(&pdev->dev, res); |
555 | if (IS_ERR(base)) | |
556 | return PTR_ERR(base); | |
aa11e38c | 557 | |
9f8a3e7f RZ |
558 | i2c_imx = devm_kzalloc(&pdev->dev, sizeof(struct imx_i2c_struct), |
559 | GFP_KERNEL); | |
aa11e38c DA |
560 | if (!i2c_imx) { |
561 | dev_err(&pdev->dev, "can't allocate interface\n"); | |
9f8a3e7f | 562 | return -ENOMEM; |
309c18d2 DA |
563 | } |
564 | ||
5bdfba29 | 565 | if (of_id) |
0fc1347a JL |
566 | imx_id = of_id->data; |
567 | else | |
568 | imx_id = platform_get_device_id(pdev); | |
569 | ||
570 | i2c_imx->devtype = imx_id->driver_data; | |
5bdfba29 | 571 | |
aa11e38c | 572 | /* Setup i2c_imx driver structure */ |
973c5ed4 | 573 | strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); |
aa11e38c DA |
574 | i2c_imx->adapter.owner = THIS_MODULE; |
575 | i2c_imx->adapter.algo = &i2c_imx_algo; | |
576 | i2c_imx->adapter.dev.parent = &pdev->dev; | |
577 | i2c_imx->adapter.nr = pdev->id; | |
dfcd04b1 | 578 | i2c_imx->adapter.dev.of_node = pdev->dev.of_node; |
aa11e38c | 579 | i2c_imx->base = base; |
aa11e38c DA |
580 | |
581 | /* Get I2C clock */ | |
1f09c672 | 582 | i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); |
aa11e38c | 583 | if (IS_ERR(i2c_imx->clk)) { |
aa11e38c | 584 | dev_err(&pdev->dev, "can't get I2C clock\n"); |
9f8a3e7f | 585 | return PTR_ERR(i2c_imx->clk); |
aa11e38c | 586 | } |
aa11e38c | 587 | |
46f2832b JL |
588 | ret = clk_prepare_enable(i2c_imx->clk); |
589 | if (ret) { | |
590 | dev_err(&pdev->dev, "can't enable I2C clock\n"); | |
591 | return ret; | |
592 | } | |
aa11e38c | 593 | /* Request IRQ */ |
9f8a3e7f RZ |
594 | ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0, |
595 | pdev->name, i2c_imx); | |
aa11e38c | 596 | if (ret) { |
9f8a3e7f RZ |
597 | dev_err(&pdev->dev, "can't claim irq %d\n", irq); |
598 | return ret; | |
aa11e38c DA |
599 | } |
600 | ||
601 | /* Init queue */ | |
602 | init_waitqueue_head(&i2c_imx->queue); | |
603 | ||
604 | /* Set up adapter data */ | |
605 | i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); | |
606 | ||
607 | /* Set up clock divider */ | |
dfcd04b1 SG |
608 | bitrate = IMX_I2C_BIT_RATE; |
609 | ret = of_property_read_u32(pdev->dev.of_node, | |
610 | "clock-frequency", &bitrate); | |
611 | if (ret < 0 && pdata && pdata->bitrate) | |
612 | bitrate = pdata->bitrate; | |
613 | i2c_imx_set_clk(i2c_imx, bitrate); | |
aa11e38c DA |
614 | |
615 | /* Set up chip registers to defaults */ | |
171408c2 JL |
616 | imx_i2c_write_reg(IMX_I2CR_IEN_OPCODE ^ I2CR_IEN, i2c_imx, IMX_I2C_I2CR); |
617 | imx_i2c_write_reg(IMX_I2SR_CLR_OPCODE, i2c_imx, IMX_I2C_I2SR); | |
aa11e38c DA |
618 | |
619 | /* Add I2C adapter */ | |
620 | ret = i2c_add_numbered_adapter(&i2c_imx->adapter); | |
621 | if (ret < 0) { | |
622 | dev_err(&pdev->dev, "registration failed\n"); | |
9f8a3e7f | 623 | return ret; |
aa11e38c DA |
624 | } |
625 | ||
dfcd04b1 SG |
626 | of_i2c_register_devices(&i2c_imx->adapter); |
627 | ||
aa11e38c DA |
628 | /* Set up platform driver data */ |
629 | platform_set_drvdata(pdev, i2c_imx); | |
46f2832b | 630 | clk_disable_unprepare(i2c_imx->clk); |
aa11e38c | 631 | |
9f8a3e7f | 632 | dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); |
aa11e38c | 633 | dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n", |
9f8a3e7f RZ |
634 | res->start, res->end); |
635 | dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x\n", | |
636 | resource_size(res), res->start); | |
aa11e38c DA |
637 | dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", |
638 | i2c_imx->adapter.name); | |
06d141e9 | 639 | dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); |
aa11e38c DA |
640 | |
641 | return 0; /* Return OK */ | |
aa11e38c DA |
642 | } |
643 | ||
644 | static int __exit i2c_imx_remove(struct platform_device *pdev) | |
645 | { | |
646 | struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); | |
aa11e38c DA |
647 | |
648 | /* remove adapter */ | |
649 | dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); | |
650 | i2c_del_adapter(&i2c_imx->adapter); | |
aa11e38c | 651 | |
aa11e38c | 652 | /* setup chip registers to defaults */ |
1d5ef2a8 JL |
653 | imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); |
654 | imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); | |
655 | imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); | |
656 | imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); | |
aa11e38c | 657 | |
aa11e38c DA |
658 | return 0; |
659 | } | |
660 | ||
661 | static struct platform_driver i2c_imx_driver = { | |
aa11e38c DA |
662 | .remove = __exit_p(i2c_imx_remove), |
663 | .driver = { | |
664 | .name = DRIVER_NAME, | |
665 | .owner = THIS_MODULE, | |
dfcd04b1 | 666 | .of_match_table = i2c_imx_dt_ids, |
5bdfba29 SG |
667 | }, |
668 | .id_table = imx_i2c_devtype, | |
aa11e38c DA |
669 | }; |
670 | ||
671 | static int __init i2c_adap_imx_init(void) | |
672 | { | |
673 | return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe); | |
674 | } | |
5d3f3331 | 675 | subsys_initcall(i2c_adap_imx_init); |
aa11e38c DA |
676 | |
677 | static void __exit i2c_adap_imx_exit(void) | |
678 | { | |
679 | platform_driver_unregister(&i2c_imx_driver); | |
680 | } | |
aa11e38c DA |
681 | module_exit(i2c_adap_imx_exit); |
682 | ||
683 | MODULE_LICENSE("GPL"); | |
684 | MODULE_AUTHOR("Darius Augulis"); | |
685 | MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); | |
686 | MODULE_ALIAS("platform:" DRIVER_NAME); |