Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
a0832798 TP |
2 | * Driver for the i2c controller on the Marvell line of host bridges |
3 | * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family). | |
1da177e4 LT |
4 | * |
5 | * Author: Mark A. Greer <mgreer@mvista.com> | |
6 | * | |
7 | * 2005 (c) MontaVista, Software, Inc. This file is licensed under | |
8 | * the terms of the GNU General Public License version 2. This program | |
9 | * is licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | */ | |
12 | #include <linux/kernel.h> | |
5a0e3ad6 | 13 | #include <linux/slab.h> |
1da177e4 LT |
14 | #include <linux/module.h> |
15 | #include <linux/spinlock.h> | |
16 | #include <linux/i2c.h> | |
17 | #include <linux/interrupt.h> | |
a0832798 | 18 | #include <linux/mv643xx_i2c.h> |
d052d1be | 19 | #include <linux/platform_device.h> |
370136bc | 20 | #include <linux/reset.h> |
21782180 | 21 | #include <linux/io.h> |
b61d1575 | 22 | #include <linux/of.h> |
004e8ed7 | 23 | #include <linux/of_device.h> |
b61d1575 | 24 | #include <linux/of_irq.h> |
b61d1575 AL |
25 | #include <linux/clk.h> |
26 | #include <linux/err.h> | |
c1d15b68 | 27 | #include <linux/delay.h> |
1da177e4 | 28 | |
683e69b8 MR |
29 | #define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1) |
30 | #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7) | |
31 | #define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3) | |
32 | ||
12598695 TP |
33 | #define MV64XXX_I2C_REG_CONTROL_ACK BIT(2) |
34 | #define MV64XXX_I2C_REG_CONTROL_IFLG BIT(3) | |
35 | #define MV64XXX_I2C_REG_CONTROL_STOP BIT(4) | |
36 | #define MV64XXX_I2C_REG_CONTROL_START BIT(5) | |
37 | #define MV64XXX_I2C_REG_CONTROL_TWSIEN BIT(6) | |
38 | #define MV64XXX_I2C_REG_CONTROL_INTEN BIT(7) | |
1da177e4 LT |
39 | |
40 | /* Ctlr status values */ | |
41 | #define MV64XXX_I2C_STATUS_BUS_ERR 0x00 | |
42 | #define MV64XXX_I2C_STATUS_MAST_START 0x08 | |
43 | #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10 | |
44 | #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18 | |
45 | #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20 | |
46 | #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28 | |
47 | #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30 | |
48 | #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38 | |
49 | #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40 | |
50 | #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48 | |
51 | #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50 | |
52 | #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58 | |
53 | #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0 | |
54 | #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8 | |
55 | #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0 | |
56 | #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8 | |
57 | #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8 | |
58 | ||
930ab3d4 GC |
59 | /* Register defines (I2C bridge) */ |
60 | #define MV64XXX_I2C_REG_TX_DATA_LO 0xc0 | |
61 | #define MV64XXX_I2C_REG_TX_DATA_HI 0xc4 | |
62 | #define MV64XXX_I2C_REG_RX_DATA_LO 0xc8 | |
63 | #define MV64XXX_I2C_REG_RX_DATA_HI 0xcc | |
64 | #define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0 | |
65 | #define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4 | |
66 | #define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8 | |
67 | #define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC | |
68 | #define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0 | |
69 | ||
70 | /* Bridge Control values */ | |
12598695 TP |
71 | #define MV64XXX_I2C_BRIDGE_CONTROL_WR BIT(0) |
72 | #define MV64XXX_I2C_BRIDGE_CONTROL_RD BIT(1) | |
930ab3d4 | 73 | #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2 |
12598695 | 74 | #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT BIT(12) |
930ab3d4 GC |
75 | #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13 |
76 | #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16 | |
12598695 | 77 | #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19) |
00d8689b | 78 | #define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START BIT(20) |
930ab3d4 GC |
79 | |
80 | /* Bridge Status values */ | |
12598695 | 81 | #define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0) |
930ab3d4 | 82 | |
1da177e4 LT |
83 | /* Driver states */ |
84 | enum { | |
85 | MV64XXX_I2C_STATE_INVALID, | |
86 | MV64XXX_I2C_STATE_IDLE, | |
87 | MV64XXX_I2C_STATE_WAITING_FOR_START_COND, | |
eda6bee6 | 88 | MV64XXX_I2C_STATE_WAITING_FOR_RESTART, |
1da177e4 LT |
89 | MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK, |
90 | MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK, | |
91 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK, | |
92 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA, | |
1da177e4 LT |
93 | }; |
94 | ||
95 | /* Driver actions */ | |
96 | enum { | |
97 | MV64XXX_I2C_ACTION_INVALID, | |
98 | MV64XXX_I2C_ACTION_CONTINUE, | |
eda6bee6 | 99 | MV64XXX_I2C_ACTION_SEND_RESTART, |
1da177e4 LT |
100 | MV64XXX_I2C_ACTION_SEND_ADDR_1, |
101 | MV64XXX_I2C_ACTION_SEND_ADDR_2, | |
102 | MV64XXX_I2C_ACTION_SEND_DATA, | |
103 | MV64XXX_I2C_ACTION_RCV_DATA, | |
104 | MV64XXX_I2C_ACTION_RCV_DATA_STOP, | |
105 | MV64XXX_I2C_ACTION_SEND_STOP, | |
106 | }; | |
107 | ||
004e8ed7 MR |
108 | struct mv64xxx_i2c_regs { |
109 | u8 addr; | |
110 | u8 ext_addr; | |
111 | u8 data; | |
112 | u8 control; | |
113 | u8 status; | |
114 | u8 clock; | |
115 | u8 soft_reset; | |
116 | }; | |
117 | ||
1da177e4 | 118 | struct mv64xxx_i2c_data { |
4243fa0b RK |
119 | struct i2c_msg *msgs; |
120 | int num_msgs; | |
1da177e4 LT |
121 | int irq; |
122 | u32 state; | |
123 | u32 action; | |
e91c021c | 124 | u32 aborting; |
1da177e4 LT |
125 | u32 cntl_bits; |
126 | void __iomem *reg_base; | |
004e8ed7 | 127 | struct mv64xxx_i2c_regs reg_offsets; |
1da177e4 LT |
128 | u32 addr1; |
129 | u32 addr2; | |
130 | u32 bytes_left; | |
131 | u32 byte_posn; | |
eda6bee6 | 132 | u32 send_stop; |
1da177e4 LT |
133 | u32 block; |
134 | int rc; | |
135 | u32 freq_m; | |
136 | u32 freq_n; | |
b61d1575 AL |
137 | #if defined(CONFIG_HAVE_CLK) |
138 | struct clk *clk; | |
139 | #endif | |
1da177e4 LT |
140 | wait_queue_head_t waitq; |
141 | spinlock_t lock; | |
142 | struct i2c_msg *msg; | |
143 | struct i2c_adapter adapter; | |
930ab3d4 | 144 | bool offload_enabled; |
c1d15b68 GC |
145 | /* 5us delay in order to avoid repeated start timing violation */ |
146 | bool errata_delay; | |
370136bc | 147 | struct reset_control *rstc; |
c7dcb1fe | 148 | bool irq_clear_inverted; |
1da177e4 LT |
149 | }; |
150 | ||
004e8ed7 MR |
151 | static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = { |
152 | .addr = 0x00, | |
153 | .ext_addr = 0x10, | |
154 | .data = 0x04, | |
155 | .control = 0x08, | |
156 | .status = 0x0c, | |
157 | .clock = 0x0c, | |
158 | .soft_reset = 0x1c, | |
159 | }; | |
160 | ||
3d66ac7d MR |
161 | static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = { |
162 | .addr = 0x00, | |
163 | .ext_addr = 0x04, | |
164 | .data = 0x08, | |
165 | .control = 0x0c, | |
166 | .status = 0x10, | |
167 | .clock = 0x14, | |
168 | .soft_reset = 0x18, | |
169 | }; | |
170 | ||
3420afbc RK |
171 | static void |
172 | mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data, | |
173 | struct i2c_msg *msg) | |
174 | { | |
175 | u32 dir = 0; | |
176 | ||
3420afbc RK |
177 | drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK | |
178 | MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN; | |
179 | ||
180 | if (msg->flags & I2C_M_RD) | |
181 | dir = 1; | |
182 | ||
183 | if (msg->flags & I2C_M_TEN) { | |
184 | drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir; | |
185 | drv_data->addr2 = (u32)msg->addr & 0xff; | |
186 | } else { | |
683e69b8 | 187 | drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir; |
3420afbc RK |
188 | drv_data->addr2 = 0; |
189 | } | |
190 | } | |
191 | ||
1da177e4 LT |
192 | /* |
193 | ***************************************************************************** | |
194 | * | |
195 | * Finite State Machine & Interrupt Routines | |
196 | * | |
197 | ***************************************************************************** | |
198 | */ | |
a07ad1cc DF |
199 | |
200 | /* Reset hardware and initialize FSM */ | |
201 | static void | |
202 | mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data) | |
203 | { | |
930ab3d4 GC |
204 | if (drv_data->offload_enabled) { |
205 | writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); | |
206 | writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING); | |
207 | writel(0, drv_data->reg_base + | |
208 | MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE); | |
209 | writel(0, drv_data->reg_base + | |
210 | MV64XXX_I2C_REG_BRIDGE_INTR_MASK); | |
211 | } | |
212 | ||
004e8ed7 | 213 | writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset); |
683e69b8 | 214 | writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n), |
004e8ed7 MR |
215 | drv_data->reg_base + drv_data->reg_offsets.clock); |
216 | writel(0, drv_data->reg_base + drv_data->reg_offsets.addr); | |
217 | writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr); | |
a07ad1cc | 218 | writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP, |
004e8ed7 | 219 | drv_data->reg_base + drv_data->reg_offsets.control); |
a07ad1cc DF |
220 | drv_data->state = MV64XXX_I2C_STATE_IDLE; |
221 | } | |
222 | ||
1da177e4 LT |
223 | static void |
224 | mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status) | |
225 | { | |
226 | /* | |
227 | * If state is idle, then this is likely the remnants of an old | |
228 | * operation that driver has given up on or the user has killed. | |
229 | * If so, issue the stop condition and go to idle. | |
230 | */ | |
231 | if (drv_data->state == MV64XXX_I2C_STATE_IDLE) { | |
232 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
233 | return; | |
234 | } | |
235 | ||
1da177e4 LT |
236 | /* The status from the ctlr [mostly] tells us what to do next */ |
237 | switch (status) { | |
238 | /* Start condition interrupt */ | |
239 | case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */ | |
240 | case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */ | |
241 | drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1; | |
242 | drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK; | |
243 | break; | |
244 | ||
245 | /* Performing a write */ | |
246 | case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */ | |
247 | if (drv_data->msg->flags & I2C_M_TEN) { | |
248 | drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; | |
249 | drv_data->state = | |
250 | MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; | |
251 | break; | |
252 | } | |
253 | /* FALLTHRU */ | |
254 | case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */ | |
255 | case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */ | |
e91c021c MG |
256 | if ((drv_data->bytes_left == 0) |
257 | || (drv_data->aborting | |
258 | && (drv_data->byte_posn != 0))) { | |
4243fa0b | 259 | if (drv_data->send_stop || drv_data->aborting) { |
eda6bee6 RG |
260 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; |
261 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
262 | } else { | |
263 | drv_data->action = | |
264 | MV64XXX_I2C_ACTION_SEND_RESTART; | |
265 | drv_data->state = | |
266 | MV64XXX_I2C_STATE_WAITING_FOR_RESTART; | |
267 | } | |
e91c021c | 268 | } else { |
1da177e4 LT |
269 | drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA; |
270 | drv_data->state = | |
271 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK; | |
272 | drv_data->bytes_left--; | |
1da177e4 LT |
273 | } |
274 | break; | |
275 | ||
276 | /* Performing a read */ | |
277 | case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */ | |
278 | if (drv_data->msg->flags & I2C_M_TEN) { | |
279 | drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; | |
280 | drv_data->state = | |
281 | MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; | |
282 | break; | |
283 | } | |
284 | /* FALLTHRU */ | |
285 | case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */ | |
286 | if (drv_data->bytes_left == 0) { | |
287 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
288 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
289 | break; | |
290 | } | |
291 | /* FALLTHRU */ | |
292 | case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */ | |
293 | if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK) | |
294 | drv_data->action = MV64XXX_I2C_ACTION_CONTINUE; | |
295 | else { | |
296 | drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA; | |
297 | drv_data->bytes_left--; | |
298 | } | |
299 | drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA; | |
300 | ||
e91c021c | 301 | if ((drv_data->bytes_left == 1) || drv_data->aborting) |
1da177e4 LT |
302 | drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK; |
303 | break; | |
304 | ||
305 | case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */ | |
306 | drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP; | |
307 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
308 | break; | |
309 | ||
310 | case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */ | |
311 | case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */ | |
312 | case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */ | |
313 | /* Doesn't seem to be a device at other end */ | |
314 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
315 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
6faa3535 | 316 | drv_data->rc = -ENXIO; |
1da177e4 LT |
317 | break; |
318 | ||
319 | default: | |
320 | dev_err(&drv_data->adapter.dev, | |
321 | "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, " | |
322 | "status: 0x%x, addr: 0x%x, flags: 0x%x\n", | |
323 | drv_data->state, status, drv_data->msg->addr, | |
324 | drv_data->msg->flags); | |
325 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
a07ad1cc | 326 | mv64xxx_i2c_hw_init(drv_data); |
1da177e4 LT |
327 | drv_data->rc = -EIO; |
328 | } | |
329 | } | |
330 | ||
4c5b38e8 WS |
331 | static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data) |
332 | { | |
485ecdf1 WS |
333 | drv_data->msg = drv_data->msgs; |
334 | drv_data->byte_posn = 0; | |
335 | drv_data->bytes_left = drv_data->msg->len; | |
336 | drv_data->aborting = 0; | |
337 | drv_data->rc = 0; | |
338 | ||
00d8689b TP |
339 | mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs); |
340 | writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START, | |
341 | drv_data->reg_base + drv_data->reg_offsets.control); | |
4c5b38e8 WS |
342 | } |
343 | ||
1da177e4 LT |
344 | static void |
345 | mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) | |
346 | { | |
347 | switch(drv_data->action) { | |
eda6bee6 | 348 | case MV64XXX_I2C_ACTION_SEND_RESTART: |
4243fa0b RK |
349 | /* We should only get here if we have further messages */ |
350 | BUG_ON(drv_data->num_msgs == 0); | |
351 | ||
4243fa0b RK |
352 | drv_data->msgs++; |
353 | drv_data->num_msgs--; | |
4c5b38e8 | 354 | mv64xxx_i2c_send_start(drv_data); |
4243fa0b | 355 | |
c1d15b68 GC |
356 | if (drv_data->errata_delay) |
357 | udelay(5); | |
358 | ||
4243fa0b RK |
359 | /* |
360 | * We're never at the start of the message here, and by this | |
361 | * time it's already too late to do any protocol mangling. | |
362 | * Thankfully, do not advertise support for that feature. | |
363 | */ | |
364 | drv_data->send_stop = drv_data->num_msgs == 1; | |
eda6bee6 RG |
365 | break; |
366 | ||
1da177e4 LT |
367 | case MV64XXX_I2C_ACTION_CONTINUE: |
368 | writel(drv_data->cntl_bits, | |
004e8ed7 | 369 | drv_data->reg_base + drv_data->reg_offsets.control); |
1da177e4 LT |
370 | break; |
371 | ||
1da177e4 LT |
372 | case MV64XXX_I2C_ACTION_SEND_ADDR_1: |
373 | writel(drv_data->addr1, | |
004e8ed7 | 374 | drv_data->reg_base + drv_data->reg_offsets.data); |
1da177e4 | 375 | writel(drv_data->cntl_bits, |
004e8ed7 | 376 | drv_data->reg_base + drv_data->reg_offsets.control); |
1da177e4 LT |
377 | break; |
378 | ||
379 | case MV64XXX_I2C_ACTION_SEND_ADDR_2: | |
380 | writel(drv_data->addr2, | |
004e8ed7 | 381 | drv_data->reg_base + drv_data->reg_offsets.data); |
1da177e4 | 382 | writel(drv_data->cntl_bits, |
004e8ed7 | 383 | drv_data->reg_base + drv_data->reg_offsets.control); |
1da177e4 LT |
384 | break; |
385 | ||
386 | case MV64XXX_I2C_ACTION_SEND_DATA: | |
387 | writel(drv_data->msg->buf[drv_data->byte_posn++], | |
004e8ed7 | 388 | drv_data->reg_base + drv_data->reg_offsets.data); |
1da177e4 | 389 | writel(drv_data->cntl_bits, |
004e8ed7 | 390 | drv_data->reg_base + drv_data->reg_offsets.control); |
1da177e4 LT |
391 | break; |
392 | ||
393 | case MV64XXX_I2C_ACTION_RCV_DATA: | |
394 | drv_data->msg->buf[drv_data->byte_posn++] = | |
004e8ed7 | 395 | readl(drv_data->reg_base + drv_data->reg_offsets.data); |
1da177e4 | 396 | writel(drv_data->cntl_bits, |
004e8ed7 | 397 | drv_data->reg_base + drv_data->reg_offsets.control); |
1da177e4 LT |
398 | break; |
399 | ||
400 | case MV64XXX_I2C_ACTION_RCV_DATA_STOP: | |
401 | drv_data->msg->buf[drv_data->byte_posn++] = | |
004e8ed7 | 402 | readl(drv_data->reg_base + drv_data->reg_offsets.data); |
1da177e4 LT |
403 | drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; |
404 | writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, | |
004e8ed7 | 405 | drv_data->reg_base + drv_data->reg_offsets.control); |
1da177e4 | 406 | drv_data->block = 0; |
c1d15b68 GC |
407 | if (drv_data->errata_delay) |
408 | udelay(5); | |
409 | ||
d295a86e | 410 | wake_up(&drv_data->waitq); |
1da177e4 LT |
411 | break; |
412 | ||
413 | case MV64XXX_I2C_ACTION_INVALID: | |
414 | default: | |
415 | dev_err(&drv_data->adapter.dev, | |
416 | "mv64xxx_i2c_do_action: Invalid action: %d\n", | |
417 | drv_data->action); | |
418 | drv_data->rc = -EIO; | |
930ab3d4 | 419 | |
1da177e4 LT |
420 | /* FALLTHRU */ |
421 | case MV64XXX_I2C_ACTION_SEND_STOP: | |
422 | drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; | |
423 | writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, | |
004e8ed7 | 424 | drv_data->reg_base + drv_data->reg_offsets.control); |
1da177e4 | 425 | drv_data->block = 0; |
d295a86e | 426 | wake_up(&drv_data->waitq); |
1da177e4 | 427 | break; |
00d8689b TP |
428 | } |
429 | } | |
930ab3d4 | 430 | |
00d8689b TP |
431 | static void |
432 | mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data, | |
433 | struct i2c_msg *msg) | |
434 | { | |
435 | u32 buf[2]; | |
436 | ||
437 | buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO); | |
438 | buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI); | |
439 | ||
440 | memcpy(msg->buf, buf, msg->len); | |
441 | } | |
442 | ||
443 | static int | |
444 | mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data) | |
445 | { | |
446 | u32 cause, status; | |
447 | ||
448 | cause = readl(drv_data->reg_base + | |
449 | MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE); | |
450 | if (!cause) | |
451 | return IRQ_NONE; | |
452 | ||
453 | status = readl(drv_data->reg_base + | |
454 | MV64XXX_I2C_REG_BRIDGE_STATUS); | |
455 | ||
456 | if (status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) { | |
457 | drv_data->rc = -EIO; | |
458 | goto out; | |
459 | } | |
460 | ||
461 | drv_data->rc = 0; | |
462 | ||
463 | /* | |
464 | * Transaction is a one message read transaction, read data | |
465 | * for this message. | |
466 | */ | |
467 | if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) { | |
468 | mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs); | |
469 | drv_data->msgs++; | |
470 | drv_data->num_msgs--; | |
1da177e4 | 471 | } |
00d8689b TP |
472 | /* |
473 | * Transaction is a two messages write/read transaction, read | |
474 | * data for the second (read) message. | |
475 | */ | |
476 | else if (drv_data->num_msgs == 2 && | |
477 | !(drv_data->msgs[0].flags & I2C_M_RD) && | |
478 | drv_data->msgs[1].flags & I2C_M_RD) { | |
479 | mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1); | |
480 | drv_data->msgs += 2; | |
481 | drv_data->num_msgs -= 2; | |
482 | } | |
483 | ||
484 | out: | |
485 | writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); | |
486 | writel(0, drv_data->reg_base + | |
487 | MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE); | |
488 | drv_data->block = 0; | |
489 | ||
490 | wake_up(&drv_data->waitq); | |
491 | ||
492 | return IRQ_HANDLED; | |
1da177e4 LT |
493 | } |
494 | ||
b0999cc5 | 495 | static irqreturn_t |
7d12e780 | 496 | mv64xxx_i2c_intr(int irq, void *dev_id) |
1da177e4 LT |
497 | { |
498 | struct mv64xxx_i2c_data *drv_data = dev_id; | |
499 | unsigned long flags; | |
500 | u32 status; | |
b0999cc5 | 501 | irqreturn_t rc = IRQ_NONE; |
1da177e4 LT |
502 | |
503 | spin_lock_irqsave(&drv_data->lock, flags); | |
930ab3d4 | 504 | |
00d8689b TP |
505 | if (drv_data->offload_enabled) |
506 | rc = mv64xxx_i2c_intr_offload(drv_data); | |
507 | ||
004e8ed7 | 508 | while (readl(drv_data->reg_base + drv_data->reg_offsets.control) & |
1da177e4 | 509 | MV64XXX_I2C_REG_CONTROL_IFLG) { |
004e8ed7 | 510 | status = readl(drv_data->reg_base + drv_data->reg_offsets.status); |
1da177e4 LT |
511 | mv64xxx_i2c_fsm(drv_data, status); |
512 | mv64xxx_i2c_do_action(drv_data); | |
c7dcb1fe MR |
513 | |
514 | if (drv_data->irq_clear_inverted) | |
515 | writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG, | |
516 | drv_data->reg_base + drv_data->reg_offsets.control); | |
517 | ||
1da177e4 LT |
518 | rc = IRQ_HANDLED; |
519 | } | |
520 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
521 | ||
522 | return rc; | |
523 | } | |
524 | ||
525 | /* | |
526 | ***************************************************************************** | |
527 | * | |
528 | * I2C Msg Execution Routines | |
529 | * | |
530 | ***************************************************************************** | |
531 | */ | |
1da177e4 LT |
532 | static void |
533 | mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data) | |
534 | { | |
535 | long time_left; | |
536 | unsigned long flags; | |
537 | char abort = 0; | |
538 | ||
d295a86e | 539 | time_left = wait_event_timeout(drv_data->waitq, |
8a52c6b4 | 540 | !drv_data->block, drv_data->adapter.timeout); |
1da177e4 LT |
541 | |
542 | spin_lock_irqsave(&drv_data->lock, flags); | |
543 | if (!time_left) { /* Timed out */ | |
544 | drv_data->rc = -ETIMEDOUT; | |
545 | abort = 1; | |
546 | } else if (time_left < 0) { /* Interrupted/Error */ | |
547 | drv_data->rc = time_left; /* errno value */ | |
548 | abort = 1; | |
549 | } | |
550 | ||
551 | if (abort && drv_data->block) { | |
e91c021c | 552 | drv_data->aborting = 1; |
1da177e4 LT |
553 | spin_unlock_irqrestore(&drv_data->lock, flags); |
554 | ||
555 | time_left = wait_event_timeout(drv_data->waitq, | |
8a52c6b4 | 556 | !drv_data->block, drv_data->adapter.timeout); |
1da177e4 | 557 | |
e91c021c | 558 | if ((time_left <= 0) && drv_data->block) { |
1da177e4 LT |
559 | drv_data->state = MV64XXX_I2C_STATE_IDLE; |
560 | dev_err(&drv_data->adapter.dev, | |
e91c021c MG |
561 | "mv64xxx: I2C bus locked, block: %d, " |
562 | "time_left: %d\n", drv_data->block, | |
563 | (int)time_left); | |
a07ad1cc | 564 | mv64xxx_i2c_hw_init(drv_data); |
1da177e4 LT |
565 | } |
566 | } else | |
567 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
568 | } | |
569 | ||
570 | static int | |
eda6bee6 | 571 | mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg, |
4243fa0b | 572 | int is_last) |
1da177e4 LT |
573 | { |
574 | unsigned long flags; | |
575 | ||
576 | spin_lock_irqsave(&drv_data->lock, flags); | |
1da177e4 | 577 | |
79970db2 WS |
578 | drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND; |
579 | ||
eda6bee6 | 580 | drv_data->send_stop = is_last; |
1da177e4 | 581 | drv_data->block = 1; |
b0200abe | 582 | mv64xxx_i2c_send_start(drv_data); |
1da177e4 LT |
583 | spin_unlock_irqrestore(&drv_data->lock, flags); |
584 | ||
585 | mv64xxx_i2c_wait_for_completion(drv_data); | |
586 | return drv_data->rc; | |
587 | } | |
588 | ||
00d8689b TP |
589 | static void |
590 | mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data) | |
591 | { | |
592 | struct i2c_msg *msg = drv_data->msgs; | |
593 | u32 buf[2]; | |
594 | ||
595 | memcpy(buf, msg->buf, msg->len); | |
596 | ||
597 | writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO); | |
598 | writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI); | |
599 | } | |
600 | ||
601 | static int | |
602 | mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data) | |
603 | { | |
604 | struct i2c_msg *msgs = drv_data->msgs; | |
605 | int num = drv_data->num_msgs; | |
606 | unsigned long ctrl_reg; | |
607 | unsigned long flags; | |
608 | ||
609 | spin_lock_irqsave(&drv_data->lock, flags); | |
610 | ||
611 | /* Build transaction */ | |
612 | ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE | | |
613 | (msgs[0].addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT); | |
614 | ||
615 | if (msgs[0].flags & I2C_M_TEN) | |
616 | ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT; | |
617 | ||
618 | /* Single write message transaction */ | |
619 | if (num == 1 && !(msgs[0].flags & I2C_M_RD)) { | |
620 | size_t len = msgs[0].len - 1; | |
621 | ||
622 | ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR | | |
623 | (len << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT); | |
624 | mv64xxx_i2c_prepare_tx(drv_data); | |
625 | } | |
626 | /* Single read message transaction */ | |
627 | else if (num == 1 && msgs[0].flags & I2C_M_RD) { | |
628 | size_t len = msgs[0].len - 1; | |
629 | ||
630 | ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD | | |
631 | (len << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT); | |
632 | } | |
633 | /* | |
634 | * Transaction with one write and one read message. This is | |
635 | * guaranteed by the mv64xx_i2c_can_offload() checks. | |
636 | */ | |
637 | else if (num == 2) { | |
638 | size_t lentx = msgs[0].len - 1; | |
639 | size_t lenrx = msgs[1].len - 1; | |
640 | ||
641 | ctrl_reg |= | |
642 | MV64XXX_I2C_BRIDGE_CONTROL_RD | | |
643 | MV64XXX_I2C_BRIDGE_CONTROL_WR | | |
644 | (lentx << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT) | | |
645 | (lenrx << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT) | | |
646 | MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START; | |
647 | mv64xxx_i2c_prepare_tx(drv_data); | |
648 | } | |
649 | ||
650 | /* Execute transaction */ | |
651 | drv_data->block = 1; | |
652 | writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); | |
653 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
654 | ||
655 | mv64xxx_i2c_wait_for_completion(drv_data); | |
656 | ||
657 | return drv_data->rc; | |
658 | } | |
659 | ||
660 | static bool | |
661 | mv64xxx_i2c_valid_offload_sz(struct i2c_msg *msg) | |
662 | { | |
663 | return msg->len <= 8 && msg->len >= 1; | |
664 | } | |
665 | ||
666 | static bool | |
667 | mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data) | |
668 | { | |
669 | struct i2c_msg *msgs = drv_data->msgs; | |
670 | int num = drv_data->num_msgs; | |
671 | ||
00d8689b TP |
672 | if (!drv_data->offload_enabled) |
673 | return false; | |
674 | ||
675 | /* | |
676 | * We can offload a transaction consisting of a single | |
677 | * message, as long as the message has a length between 1 and | |
678 | * 8 bytes. | |
679 | */ | |
680 | if (num == 1 && mv64xxx_i2c_valid_offload_sz(msgs)) | |
681 | return true; | |
682 | ||
683 | /* | |
684 | * We can offload a transaction consisting of two messages, if | |
685 | * the first is a write and a second is a read, and both have | |
686 | * a length between 1 and 8 bytes. | |
687 | */ | |
688 | if (num == 2 && | |
689 | mv64xxx_i2c_valid_offload_sz(msgs) && | |
690 | mv64xxx_i2c_valid_offload_sz(msgs + 1) && | |
691 | !(msgs[0].flags & I2C_M_RD) && | |
692 | msgs[1].flags & I2C_M_RD) | |
693 | return true; | |
694 | ||
695 | return false; | |
696 | } | |
697 | ||
1da177e4 LT |
698 | /* |
699 | ***************************************************************************** | |
700 | * | |
701 | * I2C Core Support Routines (Interface to higher level I2C code) | |
702 | * | |
703 | ***************************************************************************** | |
704 | */ | |
705 | static u32 | |
706 | mv64xxx_i2c_functionality(struct i2c_adapter *adap) | |
707 | { | |
708 | return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; | |
709 | } | |
710 | ||
711 | static int | |
712 | mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
713 | { | |
714 | struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap); | |
4243fa0b | 715 | int rc, ret = num; |
1da177e4 | 716 | |
4243fa0b RK |
717 | BUG_ON(drv_data->msgs != NULL); |
718 | drv_data->msgs = msgs; | |
719 | drv_data->num_msgs = num; | |
720 | ||
00d8689b TP |
721 | if (mv64xxx_i2c_can_offload(drv_data)) |
722 | rc = mv64xxx_i2c_offload_xfer(drv_data); | |
723 | else | |
724 | rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1); | |
725 | ||
4243fa0b RK |
726 | if (rc < 0) |
727 | ret = rc; | |
728 | ||
729 | drv_data->num_msgs = 0; | |
730 | drv_data->msgs = NULL; | |
1da177e4 | 731 | |
4243fa0b | 732 | return ret; |
1da177e4 LT |
733 | } |
734 | ||
8f9082c5 | 735 | static const struct i2c_algorithm mv64xxx_i2c_algo = { |
1da177e4 LT |
736 | .master_xfer = mv64xxx_i2c_xfer, |
737 | .functionality = mv64xxx_i2c_functionality, | |
738 | }; | |
739 | ||
740 | /* | |
741 | ***************************************************************************** | |
742 | * | |
743 | * Driver Interface & Early Init Routines | |
744 | * | |
745 | ***************************************************************************** | |
746 | */ | |
004e8ed7 | 747 | static const struct of_device_id mv64xxx_i2c_of_match_table[] = { |
5ed9d92f | 748 | { .compatible = "allwinner,sun4i-a10-i2c", .data = &mv64xxx_i2c_regs_sun4i}, |
c7dcb1fe | 749 | { .compatible = "allwinner,sun6i-a31-i2c", .data = &mv64xxx_i2c_regs_sun4i}, |
004e8ed7 | 750 | { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx}, |
930ab3d4 | 751 | { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx}, |
6cf70ae9 | 752 | { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx}, |
004e8ed7 MR |
753 | {} |
754 | }; | |
755 | MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table); | |
756 | ||
b61d1575 | 757 | #ifdef CONFIG_OF |
c1a99467 | 758 | #ifdef CONFIG_HAVE_CLK |
0b255e92 | 759 | static int |
b61d1575 AL |
760 | mv64xxx_calc_freq(const int tclk, const int n, const int m) |
761 | { | |
762 | return tclk / (10 * (m + 1) * (2 << n)); | |
763 | } | |
764 | ||
0b255e92 | 765 | static bool |
b61d1575 AL |
766 | mv64xxx_find_baud_factors(const u32 req_freq, const u32 tclk, u32 *best_n, |
767 | u32 *best_m) | |
768 | { | |
769 | int freq, delta, best_delta = INT_MAX; | |
770 | int m, n; | |
771 | ||
772 | for (n = 0; n <= 7; n++) | |
773 | for (m = 0; m <= 15; m++) { | |
774 | freq = mv64xxx_calc_freq(tclk, n, m); | |
775 | delta = req_freq - freq; | |
776 | if (delta >= 0 && delta < best_delta) { | |
777 | *best_m = m; | |
778 | *best_n = n; | |
779 | best_delta = delta; | |
780 | } | |
781 | if (best_delta == 0) | |
782 | return true; | |
783 | } | |
784 | if (best_delta == INT_MAX) | |
785 | return false; | |
786 | return true; | |
787 | } | |
c1a99467 | 788 | #endif /* CONFIG_HAVE_CLK */ |
b61d1575 | 789 | |
0b255e92 | 790 | static int |
b61d1575 | 791 | mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, |
004e8ed7 | 792 | struct device *dev) |
b61d1575 | 793 | { |
b61d1575 AL |
794 | /* CLK is mandatory when using DT to describe the i2c bus. We |
795 | * need to know tclk in order to calculate bus clock | |
796 | * factors. | |
797 | */ | |
798 | #if !defined(CONFIG_HAVE_CLK) | |
799 | /* Have OF but no CLK */ | |
800 | return -ENODEV; | |
801 | #else | |
c1a99467 TR |
802 | const struct of_device_id *device; |
803 | struct device_node *np = dev->of_node; | |
804 | u32 bus_freq, tclk; | |
805 | int rc = 0; | |
806 | ||
b61d1575 AL |
807 | if (IS_ERR(drv_data->clk)) { |
808 | rc = -ENODEV; | |
809 | goto out; | |
810 | } | |
811 | tclk = clk_get_rate(drv_data->clk); | |
4c730a06 | 812 | |
0ce4bc1d | 813 | if (of_property_read_u32(np, "clock-frequency", &bus_freq)) |
4c730a06 GC |
814 | bus_freq = 100000; /* 100kHz by default */ |
815 | ||
b61d1575 AL |
816 | if (!mv64xxx_find_baud_factors(bus_freq, tclk, |
817 | &drv_data->freq_n, &drv_data->freq_m)) { | |
818 | rc = -EINVAL; | |
819 | goto out; | |
820 | } | |
821 | drv_data->irq = irq_of_parse_and_map(np, 0); | |
822 | ||
f2a67d0c | 823 | drv_data->rstc = devm_reset_control_get_optional(dev, NULL); |
370136bc MR |
824 | if (IS_ERR(drv_data->rstc)) { |
825 | if (PTR_ERR(drv_data->rstc) == -EPROBE_DEFER) { | |
826 | rc = -EPROBE_DEFER; | |
827 | goto out; | |
828 | } | |
829 | } else { | |
830 | reset_control_deassert(drv_data->rstc); | |
831 | } | |
832 | ||
b61d1575 AL |
833 | /* Its not yet defined how timeouts will be specified in device tree. |
834 | * So hard code the value to 1 second. | |
835 | */ | |
836 | drv_data->adapter.timeout = HZ; | |
004e8ed7 MR |
837 | |
838 | device = of_match_device(mv64xxx_i2c_of_match_table, dev); | |
839 | if (!device) | |
840 | return -ENODEV; | |
841 | ||
842 | memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets)); | |
843 | ||
930ab3d4 GC |
844 | /* |
845 | * For controllers embedded in new SoCs activate the | |
c1d15b68 | 846 | * Transaction Generator support and the errata fix. |
930ab3d4 | 847 | */ |
c1d15b68 | 848 | if (of_device_is_compatible(np, "marvell,mv78230-i2c")) { |
930ab3d4 | 849 | drv_data->offload_enabled = true; |
c1d15b68 GC |
850 | drv_data->errata_delay = true; |
851 | } | |
930ab3d4 | 852 | |
6cf70ae9 GC |
853 | if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) { |
854 | drv_data->offload_enabled = false; | |
855 | drv_data->errata_delay = true; | |
856 | } | |
c7dcb1fe MR |
857 | |
858 | if (of_device_is_compatible(np, "allwinner,sun6i-a31-i2c")) | |
859 | drv_data->irq_clear_inverted = true; | |
860 | ||
b61d1575 AL |
861 | out: |
862 | return rc; | |
863 | #endif | |
864 | } | |
865 | #else /* CONFIG_OF */ | |
0b255e92 | 866 | static int |
b61d1575 | 867 | mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, |
004e8ed7 | 868 | struct device *dev) |
b61d1575 AL |
869 | { |
870 | return -ENODEV; | |
871 | } | |
872 | #endif /* CONFIG_OF */ | |
873 | ||
0b255e92 | 874 | static int |
3ae5eaec | 875 | mv64xxx_i2c_probe(struct platform_device *pd) |
1da177e4 | 876 | { |
1da177e4 | 877 | struct mv64xxx_i2c_data *drv_data; |
6d4028c6 | 878 | struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev); |
16874b07 | 879 | struct resource *r; |
1da177e4 LT |
880 | int rc; |
881 | ||
b61d1575 | 882 | if ((!pdata && !pd->dev.of_node)) |
1da177e4 LT |
883 | return -ENODEV; |
884 | ||
2c911103 RK |
885 | drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data), |
886 | GFP_KERNEL); | |
1da177e4 LT |
887 | if (!drv_data) |
888 | return -ENOMEM; | |
889 | ||
16874b07 RK |
890 | r = platform_get_resource(pd, IORESOURCE_MEM, 0); |
891 | drv_data->reg_base = devm_ioremap_resource(&pd->dev, r); | |
2c911103 RK |
892 | if (IS_ERR(drv_data->reg_base)) |
893 | return PTR_ERR(drv_data->reg_base); | |
1da177e4 | 894 | |
e91c021c | 895 | strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", |
2096b956 | 896 | sizeof(drv_data->adapter.name)); |
1da177e4 LT |
897 | |
898 | init_waitqueue_head(&drv_data->waitq); | |
899 | spin_lock_init(&drv_data->lock); | |
900 | ||
b61d1575 AL |
901 | #if defined(CONFIG_HAVE_CLK) |
902 | /* Not all platforms have a clk */ | |
4c5c95f5 | 903 | drv_data->clk = devm_clk_get(&pd->dev, NULL); |
b61d1575 AL |
904 | if (!IS_ERR(drv_data->clk)) { |
905 | clk_prepare(drv_data->clk); | |
906 | clk_enable(drv_data->clk); | |
907 | } | |
908 | #endif | |
909 | if (pdata) { | |
910 | drv_data->freq_m = pdata->freq_m; | |
911 | drv_data->freq_n = pdata->freq_n; | |
912 | drv_data->irq = platform_get_irq(pd, 0); | |
913 | drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout); | |
930ab3d4 | 914 | drv_data->offload_enabled = false; |
004e8ed7 | 915 | memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets)); |
b61d1575 | 916 | } else if (pd->dev.of_node) { |
004e8ed7 | 917 | rc = mv64xxx_of_config(drv_data, &pd->dev); |
b61d1575 | 918 | if (rc) |
2c911103 | 919 | goto exit_clk; |
b61d1575 | 920 | } |
48944738 DV |
921 | if (drv_data->irq < 0) { |
922 | rc = -ENXIO; | |
370136bc | 923 | goto exit_reset; |
48944738 | 924 | } |
b61d1575 | 925 | |
12a917f6 | 926 | drv_data->adapter.dev.parent = &pd->dev; |
1da177e4 LT |
927 | drv_data->adapter.algo = &mv64xxx_i2c_algo; |
928 | drv_data->adapter.owner = THIS_MODULE; | |
8c49086c | 929 | drv_data->adapter.class = I2C_CLASS_DEPRECATED; |
65b22ad9 | 930 | drv_data->adapter.nr = pd->id; |
b61d1575 | 931 | drv_data->adapter.dev.of_node = pd->dev.of_node; |
3ae5eaec | 932 | platform_set_drvdata(pd, drv_data); |
1da177e4 LT |
933 | i2c_set_adapdata(&drv_data->adapter, drv_data); |
934 | ||
3269bb63 MB |
935 | mv64xxx_i2c_hw_init(drv_data); |
936 | ||
0c195afb RK |
937 | rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0, |
938 | MV64XXX_I2C_CTLR_NAME, drv_data); | |
939 | if (rc) { | |
dfded4ae | 940 | dev_err(&drv_data->adapter.dev, |
0c195afb RK |
941 | "mv64xxx: Can't register intr handler irq%d: %d\n", |
942 | drv_data->irq, rc); | |
370136bc | 943 | goto exit_reset; |
65b22ad9 | 944 | } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) { |
dfded4ae MG |
945 | dev_err(&drv_data->adapter.dev, |
946 | "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc); | |
1da177e4 LT |
947 | goto exit_free_irq; |
948 | } | |
949 | ||
1da177e4 LT |
950 | return 0; |
951 | ||
2c911103 RK |
952 | exit_free_irq: |
953 | free_irq(drv_data->irq, drv_data); | |
370136bc | 954 | exit_reset: |
f2a67d0c | 955 | if (!IS_ERR_OR_NULL(drv_data->rstc)) |
370136bc | 956 | reset_control_assert(drv_data->rstc); |
2c911103 | 957 | exit_clk: |
b61d1575 AL |
958 | #if defined(CONFIG_HAVE_CLK) |
959 | /* Not all platforms have a clk */ | |
960 | if (!IS_ERR(drv_data->clk)) { | |
961 | clk_disable(drv_data->clk); | |
962 | clk_unprepare(drv_data->clk); | |
963 | } | |
964 | #endif | |
1da177e4 LT |
965 | return rc; |
966 | } | |
967 | ||
0b255e92 | 968 | static int |
3ae5eaec | 969 | mv64xxx_i2c_remove(struct platform_device *dev) |
1da177e4 | 970 | { |
3ae5eaec | 971 | struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev); |
1da177e4 | 972 | |
bf51a8c5 | 973 | i2c_del_adapter(&drv_data->adapter); |
1da177e4 | 974 | free_irq(drv_data->irq, drv_data); |
f2a67d0c | 975 | if (!IS_ERR_OR_NULL(drv_data->rstc)) |
370136bc | 976 | reset_control_assert(drv_data->rstc); |
b61d1575 AL |
977 | #if defined(CONFIG_HAVE_CLK) |
978 | /* Not all platforms have a clk */ | |
979 | if (!IS_ERR(drv_data->clk)) { | |
980 | clk_disable(drv_data->clk); | |
981 | clk_unprepare(drv_data->clk); | |
982 | } | |
983 | #endif | |
1da177e4 | 984 | |
bf51a8c5 | 985 | return 0; |
1da177e4 LT |
986 | } |
987 | ||
3ae5eaec | 988 | static struct platform_driver mv64xxx_i2c_driver = { |
1da177e4 | 989 | .probe = mv64xxx_i2c_probe, |
0b255e92 | 990 | .remove = mv64xxx_i2c_remove, |
3ae5eaec | 991 | .driver = { |
3ae5eaec | 992 | .name = MV64XXX_I2C_CTLR_NAME, |
4e905323 | 993 | .of_match_table = mv64xxx_i2c_of_match_table, |
3ae5eaec | 994 | }, |
1da177e4 LT |
995 | }; |
996 | ||
a3664b51 | 997 | module_platform_driver(mv64xxx_i2c_driver); |
1da177e4 LT |
998 | |
999 | MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>"); | |
1000 | MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver"); | |
1001 | MODULE_LICENSE("GPL"); |