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a8da7fec WS |
1 | /* |
2 | * Freescale MXS I2C bus driver | |
3 | * | |
29faeb38 | 4 | * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> |
82fa63bd | 5 | * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K. |
a8da7fec WS |
6 | * |
7 | * based on a (non-working) driver which was: | |
8 | * | |
9 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | |
10 | * | |
a8da7fec WS |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/slab.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/i2c.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/completion.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/jiffies.h> | |
27 | #include <linux/io.h> | |
6b866c15 | 28 | #include <linux/stmp_device.h> |
b2378668 SG |
29 | #include <linux/of.h> |
30 | #include <linux/of_device.h> | |
62885f59 MV |
31 | #include <linux/dma-mapping.h> |
32 | #include <linux/dmaengine.h> | |
a8da7fec WS |
33 | |
34 | #define DRIVER_NAME "mxs-i2c" | |
35 | ||
36 | #define MXS_I2C_CTRL0 (0x00) | |
37 | #define MXS_I2C_CTRL0_SET (0x04) | |
19e221be | 38 | #define MXS_I2C_CTRL0_CLR (0x08) |
a8da7fec WS |
39 | |
40 | #define MXS_I2C_CTRL0_SFTRST 0x80000000 | |
fc91e401 | 41 | #define MXS_I2C_CTRL0_RUN 0x20000000 |
a8da7fec | 42 | #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 |
19e221be | 43 | #define MXS_I2C_CTRL0_PIO_MODE 0x01000000 |
a8da7fec WS |
44 | #define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000 |
45 | #define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000 | |
46 | #define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000 | |
47 | #define MXS_I2C_CTRL0_MASTER_MODE 0x00020000 | |
48 | #define MXS_I2C_CTRL0_DIRECTION 0x00010000 | |
49 | #define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF) | |
50 | ||
cd4f2d4a MV |
51 | #define MXS_I2C_TIMING0 (0x10) |
52 | #define MXS_I2C_TIMING1 (0x20) | |
53 | #define MXS_I2C_TIMING2 (0x30) | |
54 | ||
a8da7fec WS |
55 | #define MXS_I2C_CTRL1 (0x40) |
56 | #define MXS_I2C_CTRL1_SET (0x44) | |
57 | #define MXS_I2C_CTRL1_CLR (0x48) | |
58 | ||
92b775c2 | 59 | #define MXS_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000 |
a8da7fec WS |
60 | #define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80 |
61 | #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40 | |
62 | #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20 | |
63 | #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10 | |
64 | #define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08 | |
65 | #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04 | |
66 | #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02 | |
67 | #define MXS_I2C_CTRL1_SLAVE_IRQ 0x01 | |
68 | ||
535ebd21 | 69 | #define MXS_I2C_STAT (0x50) |
29faeb38 | 70 | #define MXS_I2C_STAT_GOT_A_NAK 0x10000000 |
535ebd21 LS |
71 | #define MXS_I2C_STAT_BUS_BUSY 0x00000800 |
72 | #define MXS_I2C_STAT_CLK_GEN_BUSY 0x00000400 | |
73 | ||
19e221be | 74 | #define MXS_I2C_DATA(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0) |
fc91e401 | 75 | |
19e221be | 76 | #define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8) |
fc91e401 MV |
77 | |
78 | #define MXS_I2C_DEBUG0_DMAREQ 0x80000000 | |
79 | ||
a8da7fec WS |
80 | #define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \ |
81 | MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \ | |
82 | MXS_I2C_CTRL1_EARLY_TERM_IRQ | \ | |
83 | MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \ | |
84 | MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \ | |
85 | MXS_I2C_CTRL1_SLAVE_IRQ) | |
86 | ||
a8da7fec WS |
87 | |
88 | #define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \ | |
89 | MXS_I2C_CTRL0_PRE_SEND_START | \ | |
90 | MXS_I2C_CTRL0_MASTER_MODE | \ | |
91 | MXS_I2C_CTRL0_DIRECTION | \ | |
92 | MXS_I2C_CTRL0_XFER_COUNT(1)) | |
93 | ||
94 | #define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \ | |
95 | MXS_I2C_CTRL0_MASTER_MODE | \ | |
96 | MXS_I2C_CTRL0_DIRECTION) | |
97 | ||
98 | #define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \ | |
99 | MXS_I2C_CTRL0_MASTER_MODE) | |
100 | ||
616228a1 JB |
101 | enum mxs_i2c_devtype { |
102 | MXS_I2C_UNKNOWN = 0, | |
103 | MXS_I2C_V1, | |
104 | MXS_I2C_V2, | |
105 | }; | |
106 | ||
a8da7fec WS |
107 | /** |
108 | * struct mxs_i2c_dev - per device, private MXS-I2C data | |
109 | * | |
110 | * @dev: driver model device node | |
616228a1 | 111 | * @dev_type: distinguish i.MX23/i.MX28 features |
a8da7fec WS |
112 | * @regs: IO registers pointer |
113 | * @cmd_complete: completion object for transaction wait | |
114 | * @cmd_err: error code for last transaction | |
115 | * @adapter: i2c subsystem adapter node | |
116 | */ | |
117 | struct mxs_i2c_dev { | |
118 | struct device *dev; | |
616228a1 | 119 | enum mxs_i2c_devtype dev_type; |
a8da7fec WS |
120 | void __iomem *regs; |
121 | struct completion cmd_complete; | |
0f40cbc4 | 122 | int cmd_err; |
a8da7fec | 123 | struct i2c_adapter adapter; |
626f0a2f MV |
124 | |
125 | uint32_t timing0; | |
126 | uint32_t timing1; | |
869c6a3e | 127 | uint32_t timing2; |
62885f59 MV |
128 | |
129 | /* DMA support components */ | |
869c6a3e | 130 | struct dma_chan *dmach; |
62885f59 MV |
131 | uint32_t pio_data[2]; |
132 | uint32_t addr_data; | |
133 | struct scatterlist sg_io[2]; | |
134 | bool dma_read; | |
a8da7fec WS |
135 | }; |
136 | ||
63151c53 | 137 | static int mxs_i2c_reset(struct mxs_i2c_dev *i2c) |
a8da7fec | 138 | { |
63151c53 FE |
139 | int ret = stmp_reset_block(i2c->regs); |
140 | if (ret) | |
141 | return ret; | |
cd4f2d4a | 142 | |
626f0a2f MV |
143 | /* |
144 | * Configure timing for the I2C block. The I2C TIMING2 register has to | |
145 | * be programmed with this particular magic number. The rest is derived | |
146 | * from the XTAL speed and requested I2C speed. | |
147 | * | |
148 | * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4]. | |
149 | */ | |
150 | writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0); | |
151 | writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1); | |
869c6a3e | 152 | writel(i2c->timing2, i2c->regs + MXS_I2C_TIMING2); |
cd4f2d4a | 153 | |
a8da7fec | 154 | writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); |
63151c53 FE |
155 | |
156 | return 0; | |
a8da7fec WS |
157 | } |
158 | ||
62885f59 MV |
159 | static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c) |
160 | { | |
161 | if (i2c->dma_read) { | |
162 | dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE); | |
163 | dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE); | |
164 | } else { | |
165 | dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE); | |
166 | } | |
167 | } | |
168 | ||
169 | static void mxs_i2c_dma_irq_callback(void *param) | |
170 | { | |
171 | struct mxs_i2c_dev *i2c = param; | |
172 | ||
173 | complete(&i2c->cmd_complete); | |
174 | mxs_i2c_dma_finish(i2c); | |
175 | } | |
176 | ||
177 | static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap, | |
178 | struct i2c_msg *msg, uint32_t flags) | |
179 | { | |
180 | struct dma_async_tx_descriptor *desc; | |
181 | struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap); | |
182 | ||
183 | if (msg->flags & I2C_M_RD) { | |
184 | i2c->dma_read = 1; | |
185 | i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_READ; | |
186 | ||
187 | /* | |
188 | * SELECT command. | |
189 | */ | |
190 | ||
191 | /* Queue the PIO register write transfer. */ | |
192 | i2c->pio_data[0] = MXS_CMD_I2C_SELECT; | |
193 | desc = dmaengine_prep_slave_sg(i2c->dmach, | |
194 | (struct scatterlist *)&i2c->pio_data[0], | |
195 | 1, DMA_TRANS_NONE, 0); | |
196 | if (!desc) { | |
197 | dev_err(i2c->dev, | |
198 | "Failed to get PIO reg. write descriptor.\n"); | |
199 | goto select_init_pio_fail; | |
200 | } | |
201 | ||
202 | /* Queue the DMA data transfer. */ | |
203 | sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1); | |
204 | dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE); | |
205 | desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1, | |
206 | DMA_MEM_TO_DEV, | |
207 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
208 | if (!desc) { | |
209 | dev_err(i2c->dev, | |
210 | "Failed to get DMA data write descriptor.\n"); | |
211 | goto select_init_dma_fail; | |
212 | } | |
213 | ||
214 | /* | |
215 | * READ command. | |
216 | */ | |
217 | ||
218 | /* Queue the PIO register write transfer. */ | |
219 | i2c->pio_data[1] = flags | MXS_CMD_I2C_READ | | |
220 | MXS_I2C_CTRL0_XFER_COUNT(msg->len); | |
221 | desc = dmaengine_prep_slave_sg(i2c->dmach, | |
222 | (struct scatterlist *)&i2c->pio_data[1], | |
223 | 1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT); | |
224 | if (!desc) { | |
225 | dev_err(i2c->dev, | |
226 | "Failed to get PIO reg. write descriptor.\n"); | |
227 | goto select_init_dma_fail; | |
228 | } | |
229 | ||
230 | /* Queue the DMA data transfer. */ | |
231 | sg_init_one(&i2c->sg_io[1], msg->buf, msg->len); | |
232 | dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE); | |
233 | desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1, | |
234 | DMA_DEV_TO_MEM, | |
235 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
236 | if (!desc) { | |
237 | dev_err(i2c->dev, | |
238 | "Failed to get DMA data write descriptor.\n"); | |
239 | goto read_init_dma_fail; | |
240 | } | |
241 | } else { | |
242 | i2c->dma_read = 0; | |
243 | i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_WRITE; | |
244 | ||
245 | /* | |
246 | * WRITE command. | |
247 | */ | |
248 | ||
249 | /* Queue the PIO register write transfer. */ | |
250 | i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE | | |
251 | MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1); | |
252 | desc = dmaengine_prep_slave_sg(i2c->dmach, | |
253 | (struct scatterlist *)&i2c->pio_data[0], | |
254 | 1, DMA_TRANS_NONE, 0); | |
255 | if (!desc) { | |
256 | dev_err(i2c->dev, | |
257 | "Failed to get PIO reg. write descriptor.\n"); | |
258 | goto write_init_pio_fail; | |
259 | } | |
260 | ||
261 | /* Queue the DMA data transfer. */ | |
262 | sg_init_table(i2c->sg_io, 2); | |
263 | sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1); | |
264 | sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len); | |
265 | dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE); | |
266 | desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2, | |
267 | DMA_MEM_TO_DEV, | |
268 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
269 | if (!desc) { | |
270 | dev_err(i2c->dev, | |
271 | "Failed to get DMA data write descriptor.\n"); | |
272 | goto write_init_dma_fail; | |
273 | } | |
274 | } | |
275 | ||
276 | /* | |
277 | * The last descriptor must have this callback, | |
278 | * to finish the DMA transaction. | |
279 | */ | |
280 | desc->callback = mxs_i2c_dma_irq_callback; | |
281 | desc->callback_param = i2c; | |
282 | ||
283 | /* Start the transfer. */ | |
284 | dmaengine_submit(desc); | |
285 | dma_async_issue_pending(i2c->dmach); | |
286 | return 0; | |
287 | ||
288 | /* Read failpath. */ | |
289 | read_init_dma_fail: | |
290 | dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE); | |
291 | select_init_dma_fail: | |
292 | dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE); | |
293 | select_init_pio_fail: | |
c35d3cfd | 294 | dmaengine_terminate_all(i2c->dmach); |
62885f59 MV |
295 | return -EINVAL; |
296 | ||
297 | /* Write failpath. */ | |
298 | write_init_dma_fail: | |
299 | dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE); | |
300 | write_init_pio_fail: | |
c35d3cfd | 301 | dmaengine_terminate_all(i2c->dmach); |
62885f59 MV |
302 | return -EINVAL; |
303 | } | |
304 | ||
29faeb38 | 305 | static int mxs_i2c_pio_wait_xfer_end(struct mxs_i2c_dev *i2c) |
fc91e401 MV |
306 | { |
307 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); | |
308 | ||
29faeb38 | 309 | while (readl(i2c->regs + MXS_I2C_CTRL0) & MXS_I2C_CTRL0_RUN) { |
535ebd21 LS |
310 | if (time_after(jiffies, timeout)) |
311 | return -ETIMEDOUT; | |
312 | cond_resched(); | |
313 | } | |
314 | ||
fc91e401 MV |
315 | return 0; |
316 | } | |
317 | ||
92b775c2 LS |
318 | static int mxs_i2c_pio_check_error_state(struct mxs_i2c_dev *i2c) |
319 | { | |
320 | u32 state; | |
321 | ||
322 | state = readl(i2c->regs + MXS_I2C_CTRL1_CLR) & MXS_I2C_IRQ_MASK; | |
323 | ||
324 | if (state & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ) | |
325 | i2c->cmd_err = -ENXIO; | |
326 | else if (state & (MXS_I2C_CTRL1_EARLY_TERM_IRQ | | |
327 | MXS_I2C_CTRL1_MASTER_LOSS_IRQ | | |
328 | MXS_I2C_CTRL1_SLAVE_STOP_IRQ | | |
329 | MXS_I2C_CTRL1_SLAVE_IRQ)) | |
330 | i2c->cmd_err = -EIO; | |
331 | ||
332 | return i2c->cmd_err; | |
333 | } | |
334 | ||
535ebd21 LS |
335 | static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd) |
336 | { | |
337 | u32 reg; | |
338 | ||
339 | writel(cmd, i2c->regs + MXS_I2C_CTRL0); | |
340 | ||
341 | /* readback makes sure the write is latched into hardware */ | |
342 | reg = readl(i2c->regs + MXS_I2C_CTRL0); | |
343 | reg |= MXS_I2C_CTRL0_RUN; | |
344 | writel(reg, i2c->regs + MXS_I2C_CTRL0); | |
345 | } | |
346 | ||
29faeb38 MV |
347 | /* |
348 | * Start WRITE transaction on the I2C bus. By studying i.MX23 datasheet, | |
349 | * CTRL0::PIO_MODE bit description clarifies the order in which the registers | |
350 | * must be written during PIO mode operation. First, the CTRL0 register has | |
351 | * to be programmed with all the necessary bits but the RUN bit. Then the | |
352 | * payload has to be written into the DATA register. Finally, the transmission | |
353 | * is executed by setting the RUN bit in CTRL0. | |
354 | */ | |
355 | static void mxs_i2c_pio_trigger_write_cmd(struct mxs_i2c_dev *i2c, u32 cmd, | |
356 | u32 data) | |
357 | { | |
358 | writel(cmd, i2c->regs + MXS_I2C_CTRL0); | |
19e221be MV |
359 | |
360 | if (i2c->dev_type == MXS_I2C_V1) | |
361 | writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_SET); | |
362 | ||
363 | writel(data, i2c->regs + MXS_I2C_DATA(i2c)); | |
29faeb38 MV |
364 | writel(MXS_I2C_CTRL0_RUN, i2c->regs + MXS_I2C_CTRL0_SET); |
365 | } | |
366 | ||
fc91e401 MV |
367 | static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap, |
368 | struct i2c_msg *msg, uint32_t flags) | |
369 | { | |
370 | struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap); | |
371 | uint32_t addr_data = msg->addr << 1; | |
372 | uint32_t data = 0; | |
29faeb38 MV |
373 | int i, ret, xlen = 0, xmit = 0; |
374 | uint32_t start; | |
fc91e401 MV |
375 | |
376 | /* Mute IRQs coming from this block. */ | |
377 | writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR); | |
378 | ||
29faeb38 MV |
379 | /* |
380 | * MX23 idea: | |
381 | * - Enable CTRL0::PIO_MODE (1 << 24) | |
382 | * - Enable CTRL1::ACK_MODE (1 << 27) | |
383 | * | |
384 | * WARNING! The MX23 is broken in some way, even if it claims | |
385 | * to support PIO, when we try to transfer any amount of data | |
386 | * that is not aligned to 4 bytes, the DMA engine will have | |
387 | * bits in DEBUG1::DMA_BYTES_ENABLES still set even after the | |
388 | * transfer. This in turn will mess up the next transfer as | |
389 | * the block it emit one byte write onto the bus terminated | |
390 | * with a NAK+STOP. A possible workaround is to reset the IP | |
391 | * block after every PIO transmission, which might just work. | |
392 | * | |
393 | * NOTE: The CTRL0::PIO_MODE description is important, since | |
394 | * it outlines how the PIO mode is really supposed to work. | |
395 | */ | |
fc91e401 | 396 | if (msg->flags & I2C_M_RD) { |
29faeb38 MV |
397 | /* |
398 | * PIO READ transfer: | |
399 | * | |
400 | * This transfer MUST be limited to 4 bytes maximum. It is not | |
401 | * possible to transfer more than four bytes via PIO, since we | |
402 | * can not in any way make sure we can read the data from the | |
403 | * DATA register fast enough. Besides, the RX FIFO is only four | |
404 | * bytes deep, thus we can only really read up to four bytes at | |
405 | * time. Finally, there is no bit indicating us that new data | |
406 | * arrived at the FIFO and can thus be fetched from the DATA | |
407 | * register. | |
408 | */ | |
409 | BUG_ON(msg->len > 4); | |
410 | ||
fc91e401 MV |
411 | addr_data |= I2C_SMBUS_READ; |
412 | ||
413 | /* SELECT command. */ | |
29faeb38 MV |
414 | mxs_i2c_pio_trigger_write_cmd(i2c, MXS_CMD_I2C_SELECT, |
415 | addr_data); | |
fc91e401 | 416 | |
29faeb38 MV |
417 | ret = mxs_i2c_pio_wait_xfer_end(i2c); |
418 | if (ret) { | |
419 | dev_err(i2c->dev, | |
420 | "PIO: Failed to send SELECT command!\n"); | |
92b775c2 | 421 | goto cleanup; |
29faeb38 | 422 | } |
92b775c2 | 423 | |
fc91e401 | 424 | /* READ command. */ |
535ebd21 LS |
425 | mxs_i2c_pio_trigger_cmd(i2c, |
426 | MXS_CMD_I2C_READ | flags | | |
427 | MXS_I2C_CTRL0_XFER_COUNT(msg->len)); | |
fc91e401 | 428 | |
29faeb38 MV |
429 | ret = mxs_i2c_pio_wait_xfer_end(i2c); |
430 | if (ret) { | |
431 | dev_err(i2c->dev, | |
432 | "PIO: Failed to send SELECT command!\n"); | |
433 | goto cleanup; | |
434 | } | |
435 | ||
19e221be | 436 | data = readl(i2c->regs + MXS_I2C_DATA(i2c)); |
fc91e401 | 437 | for (i = 0; i < msg->len; i++) { |
fc91e401 MV |
438 | msg->buf[i] = data & 0xff; |
439 | data >>= 8; | |
440 | } | |
441 | } else { | |
29faeb38 MV |
442 | /* |
443 | * PIO WRITE transfer: | |
444 | * | |
445 | * The code below implements clock stretching to circumvent | |
446 | * the possibility of kernel not being able to supply data | |
447 | * fast enough. It is possible to transfer arbitrary amount | |
448 | * of data using PIO write. | |
449 | */ | |
fc91e401 MV |
450 | addr_data |= I2C_SMBUS_WRITE; |
451 | ||
fc91e401 MV |
452 | /* |
453 | * The LSB of data buffer is the first byte blasted across | |
454 | * the bus. Higher order bytes follow. Thus the following | |
455 | * filling schematic. | |
456 | */ | |
29faeb38 | 457 | |
fc91e401 | 458 | data = addr_data << 24; |
29faeb38 MV |
459 | |
460 | /* Start the transfer with START condition. */ | |
461 | start = MXS_I2C_CTRL0_PRE_SEND_START; | |
462 | ||
463 | /* If the transfer is long, use clock stretching. */ | |
464 | if (msg->len > 3) | |
465 | start |= MXS_I2C_CTRL0_RETAIN_CLOCK; | |
466 | ||
fc91e401 MV |
467 | for (i = 0; i < msg->len; i++) { |
468 | data >>= 8; | |
469 | data |= (msg->buf[i] << 24); | |
29faeb38 MV |
470 | |
471 | xmit = 0; | |
472 | ||
473 | /* This is the last transfer of the message. */ | |
474 | if (i + 1 == msg->len) { | |
475 | /* Add optional STOP flag. */ | |
476 | start |= flags; | |
477 | /* Remove RETAIN_CLOCK bit. */ | |
478 | start &= ~MXS_I2C_CTRL0_RETAIN_CLOCK; | |
479 | xmit = 1; | |
fc91e401 | 480 | } |
fc91e401 | 481 | |
29faeb38 MV |
482 | /* Four bytes are ready in the "data" variable. */ |
483 | if ((i & 3) == 2) | |
484 | xmit = 1; | |
485 | ||
486 | /* Nothing interesting happened, continue stuffing. */ | |
487 | if (!xmit) | |
488 | continue; | |
489 | ||
490 | /* | |
491 | * Compute the size of the transfer and shift the | |
492 | * data accordingly. | |
493 | * | |
494 | * i = (4k + 0) .... xlen = 2 | |
495 | * i = (4k + 1) .... xlen = 3 | |
496 | * i = (4k + 2) .... xlen = 4 | |
497 | * i = (4k + 3) .... xlen = 1 | |
498 | */ | |
499 | ||
500 | if ((i % 4) == 3) | |
501 | xlen = 1; | |
502 | else | |
503 | xlen = (i % 4) + 2; | |
504 | ||
505 | data >>= (4 - xlen) * 8; | |
506 | ||
507 | dev_dbg(i2c->dev, | |
508 | "PIO: len=%i pos=%i total=%i [W%s%s%s]\n", | |
509 | xlen, i, msg->len, | |
510 | start & MXS_I2C_CTRL0_PRE_SEND_START ? "S" : "", | |
511 | start & MXS_I2C_CTRL0_POST_SEND_STOP ? "E" : "", | |
512 | start & MXS_I2C_CTRL0_RETAIN_CLOCK ? "C" : ""); | |
513 | ||
535ebd21 | 514 | writel(MXS_I2C_DEBUG0_DMAREQ, |
19e221be | 515 | i2c->regs + MXS_I2C_DEBUG0_CLR(i2c)); |
29faeb38 MV |
516 | |
517 | mxs_i2c_pio_trigger_write_cmd(i2c, | |
518 | start | MXS_I2C_CTRL0_MASTER_MODE | | |
519 | MXS_I2C_CTRL0_DIRECTION | | |
520 | MXS_I2C_CTRL0_XFER_COUNT(xlen), data); | |
521 | ||
522 | /* The START condition is sent only once. */ | |
523 | start &= ~MXS_I2C_CTRL0_PRE_SEND_START; | |
524 | ||
525 | /* Wait for the end of the transfer. */ | |
526 | ret = mxs_i2c_pio_wait_xfer_end(i2c); | |
527 | if (ret) { | |
528 | dev_err(i2c->dev, | |
529 | "PIO: Failed to finish WRITE cmd!\n"); | |
530 | break; | |
531 | } | |
532 | ||
533 | /* Check NAK here. */ | |
534 | ret = readl(i2c->regs + MXS_I2C_STAT) & | |
535 | MXS_I2C_STAT_GOT_A_NAK; | |
536 | if (ret) { | |
537 | ret = -ENXIO; | |
538 | goto cleanup; | |
539 | } | |
fc91e401 MV |
540 | } |
541 | } | |
542 | ||
92b775c2 | 543 | /* make sure we capture any occurred error into cmd_err */ |
29faeb38 | 544 | ret = mxs_i2c_pio_check_error_state(i2c); |
92b775c2 LS |
545 | |
546 | cleanup: | |
fc91e401 MV |
547 | /* Clear any dangling IRQs and re-enable interrupts. */ |
548 | writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR); | |
549 | writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); | |
550 | ||
19e221be MV |
551 | /* Clear the PIO_MODE on i.MX23 */ |
552 | if (i2c->dev_type == MXS_I2C_V1) | |
553 | writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_CLR); | |
554 | ||
29faeb38 | 555 | return ret; |
fc91e401 MV |
556 | } |
557 | ||
a8da7fec WS |
558 | /* |
559 | * Low level master read/write transaction. | |
560 | */ | |
561 | static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, | |
562 | int stop) | |
563 | { | |
564 | struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap); | |
29faeb38 | 565 | int ret; |
a8da7fec | 566 | int flags; |
29faeb38 | 567 | int use_pio = 0; |
a8da7fec | 568 | |
62885f59 MV |
569 | flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0; |
570 | ||
a8da7fec WS |
571 | dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", |
572 | msg->addr, msg->len, msg->flags, stop); | |
573 | ||
574 | if (msg->len == 0) | |
575 | return -EINVAL; | |
576 | ||
fc91e401 | 577 | /* |
29faeb38 MV |
578 | * The MX28 I2C IP block can only do PIO READ for transfer of to up |
579 | * 4 bytes of length. The write transfer is not limited as it can use | |
580 | * clock stretching to avoid FIFO underruns. | |
fc91e401 | 581 | */ |
29faeb38 MV |
582 | if ((msg->flags & I2C_M_RD) && (msg->len <= 4)) |
583 | use_pio = 1; | |
584 | if (!(msg->flags & I2C_M_RD) && (msg->len < 7)) | |
585 | use_pio = 1; | |
586 | ||
92b775c2 | 587 | i2c->cmd_err = 0; |
29faeb38 | 588 | if (use_pio) { |
fc91e401 | 589 | ret = mxs_i2c_pio_setup_xfer(adap, msg, flags); |
29faeb38 MV |
590 | /* No need to reset the block if NAK was received. */ |
591 | if (ret && (ret != -ENXIO)) | |
592 | mxs_i2c_reset(i2c); | |
fc91e401 | 593 | } else { |
16735d02 | 594 | reinit_completion(&i2c->cmd_complete); |
fc91e401 MV |
595 | ret = mxs_i2c_dma_setup_xfer(adap, msg, flags); |
596 | if (ret) | |
597 | return ret; | |
a8da7fec | 598 | |
fc91e401 | 599 | ret = wait_for_completion_timeout(&i2c->cmd_complete, |
a8da7fec | 600 | msecs_to_jiffies(1000)); |
fc91e401 MV |
601 | if (ret == 0) |
602 | goto timeout; | |
29faeb38 MV |
603 | |
604 | ret = i2c->cmd_err; | |
92b775c2 | 605 | } |
fc91e401 | 606 | |
29faeb38 | 607 | if (ret == -ENXIO) { |
92b775c2 LS |
608 | /* |
609 | * If the transfer fails with a NAK from the slave the | |
610 | * controller halts until it gets told to return to idle state. | |
611 | */ | |
612 | writel(MXS_I2C_CTRL1_CLR_GOT_A_NAK, | |
613 | i2c->regs + MXS_I2C_CTRL1_SET); | |
fc91e401 | 614 | } |
a8da7fec | 615 | |
19e221be MV |
616 | /* |
617 | * WARNING! | |
618 | * The i.MX23 is strange. After each and every operation, it's I2C IP | |
619 | * block must be reset, otherwise the IP block will misbehave. This can | |
620 | * be observed on the bus by the block sending out one single byte onto | |
621 | * the bus. In case such an error happens, bit 27 will be set in the | |
622 | * DEBUG0 register. This bit is not documented in the i.MX23 datasheet | |
623 | * and is marked as "TBD" instead. To reset this bit to a correct state, | |
624 | * reset the whole block. Since the block reset does not take long, do | |
625 | * reset the block after every transfer to play safe. | |
626 | */ | |
627 | if (i2c->dev_type == MXS_I2C_V1) | |
628 | mxs_i2c_reset(i2c); | |
92b775c2 | 629 | |
fc91e401 | 630 | dev_dbg(i2c->dev, "Done with err=%d\n", ret); |
a8da7fec | 631 | |
fc91e401 | 632 | return ret; |
a8da7fec WS |
633 | |
634 | timeout: | |
635 | dev_dbg(i2c->dev, "Timeout!\n"); | |
82fa63bd | 636 | mxs_i2c_dma_finish(i2c); |
63151c53 FE |
637 | ret = mxs_i2c_reset(i2c); |
638 | if (ret) | |
639 | return ret; | |
640 | ||
a8da7fec WS |
641 | return -ETIMEDOUT; |
642 | } | |
643 | ||
644 | static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], | |
645 | int num) | |
646 | { | |
647 | int i; | |
648 | int err; | |
649 | ||
650 | for (i = 0; i < num; i++) { | |
651 | err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1)); | |
652 | if (err) | |
653 | return err; | |
654 | } | |
655 | ||
656 | return num; | |
657 | } | |
658 | ||
659 | static u32 mxs_i2c_func(struct i2c_adapter *adap) | |
660 | { | |
8f414059 | 661 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
a8da7fec WS |
662 | } |
663 | ||
664 | static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id) | |
665 | { | |
666 | struct mxs_i2c_dev *i2c = dev_id; | |
667 | u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK; | |
668 | ||
669 | if (!stat) | |
670 | return IRQ_NONE; | |
671 | ||
672 | if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ) | |
673 | i2c->cmd_err = -ENXIO; | |
674 | else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ | | |
675 | MXS_I2C_CTRL1_MASTER_LOSS_IRQ | | |
676 | MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ)) | |
677 | /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */ | |
678 | i2c->cmd_err = -EIO; | |
a8da7fec | 679 | |
a8da7fec | 680 | writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR); |
844990da | 681 | |
a8da7fec WS |
682 | return IRQ_HANDLED; |
683 | } | |
684 | ||
685 | static const struct i2c_algorithm mxs_i2c_algo = { | |
686 | .master_xfer = mxs_i2c_xfer, | |
687 | .functionality = mxs_i2c_func, | |
688 | }; | |
689 | ||
869c6a3e | 690 | static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, uint32_t speed) |
626f0a2f | 691 | { |
869c6a3e | 692 | /* The I2C block clock runs at 24MHz */ |
626f0a2f | 693 | const uint32_t clk = 24000000; |
869c6a3e | 694 | uint32_t divider; |
626f0a2f | 695 | uint16_t high_count, low_count, rcv_count, xmit_count; |
869c6a3e | 696 | uint32_t bus_free, leadin; |
626f0a2f MV |
697 | struct device *dev = i2c->dev; |
698 | ||
869c6a3e LW |
699 | divider = DIV_ROUND_UP(clk, speed); |
700 | ||
701 | if (divider < 25) { | |
702 | /* | |
703 | * limit the divider, so that min(low_count, high_count) | |
704 | * is >= 1 | |
705 | */ | |
706 | divider = 25; | |
707 | dev_warn(dev, | |
708 | "Speed too high (%u.%03u kHz), using %u.%03u kHz\n", | |
709 | speed / 1000, speed % 1000, | |
710 | clk / divider / 1000, clk / divider % 1000); | |
711 | } else if (divider > 1897) { | |
712 | /* | |
713 | * limit the divider, so that max(low_count, high_count) | |
714 | * cannot exceed 1023 | |
715 | */ | |
716 | divider = 1897; | |
717 | dev_warn(dev, | |
718 | "Speed too low (%u.%03u kHz), using %u.%03u kHz\n", | |
719 | speed / 1000, speed % 1000, | |
720 | clk / divider / 1000, clk / divider % 1000); | |
626f0a2f MV |
721 | } |
722 | ||
723 | /* | |
869c6a3e LW |
724 | * The I2C spec specifies the following timing data: |
725 | * standard mode fast mode Bitfield name | |
726 | * tLOW (SCL LOW period) 4700 ns 1300 ns | |
727 | * tHIGH (SCL HIGH period) 4000 ns 600 ns | |
728 | * tSU;DAT (data setup time) 250 ns 100 ns | |
729 | * tHD;STA (START hold time) 4000 ns 600 ns | |
730 | * tBUF (bus free time) 4700 ns 1300 ns | |
626f0a2f | 731 | * |
869c6a3e LW |
732 | * The hardware (of the i.MX28 at least) seems to add 2 additional |
733 | * clock cycles to the low_count and 7 cycles to the high_count. | |
734 | * This is compensated for by subtracting the respective constants | |
735 | * from the values written to the timing registers. | |
626f0a2f | 736 | */ |
869c6a3e LW |
737 | if (speed > 100000) { |
738 | /* fast mode */ | |
739 | low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6)); | |
740 | high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6)); | |
741 | leadin = DIV_ROUND_UP(600 * (clk / 1000000), 1000); | |
742 | bus_free = DIV_ROUND_UP(1300 * (clk / 1000000), 1000); | |
743 | } else { | |
744 | /* normal mode */ | |
745 | low_count = DIV_ROUND_CLOSEST(divider * 47, (47 + 40)); | |
746 | high_count = DIV_ROUND_CLOSEST(divider * 40, (47 + 40)); | |
747 | leadin = DIV_ROUND_UP(4700 * (clk / 1000000), 1000); | |
748 | bus_free = DIV_ROUND_UP(4700 * (clk / 1000000), 1000); | |
749 | } | |
750 | rcv_count = high_count * 3 / 8; | |
751 | xmit_count = low_count * 3 / 8; | |
752 | ||
753 | dev_dbg(dev, | |
754 | "speed=%u(actual %u) divider=%u low=%u high=%u xmit=%u rcv=%u leadin=%u bus_free=%u\n", | |
755 | speed, clk / divider, divider, low_count, high_count, | |
756 | xmit_count, rcv_count, leadin, bus_free); | |
626f0a2f | 757 | |
869c6a3e LW |
758 | low_count -= 2; |
759 | high_count -= 7; | |
626f0a2f MV |
760 | i2c->timing0 = (high_count << 16) | rcv_count; |
761 | i2c->timing1 = (low_count << 16) | xmit_count; | |
869c6a3e | 762 | i2c->timing2 = (bus_free << 16 | leadin); |
626f0a2f MV |
763 | } |
764 | ||
cd4f2d4a MV |
765 | static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c) |
766 | { | |
767 | uint32_t speed; | |
768 | struct device *dev = i2c->dev; | |
769 | struct device_node *node = dev->of_node; | |
770 | int ret; | |
771 | ||
cd4f2d4a | 772 | ret = of_property_read_u32(node, "clock-frequency", &speed); |
626f0a2f | 773 | if (ret) { |
cd4f2d4a | 774 | dev_warn(dev, "No I2C speed selected, using 100kHz\n"); |
626f0a2f MV |
775 | speed = 100000; |
776 | } | |
777 | ||
778 | mxs_i2c_derive_timing(i2c, speed); | |
cd4f2d4a MV |
779 | |
780 | return 0; | |
781 | } | |
782 | ||
616228a1 JB |
783 | static struct platform_device_id mxs_i2c_devtype[] = { |
784 | { | |
785 | .name = "imx23-i2c", | |
786 | .driver_data = MXS_I2C_V1, | |
787 | }, { | |
788 | .name = "imx28-i2c", | |
789 | .driver_data = MXS_I2C_V2, | |
790 | }, { /* sentinel */ } | |
791 | }; | |
792 | MODULE_DEVICE_TABLE(platform, mxs_i2c_devtype); | |
793 | ||
794 | static const struct of_device_id mxs_i2c_dt_ids[] = { | |
795 | { .compatible = "fsl,imx23-i2c", .data = &mxs_i2c_devtype[0], }, | |
796 | { .compatible = "fsl,imx28-i2c", .data = &mxs_i2c_devtype[1], }, | |
797 | { /* sentinel */ } | |
798 | }; | |
799 | MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids); | |
800 | ||
0b255e92 | 801 | static int mxs_i2c_probe(struct platform_device *pdev) |
a8da7fec | 802 | { |
616228a1 JB |
803 | const struct of_device_id *of_id = |
804 | of_match_device(mxs_i2c_dt_ids, &pdev->dev); | |
a8da7fec WS |
805 | struct device *dev = &pdev->dev; |
806 | struct mxs_i2c_dev *i2c; | |
807 | struct i2c_adapter *adap; | |
808 | struct resource *res; | |
809 | resource_size_t res_size; | |
e5aba13d | 810 | int err, irq; |
a8da7fec WS |
811 | |
812 | i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL); | |
813 | if (!i2c) | |
814 | return -ENOMEM; | |
815 | ||
616228a1 JB |
816 | if (of_id) { |
817 | const struct platform_device_id *device_id = of_id->data; | |
818 | i2c->dev_type = device_id->driver_data; | |
819 | } | |
820 | ||
a8da7fec | 821 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
62885f59 | 822 | irq = platform_get_irq(pdev, 0); |
62885f59 | 823 | |
e5aba13d | 824 | if (!res || irq < 0) |
a8da7fec WS |
825 | return -ENOENT; |
826 | ||
827 | res_size = resource_size(res); | |
828 | if (!devm_request_mem_region(dev, res->start, res_size, res->name)) | |
829 | return -EBUSY; | |
830 | ||
831 | i2c->regs = devm_ioremap_nocache(dev, res->start, res_size); | |
832 | if (!i2c->regs) | |
833 | return -EBUSY; | |
834 | ||
a8da7fec WS |
835 | err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c); |
836 | if (err) | |
837 | return err; | |
838 | ||
839 | i2c->dev = dev; | |
cd4f2d4a | 840 | |
85de7fac MV |
841 | init_completion(&i2c->cmd_complete); |
842 | ||
72ee734a WS |
843 | if (dev->of_node) { |
844 | err = mxs_i2c_get_ofdata(i2c); | |
845 | if (err) | |
846 | return err; | |
847 | } | |
cd4f2d4a | 848 | |
62885f59 | 849 | /* Setup the DMA */ |
e5aba13d | 850 | i2c->dmach = dma_request_slave_channel(dev, "rx-tx"); |
82fa63bd WS |
851 | if (!i2c->dmach) { |
852 | dev_err(dev, "Failed to request dma\n"); | |
853 | return -ENODEV; | |
62885f59 MV |
854 | } |
855 | ||
a8da7fec WS |
856 | platform_set_drvdata(pdev, i2c); |
857 | ||
858 | /* Do reset to enforce correct startup after pinmuxing */ | |
63151c53 FE |
859 | err = mxs_i2c_reset(i2c); |
860 | if (err) | |
861 | return err; | |
a8da7fec WS |
862 | |
863 | adap = &i2c->adapter; | |
864 | strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name)); | |
865 | adap->owner = THIS_MODULE; | |
866 | adap->algo = &mxs_i2c_algo; | |
867 | adap->dev.parent = dev; | |
868 | adap->nr = pdev->id; | |
b2378668 | 869 | adap->dev.of_node = pdev->dev.of_node; |
a8da7fec WS |
870 | i2c_set_adapdata(adap, i2c); |
871 | err = i2c_add_numbered_adapter(adap); | |
872 | if (err) { | |
873 | dev_err(dev, "Failed to add adapter (%d)\n", err); | |
874 | writel(MXS_I2C_CTRL0_SFTRST, | |
875 | i2c->regs + MXS_I2C_CTRL0_SET); | |
876 | return err; | |
877 | } | |
878 | ||
879 | return 0; | |
880 | } | |
881 | ||
0b255e92 | 882 | static int mxs_i2c_remove(struct platform_device *pdev) |
a8da7fec WS |
883 | { |
884 | struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev); | |
a8da7fec | 885 | |
bf51a8c5 | 886 | i2c_del_adapter(&i2c->adapter); |
a8da7fec | 887 | |
62885f59 MV |
888 | if (i2c->dmach) |
889 | dma_release_channel(i2c->dmach); | |
890 | ||
a8da7fec WS |
891 | writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET); |
892 | ||
a8da7fec WS |
893 | return 0; |
894 | } | |
895 | ||
896 | static struct platform_driver mxs_i2c_driver = { | |
897 | .driver = { | |
898 | .name = DRIVER_NAME, | |
899 | .owner = THIS_MODULE, | |
b2378668 | 900 | .of_match_table = mxs_i2c_dt_ids, |
a8da7fec | 901 | }, |
cc40bf9a | 902 | .probe = mxs_i2c_probe, |
0b255e92 | 903 | .remove = mxs_i2c_remove, |
a8da7fec WS |
904 | }; |
905 | ||
906 | static int __init mxs_i2c_init(void) | |
907 | { | |
cc40bf9a | 908 | return platform_driver_register(&mxs_i2c_driver); |
a8da7fec WS |
909 | } |
910 | subsys_initcall(mxs_i2c_init); | |
911 | ||
912 | static void __exit mxs_i2c_exit(void) | |
913 | { | |
914 | platform_driver_unregister(&mxs_i2c_driver); | |
915 | } | |
916 | module_exit(mxs_i2c_exit); | |
917 | ||
29faeb38 | 918 | MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); |
a8da7fec WS |
919 | MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); |
920 | MODULE_DESCRIPTION("MXS I2C Bus Driver"); | |
921 | MODULE_LICENSE("GPL"); | |
922 | MODULE_ALIAS("platform:" DRIVER_NAME); |