[deliverable/linux.git] / drivers / i2c / busses / i2c-ocores.c

/*
 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
 * (http://www.opencores.org/projects.cgi/web/i2c/overview).
 *
 * Peter Korsgaard <jacmet@sunsite.dk>
 *
 * Support for the GRLIB port of the controller by
 * Andreas Larsson <andreas@gaisler.com>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/i2c-ocores.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/log2.h>

struct ocores_i2c {
	void __iomem *base;
	u32 reg_shift;
	u32 reg_io_width;
	wait_queue_head_t wait;
	struct i2c_adapter adap;
	struct i2c_msg *msg;
	int pos;
	int nmsgs;
	int state; /* see STATE_ */
	int clock_khz;
	void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
	u8 (*getreg)(struct ocores_i2c *i2c, int reg);
};

/* registers */
#define OCI2C_PRELOW		0
#define OCI2C_PREHIGH		1
#define OCI2C_CONTROL		2
#define OCI2C_DATA		3
#define OCI2C_CMD		4 /* write only */
#define OCI2C_STATUS		4 /* read only, same address as OCI2C_CMD */

#define OCI2C_CTRL_IEN		0x40
#define OCI2C_CTRL_EN		0x80

#define OCI2C_CMD_START		0x91
#define OCI2C_CMD_STOP		0x41
#define OCI2C_CMD_READ		0x21
#define OCI2C_CMD_WRITE		0x11
#define OCI2C_CMD_READ_ACK	0x21
#define OCI2C_CMD_READ_NACK	0x29
#define OCI2C_CMD_IACK		0x01

#define OCI2C_STAT_IF		0x01
#define OCI2C_STAT_TIP		0x02
#define OCI2C_STAT_ARBLOST	0x20
#define OCI2C_STAT_BUSY		0x40
#define OCI2C_STAT_NACK		0x80

#define STATE_DONE		0
#define STATE_START		1
#define STATE_WRITE		2
#define STATE_READ		3
#define STATE_ERROR		4

#define TYPE_OCORES		0
#define TYPE_GRLIB		1

static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
{
	iowrite8(value, i2c->base + (reg << i2c->reg_shift));
}

static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
{
	iowrite16(value, i2c->base + (reg << i2c->reg_shift));
}

static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
{
	iowrite32(value, i2c->base + (reg << i2c->reg_shift));
}

static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
{
	return ioread8(i2c->base + (reg << i2c->reg_shift));
}

static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
{
	return ioread16(i2c->base + (reg << i2c->reg_shift));
}

static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
{
	return ioread32(i2c->base + (reg << i2c->reg_shift));
}

static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
{
	i2c->setreg(i2c, reg, value);
}

static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
{
	return i2c->getreg(i2c, reg);
}

static void ocores_process(struct ocores_i2c *i2c)
{
	struct i2c_msg *msg = i2c->msg;
	u8 stat = oc_getreg(i2c, OCI2C_STATUS);

	if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
		/* stop has been sent */
		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
		wake_up(&i2c->wait);
		return;
	}

	/* error? */
	if (stat & OCI2C_STAT_ARBLOST) {
		i2c->state = STATE_ERROR;
		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
		return;
	}

	if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
		i2c->state =
			(msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;

		if (stat & OCI2C_STAT_NACK) {
			i2c->state = STATE_ERROR;
			oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
			return;
		}
	} else
		msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);

	/* end of msg? */
	if (i2c->pos == msg->len) {
		i2c->nmsgs--;
		i2c->msg++;
		i2c->pos = 0;
		msg = i2c->msg;

		if (i2c->nmsgs) {	/* end? */
			/* send start? */
			if (!(msg->flags & I2C_M_NOSTART)) {
				u8 addr = (msg->addr << 1);

				if (msg->flags & I2C_M_RD)
					addr |= 1;

				i2c->state = STATE_START;

				oc_setreg(i2c, OCI2C_DATA, addr);
				oc_setreg(i2c, OCI2C_CMD,  OCI2C_CMD_START);
				return;
			} else
				i2c->state = (msg->flags & I2C_M_RD)
					? STATE_READ : STATE_WRITE;
		} else {
			i2c->state = STATE_DONE;
			oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
			return;
		}
	}

	if (i2c->state == STATE_READ) {
		oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
			  OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
	} else {
		oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
	}
}

static irqreturn_t ocores_isr(int irq, void *dev_id)
{
	struct ocores_i2c *i2c = dev_id;

	ocores_process(i2c);

	return IRQ_HANDLED;
}

static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
	struct ocores_i2c *i2c = i2c_get_adapdata(adap);

	i2c->msg = msgs;
	i2c->pos = 0;
	i2c->nmsgs = num;
	i2c->state = STATE_START;

	oc_setreg(i2c, OCI2C_DATA,
			(i2c->msg->addr << 1) |
			((i2c->msg->flags & I2C_M_RD) ? 1:0));

	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);

	if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
			       (i2c->state == STATE_DONE), HZ))
		return (i2c->state == STATE_DONE) ? num : -EIO;
	else
		return -ETIMEDOUT;
}

static void ocores_init(struct ocores_i2c *i2c)
{
	int prescale;
	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);

	/* make sure the device is disabled */
	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));

	prescale = (i2c->clock_khz / (5*100)) - 1;
	oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
	oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);

	/* Init the device */
	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
	oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);
}


static u32 ocores_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm ocores_algorithm = {
	.master_xfer	= ocores_xfer,
	.functionality	= ocores_func,
};

static struct i2c_adapter ocores_adapter = {
	.owner		= THIS_MODULE,
	.name		= "i2c-ocores",
	.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD | I2C_CLASS_DEPRECATED,
	.algo		= &ocores_algorithm,
};

static struct of_device_id ocores_i2c_match[] = {
	{
		.compatible = "opencores,i2c-ocores",
		.data = (void *)TYPE_OCORES,
	},
	{
		.compatible = "aeroflexgaisler,i2cmst",
		.data = (void *)TYPE_GRLIB,
	},
	{},
};
MODULE_DEVICE_TABLE(of, ocores_i2c_match);

#ifdef CONFIG_OF
/* Read and write functions for the GRLIB port of the controller. Registers are
 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
 * register. The subsequent registers has their offset decreased accordingly. */
static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
{
	u32 rd;
	int rreg = reg;
	if (reg != OCI2C_PRELOW)
		rreg--;
	rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
	if (reg == OCI2C_PREHIGH)
		return (u8)(rd >> 8);
	else
		return (u8)rd;
}

static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
{
	u32 curr, wr;
	int rreg = reg;
	if (reg != OCI2C_PRELOW)
		rreg--;
	if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
		curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
		if (reg == OCI2C_PRELOW)
			wr = (curr & 0xff00) | value;
		else
			wr = (((u32)value) << 8) | (curr & 0xff);
	} else {
		wr = value;
	}
	iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
}

static int ocores_i2c_of_probe(struct platform_device *pdev,
				struct ocores_i2c *i2c)
{
	struct device_node *np = pdev->dev.of_node;
	const struct of_device_id *match;
	u32 val;

	if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
		/* no 'reg-shift', check for deprecated 'regstep' */
		if (!of_property_read_u32(np, "regstep", &val)) {
			if (!is_power_of_2(val)) {
				dev_err(&pdev->dev, "invalid regstep %d\n",
					val);
				return -EINVAL;
			}
			i2c->reg_shift = ilog2(val);
			dev_warn(&pdev->dev,
				"regstep property deprecated, use reg-shift\n");
		}
	}

	if (of_property_read_u32(np, "clock-frequency", &val)) {
		dev_err(&pdev->dev,
			"Missing required parameter 'clock-frequency'\n");
		return -ENODEV;
	}
	i2c->clock_khz = val / 1000;

	of_property_read_u32(pdev->dev.of_node, "reg-io-width",
				&i2c->reg_io_width);

	match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
	if (match && (long)match->data == TYPE_GRLIB) {
		dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
		i2c->setreg = oc_setreg_grlib;
		i2c->getreg = oc_getreg_grlib;
	}

	return 0;
}
#else
#define ocores_i2c_of_probe(pdev,i2c) -ENODEV
#endif

static int ocores_i2c_probe(struct platform_device *pdev)
{
	struct ocores_i2c *i2c;
	struct ocores_i2c_platform_data *pdata;
	struct resource *res;
	int irq;
	int ret;
	int i;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
	if (!i2c)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	i2c->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(i2c->base))
		return PTR_ERR(i2c->base);

	pdata = dev_get_platdata(&pdev->dev);
	if (pdata) {
		i2c->reg_shift = pdata->reg_shift;
		i2c->reg_io_width = pdata->reg_io_width;
		i2c->clock_khz = pdata->clock_khz;
	} else {
		ret = ocores_i2c_of_probe(pdev, i2c);
		if (ret)
			return ret;
	}

	if (i2c->reg_io_width == 0)
		i2c->reg_io_width = 1; /* Set to default value */

	if (!i2c->setreg || !i2c->getreg) {
		switch (i2c->reg_io_width) {
		case 1:
			i2c->setreg = oc_setreg_8;
			i2c->getreg = oc_getreg_8;
			break;

		case 2:
			i2c->setreg = oc_setreg_16;
			i2c->getreg = oc_getreg_16;
			break;

		case 4:
			i2c->setreg = oc_setreg_32;
			i2c->getreg = oc_getreg_32;
			break;

		default:
			dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
				i2c->reg_io_width);
			return -EINVAL;
		}
	}

	ocores_init(i2c);

	init_waitqueue_head(&i2c->wait);
	ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
			       pdev->name, i2c);
	if (ret) {
		dev_err(&pdev->dev, "Cannot claim IRQ\n");
		return ret;
	}

	/* hook up driver to tree */
	platform_set_drvdata(pdev, i2c);
	i2c->adap = ocores_adapter;
	i2c_set_adapdata(&i2c->adap, i2c);
	i2c->adap.dev.parent = &pdev->dev;
	i2c->adap.dev.of_node = pdev->dev.of_node;

	/* add i2c adapter to i2c tree */
	ret = i2c_add_adapter(&i2c->adap);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add adapter\n");
		return ret;
	}

	/* add in known devices to the bus */
	if (pdata) {
		for (i = 0; i < pdata->num_devices; i++)
			i2c_new_device(&i2c->adap, pdata->devices + i);
	}

	return 0;
}

static int ocores_i2c_remove(struct platform_device *pdev)
{
	struct ocores_i2c *i2c = platform_get_drvdata(pdev);

	/* disable i2c logic */
	oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
		  & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));

	/* remove adapter & data */
	i2c_del_adapter(&i2c->adap);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int ocores_i2c_suspend(struct device *dev)
{
	struct ocores_i2c *i2c = dev_get_drvdata(dev);
	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);

	/* make sure the device is disabled */
	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));

	return 0;
}

static int ocores_i2c_resume(struct device *dev)
{
	struct ocores_i2c *i2c = dev_get_drvdata(dev);

	ocores_init(i2c);

	return 0;
}

static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
#define OCORES_I2C_PM	(&ocores_i2c_pm)
#else
#define OCORES_I2C_PM	NULL
#endif

static struct platform_driver ocores_i2c_driver = {
	.probe   = ocores_i2c_probe,
	.remove  = ocores_i2c_remove,
	.driver  = {
		.owner = THIS_MODULE,
		.name = "ocores-i2c",
		.of_match_table = ocores_i2c_match,
		.pm = OCORES_I2C_PM,
	},
};

module_platform_driver(ocores_i2c_driver);

MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
MODULE_DESCRIPTION("OpenCores I2C bus driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ocores-i2c");
Commit	Line	Data
18f98b1e PK	1	/*
	2	* i2c-ocores.c: I2C bus driver for OpenCores I2C controller
	3	* (http://www.opencores.org/projects.cgi/web/i2c/overview).
	4	*
	5	* Peter Korsgaard <jacmet@sunsite.dk>
	6	*
a000b8c1 AL	7	* Support for the GRLIB port of the controller by
	8	* Andreas Larsson <andreas@gaisler.com>
	9	*
18f98b1e PK	10	* This file is licensed under the terms of the GNU General Public License
	11	* version 2. This program is licensed "as is" without any warranty of any
	12	* kind, whether express or implied.
	13	*/
	14
84dbf809	15	#include <linux/err.h>
18f98b1e PK	16	#include <linux/kernel.h>
18f98b1e PK	17	#include <linux/module.h>
18f98b1e PK	18	#include <linux/errno.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/i2c.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/wait.h>
	23	#include <linux/i2c-ocores.h>
5a0e3ad6	24	#include <linux/slab.h>
21782180	25	#include <linux/io.h>
8bb986a8	26	#include <linux/log2.h>
18f98b1e PK	27
	28	struct ocores_i2c {
	29	void __iomem *base;
8bb986a8	30	u32 reg_shift;
7326e38f	31	u32 reg_io_width;
18f98b1e PK	32	wait_queue_head_t wait;
	33	struct i2c_adapter adap;
	34	struct i2c_msg *msg;
	35	int pos;
	36	int nmsgs;
	37	int state; /* see STATE_ */
2373c180	38	int clock_khz;
a000b8c1 AL	39	void (setreg)(struct ocores_i2c i2c, int reg, u8 value);
a000b8c1 AL	40	u8 (getreg)(struct ocores_i2c i2c, int reg);
18f98b1e PK	41	};
	42
	43	/* registers */
	44	#define OCI2C_PRELOW 0
	45	#define OCI2C_PREHIGH 1
	46	#define OCI2C_CONTROL 2
	47	#define OCI2C_DATA 3
1ded969f PK	48	#define OCI2C_CMD 4 /* write only */
1ded969f PK	49	#define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
18f98b1e PK	50
	51	#define OCI2C_CTRL_IEN 0x40
	52	#define OCI2C_CTRL_EN 0x80
	53
	54	#define OCI2C_CMD_START 0x91
	55	#define OCI2C_CMD_STOP 0x41
	56	#define OCI2C_CMD_READ 0x21
	57	#define OCI2C_CMD_WRITE 0x11
	58	#define OCI2C_CMD_READ_ACK 0x21
	59	#define OCI2C_CMD_READ_NACK 0x29
	60	#define OCI2C_CMD_IACK 0x01
	61
	62	#define OCI2C_STAT_IF 0x01
	63	#define OCI2C_STAT_TIP 0x02
	64	#define OCI2C_STAT_ARBLOST 0x20
	65	#define OCI2C_STAT_BUSY 0x40
	66	#define OCI2C_STAT_NACK 0x80
	67
	68	#define STATE_DONE 0
	69	#define STATE_START 1
	70	#define STATE_WRITE 2
	71	#define STATE_READ 3
	72	#define STATE_ERROR 4
	73
a000b8c1 AL	74	#define TYPE_OCORES 0
	75	#define TYPE_GRLIB 1
	76
	77	static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
18f98b1e	78	{
a000b8c1 AL	79	iowrite8(value, i2c->base + (reg << i2c->reg_shift));
	80	}
	81
	82	static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
	83	{
	84	iowrite16(value, i2c->base + (reg << i2c->reg_shift));
	85	}
	86
	87	static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
	88	{
	89	iowrite32(value, i2c->base + (reg << i2c->reg_shift));
	90	}
	91
	92	static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
	93	{
	94	return ioread8(i2c->base + (reg << i2c->reg_shift));
	95	}
	96
	97	static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
	98	{
	99	return ioread16(i2c->base + (reg << i2c->reg_shift));
	100	}
	101
	102	static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
	103	{
	104	return ioread32(i2c->base + (reg << i2c->reg_shift));
	105	}
	106
18f98b1e PK	107	static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
18f98b1e PK	108	{
a000b8c1	109	i2c->setreg(i2c, reg, value);
18f98b1e PK	110	}
	111
	112	static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
	113	{
a000b8c1	114	return i2c->getreg(i2c, reg);
18f98b1e PK	115	}
	116
	117	static void ocores_process(struct ocores_i2c *i2c)
	118	{
	119	struct i2c_msg *msg = i2c->msg;
	120	u8 stat = oc_getreg(i2c, OCI2C_STATUS);
	121
	122	if ((i2c->state == STATE_DONE) \|\| (i2c->state == STATE_ERROR)) {
	123	/* stop has been sent */
	124	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
	125	wake_up(&i2c->wait);
	126	return;
	127	}
	128
	129	/* error? */
	130	if (stat & OCI2C_STAT_ARBLOST) {
	131	i2c->state = STATE_ERROR;
	132	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
	133	return;
	134	}
	135
	136	if ((i2c->state == STATE_START) \|\| (i2c->state == STATE_WRITE)) {
	137	i2c->state =
	138	(msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
	139
	140	if (stat & OCI2C_STAT_NACK) {
	141	i2c->state = STATE_ERROR;
	142	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
	143	return;
	144	}
	145	} else
	146	msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
	147
	148	/* end of msg? */
	149	if (i2c->pos == msg->len) {
	150	i2c->nmsgs--;
	151	i2c->msg++;
	152	i2c->pos = 0;
	153	msg = i2c->msg;
	154
	155	if (i2c->nmsgs) { /* end? */
	156	/* send start? */
	157	if (!(msg->flags & I2C_M_NOSTART)) {
	158	u8 addr = (msg->addr << 1);
	159
	160	if (msg->flags & I2C_M_RD)
	161	addr \|= 1;
	162
	163	i2c->state = STATE_START;
	164
	165	oc_setreg(i2c, OCI2C_DATA, addr);
	166	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
	167	return;
	168	} else
	169	i2c->state = (msg->flags & I2C_M_RD)
	170	? STATE_READ : STATE_WRITE;
	171	} else {
	172	i2c->state = STATE_DONE;
	173	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
	174	return;
	175	}
	176	}
	177
	178	if (i2c->state == STATE_READ) {
179	oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
180	OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
181	} else {
182	oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
183	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
184	}
185	}
186
7d12e780	187	static irqreturn_t ocores_isr(int irq, void *dev_id)
18f98b1e PK	188	{
	189	struct ocores_i2c *i2c = dev_id;
	190
	191	ocores_process(i2c);
	192
	193	return IRQ_HANDLED;
	194	}
	195
	196	static int ocores_xfer(struct i2c_adapter adap, struct i2c_msg msgs, int num)
	197	{
	198	struct ocores_i2c *i2c = i2c_get_adapdata(adap);
	199
	200	i2c->msg = msgs;
	201	i2c->pos = 0;
	202	i2c->nmsgs = num;
	203	i2c->state = STATE_START;
	204
	205	oc_setreg(i2c, OCI2C_DATA,
	206	(i2c->msg->addr << 1) \|
	207	((i2c->msg->flags & I2C_M_RD) ? 1:0));
	208
	209	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
	210
	211	if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) \|\|
	212	(i2c->state == STATE_DONE), HZ))
	213	return (i2c->state == STATE_DONE) ? num : -EIO;
	214	else
	215	return -ETIMEDOUT;
	216	}
	217
2373c180	218	static void ocores_init(struct ocores_i2c *i2c)
18f98b1e PK	219	{
	220	int prescale;
	221	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
	222
	223	/* make sure the device is disabled */
	224	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN\|OCI2C_CTRL_IEN));
	225
2373c180	226	prescale = (i2c->clock_khz / (5*100)) - 1;
18f98b1e PK	227	oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
	228	oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
	229
	230	/* Init the device */
	231	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
	232	oc_setreg(i2c, OCI2C_CONTROL, ctrl \| OCI2C_CTRL_IEN \| OCI2C_CTRL_EN);
	233	}
	234
	235
	236	static u32 ocores_func(struct i2c_adapter *adap)
	237	{
	238	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	239	}
	240
8f9082c5	241	static const struct i2c_algorithm ocores_algorithm = {
18f98b1e PK	242	.master_xfer = ocores_xfer,
	243	.functionality = ocores_func,
	244	};
	245
	246	static struct i2c_adapter ocores_adapter = {
	247	.owner = THIS_MODULE,
	248	.name = "i2c-ocores",
878f00b0	249	.class = I2C_CLASS_HWMON \| I2C_CLASS_SPD \| I2C_CLASS_DEPRECATED,
18f98b1e	250	.algo = &ocores_algorithm,
18f98b1e PK	251	};
18f98b1e PK	252
a000b8c1 AL	253	static struct of_device_id ocores_i2c_match[] = {
	254	{
	255	.compatible = "opencores,i2c-ocores",
	256	.data = (void *)TYPE_OCORES,
	257	},
	258	{
	259	.compatible = "aeroflexgaisler,i2cmst",
	260	.data = (void *)TYPE_GRLIB,
	261	},
	262	{},
	263	};
	264	MODULE_DEVICE_TABLE(of, ocores_i2c_match);
	265
049bb69d	266	#ifdef CONFIG_OF
c5d54744 AL	267	/* Read and write functions for the GRLIB port of the controller. Registers are
	268	* 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
	269	* register. The subsequent registers has their offset decreased accordingly. */
	270	static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
	271	{
	272	u32 rd;
	273	int rreg = reg;
	274	if (reg != OCI2C_PRELOW)
	275	rreg--;
	276	rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
	277	if (reg == OCI2C_PREHIGH)
	278	return (u8)(rd >> 8);
	279	else
	280	return (u8)rd;
	281	}
	282
	283	static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
	284	{
	285	u32 curr, wr;
	286	int rreg = reg;
	287	if (reg != OCI2C_PRELOW)
	288	rreg--;
	289	if (reg == OCI2C_PRELOW \|\| reg == OCI2C_PREHIGH) {
	290	curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
	291	if (reg == OCI2C_PRELOW)
	292	wr = (curr & 0xff00) \| value;
	293	else
	294	wr = (((u32)value) << 8) \| (curr & 0xff);
	295	} else {
	296	wr = value;
	297	}
	298	iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
	299	}
	300
9ae97a89 J	301	static int ocores_i2c_of_probe(struct platform_device *pdev,
9ae97a89 J	302	struct ocores_i2c *i2c)
049bb69d	303	{
8bb986a8	304	struct device_node *np = pdev->dev.of_node;
a000b8c1	305	const struct of_device_id *match;
8bb986a8 GR	306	u32 val;
	307
	308	if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
	309	/* no 'reg-shift', check for deprecated 'regstep' */
	310	if (!of_property_read_u32(np, "regstep", &val)) {
	311	if (!is_power_of_2(val)) {
	312	dev_err(&pdev->dev, "invalid regstep %d\n",
	313	val);
	314	return -EINVAL;
	315	}
	316	i2c->reg_shift = ilog2(val);
	317	dev_warn(&pdev->dev,
	318	"regstep property deprecated, use reg-shift\n");
	319	}
049bb69d	320	}
049bb69d	321
8bb986a8	322	if (of_property_read_u32(np, "clock-frequency", &val)) {
049bb69d	323	dev_err(&pdev->dev,
9ae97a89	324	"Missing required parameter 'clock-frequency'\n");
049bb69d JB	325	return -ENODEV;
049bb69d JB	326	}
8bb986a8	327	i2c->clock_khz = val / 1000;
049bb69d	328
7326e38f GR	329	of_property_read_u32(pdev->dev.of_node, "reg-io-width",
7326e38f GR	330	&i2c->reg_io_width);
a000b8c1 AL	331
a000b8c1 AL	332	match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
6beaddf2	333	if (match && (long)match->data == TYPE_GRLIB) {
a000b8c1 AL	334	dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
	335	i2c->setreg = oc_setreg_grlib;
	336	i2c->getreg = oc_getreg_grlib;
	337	}
	338
049bb69d JB	339	return 0;
	340	}
	341	#else
	342	#define ocores_i2c_of_probe(pdev,i2c) -ENODEV
	343	#endif
18f98b1e	344
0b255e92	345	static int ocores_i2c_probe(struct platform_device *pdev)
18f98b1e PK	346	{
	347	struct ocores_i2c *i2c;
	348	struct ocores_i2c_platform_data *pdata;
f5f35a92 AL	349	struct resource *res;
f5f35a92 AL	350	int irq;
18f98b1e	351	int ret;
dd14be4c	352	int i;
18f98b1e	353
f5f35a92 AL	354	irq = platform_get_irq(pdev, 0);
	355	if (irq < 0)
	356	return irq;
18f98b1e	357
47def5b8	358	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
18f98b1e PK	359	if (!i2c)
	360	return -ENOMEM;
	361
b7d12a86	362	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
84dbf809 TR	363	i2c->base = devm_ioremap_resource(&pdev->dev, res);
	364	if (IS_ERR(i2c->base))
	365	return PTR_ERR(i2c->base);
18f98b1e	366
6d4028c6	367	pdata = dev_get_platdata(&pdev->dev);
049bb69d	368	if (pdata) {
8bb986a8	369	i2c->reg_shift = pdata->reg_shift;
7326e38f	370	i2c->reg_io_width = pdata->reg_io_width;
049bb69d JB	371	i2c->clock_khz = pdata->clock_khz;
	372	} else {
	373	ret = ocores_i2c_of_probe(pdev, i2c);
	374	if (ret)
	375	return ret;
	376	}
	377
7326e38f GR	378	if (i2c->reg_io_width == 0)
	379	i2c->reg_io_width = 1; /* Set to default value */
	380
a000b8c1 AL	381	if (!i2c->setreg \|\| !i2c->getreg) {
	382	switch (i2c->reg_io_width) {
	383	case 1:
	384	i2c->setreg = oc_setreg_8;
	385	i2c->getreg = oc_getreg_8;
	386	break;
	387
	388	case 2:
	389	i2c->setreg = oc_setreg_16;
	390	i2c->getreg = oc_getreg_16;
	391	break;
	392
	393	case 4:
	394	i2c->setreg = oc_setreg_32;
	395	i2c->getreg = oc_getreg_32;
	396	break;
	397
	398	default:
	399	dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
	400	i2c->reg_io_width);
	401	return -EINVAL;
	402	}
	403	}
	404
2373c180	405	ocores_init(i2c);
18f98b1e PK	406
18f98b1e PK	407	init_waitqueue_head(&i2c->wait);
f5f35a92	408	ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
47def5b8	409	pdev->name, i2c);
18f98b1e PK	410	if (ret) {
18f98b1e PK	411	dev_err(&pdev->dev, "Cannot claim IRQ\n");
47def5b8	412	return ret;
18f98b1e PK	413	}
	414
	415	/* hook up driver to tree */
	416	platform_set_drvdata(pdev, i2c);
	417	i2c->adap = ocores_adapter;
	418	i2c_set_adapdata(&i2c->adap, i2c);
	419	i2c->adap.dev.parent = &pdev->dev;
049bb69d	420	i2c->adap.dev.of_node = pdev->dev.of_node;
18f98b1e PK	421
	422	/* add i2c adapter to i2c tree */
	423	ret = i2c_add_adapter(&i2c->adap);
	424	if (ret) {
	425	dev_err(&pdev->dev, "Failed to add adapter\n");
47def5b8	426	return ret;
18f98b1e PK	427	}
18f98b1e PK	428
dd14be4c	429	/* add in known devices to the bus */
049bb69d JB	430	if (pdata) {
	431	for (i = 0; i < pdata->num_devices; i++)
	432	i2c_new_device(&i2c->adap, pdata->devices + i);
	433	}
dd14be4c	434
18f98b1e	435	return 0;
18f98b1e PK	436	}
18f98b1e PK	437
0b255e92	438	static int ocores_i2c_remove(struct platform_device *pdev)
18f98b1e PK	439	{
18f98b1e PK	440	struct ocores_i2c *i2c = platform_get_drvdata(pdev);
18f98b1e PK	441
	442	/* disable i2c logic */
	443	oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
	444	& ~(OCI2C_CTRL_EN\|OCI2C_CTRL_IEN));
	445
	446	/* remove adapter & data */
	447	i2c_del_adapter(&i2c->adap);
18f98b1e	448
18f98b1e PK	449	return 0;
	450	}
	451
f076e916	452	#ifdef CONFIG_PM_SLEEP
84603c7c	453	static int ocores_i2c_suspend(struct device *dev)
2373c180	454	{
84603c7c	455	struct ocores_i2c *i2c = dev_get_drvdata(dev);
2373c180 ML	456	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
	457
	458	/* make sure the device is disabled */
	459	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN\|OCI2C_CTRL_IEN));
	460
	461	return 0;
	462	}
	463
84603c7c	464	static int ocores_i2c_resume(struct device *dev)
2373c180	465	{
84603c7c	466	struct ocores_i2c *i2c = dev_get_drvdata(dev);
2373c180 ML	467
	468	ocores_init(i2c);
	469
	470	return 0;
	471	}
84603c7c RW	472
	473	static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
	474	#define OCORES_I2C_PM (&ocores_i2c_pm)
2373c180	475	#else
84603c7c	476	#define OCORES_I2C_PM NULL
2373c180 ML	477	#endif
2373c180 ML	478
18f98b1e	479	static struct platform_driver ocores_i2c_driver = {
2373c180	480	.probe = ocores_i2c_probe,
0b255e92	481	.remove = ocores_i2c_remove,
2373c180	482	.driver = {
18f98b1e PK	483	.owner = THIS_MODULE,
18f98b1e PK	484	.name = "ocores-i2c",
c9e358df	485	.of_match_table = ocores_i2c_match,
84603c7c	486	.pm = OCORES_I2C_PM,
18f98b1e PK	487	},
	488	};
	489
a3664b51	490	module_platform_driver(ocores_i2c_driver);
18f98b1e PK	491
	492	MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
	493	MODULE_DESCRIPTION("OpenCores I2C bus driver");
	494	MODULE_LICENSE("GPL");
a3664b51	495	MODULE_ALIAS("platform:ocores-i2c");