[deliverable/linux.git] / drivers / i2c / busses / i2c-ocores.c

/*
 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
 * (http://www.opencores.org/projects.cgi/web/i2c/overview).
 *
 * Peter Korsgaard <jacmet@sunsite.dk>
 *
 * Support for the GRLIB port of the controller by
 * Andreas Larsson <andreas@gaisler.com>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/i2c-ocores.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of_i2c.h>
#include <linux/log2.h>

struct ocores_i2c {
	void __iomem *base;
	u32 reg_shift;
	u32 reg_io_width;
	wait_queue_head_t wait;
	struct i2c_adapter adap;
	struct i2c_msg *msg;
	int pos;
	int nmsgs;
	int state; /* see STATE_ */
	int clock_khz;
	void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
	u8 (*getreg)(struct ocores_i2c *i2c, int reg);
};

/* registers */
#define OCI2C_PRELOW		0
#define OCI2C_PREHIGH		1
#define OCI2C_CONTROL		2
#define OCI2C_DATA		3
#define OCI2C_CMD		4 /* write only */
#define OCI2C_STATUS		4 /* read only, same address as OCI2C_CMD */

#define OCI2C_CTRL_IEN		0x40
#define OCI2C_CTRL_EN		0x80

#define OCI2C_CMD_START		0x91
#define OCI2C_CMD_STOP		0x41
#define OCI2C_CMD_READ		0x21
#define OCI2C_CMD_WRITE		0x11
#define OCI2C_CMD_READ_ACK	0x21
#define OCI2C_CMD_READ_NACK	0x29
#define OCI2C_CMD_IACK		0x01

#define OCI2C_STAT_IF		0x01
#define OCI2C_STAT_TIP		0x02
#define OCI2C_STAT_ARBLOST	0x20
#define OCI2C_STAT_BUSY		0x40
#define OCI2C_STAT_NACK		0x80

#define STATE_DONE		0
#define STATE_START		1
#define STATE_WRITE		2
#define STATE_READ		3
#define STATE_ERROR		4

#define TYPE_OCORES		0
#define TYPE_GRLIB		1

static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
{
	iowrite8(value, i2c->base + (reg << i2c->reg_shift));
}

static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
{
	iowrite16(value, i2c->base + (reg << i2c->reg_shift));
}

static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
{
	iowrite32(value, i2c->base + (reg << i2c->reg_shift));
}

static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
{
	return ioread8(i2c->base + (reg << i2c->reg_shift));
}

static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
{
	return ioread16(i2c->base + (reg << i2c->reg_shift));
}

static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
{
	return ioread32(i2c->base + (reg << i2c->reg_shift));
}

static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
{
	i2c->setreg(i2c, reg, value);
}

static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
{
	return i2c->getreg(i2c, reg);
}

static void ocores_process(struct ocores_i2c *i2c)
{
	struct i2c_msg *msg = i2c->msg;
	u8 stat = oc_getreg(i2c, OCI2C_STATUS);

	if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
		/* stop has been sent */
		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
		wake_up(&i2c->wait);
		return;
	}

	/* error? */
	if (stat & OCI2C_STAT_ARBLOST) {
		i2c->state = STATE_ERROR;
		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
		return;
	}

	if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
		i2c->state =
			(msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;

		if (stat & OCI2C_STAT_NACK) {
			i2c->state = STATE_ERROR;
			oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
			return;
		}
	} else
		msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);

	/* end of msg? */
	if (i2c->pos == msg->len) {
		i2c->nmsgs--;
		i2c->msg++;
		i2c->pos = 0;
		msg = i2c->msg;

		if (i2c->nmsgs) {	/* end? */
			/* send start? */
			if (!(msg->flags & I2C_M_NOSTART)) {
				u8 addr = (msg->addr << 1);

				if (msg->flags & I2C_M_RD)
					addr |= 1;

				i2c->state = STATE_START;

				oc_setreg(i2c, OCI2C_DATA, addr);
				oc_setreg(i2c, OCI2C_CMD,  OCI2C_CMD_START);
				return;
			} else
				i2c->state = (msg->flags & I2C_M_RD)
					? STATE_READ : STATE_WRITE;
		} else {
			i2c->state = STATE_DONE;
			oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
			return;
		}
	}

	if (i2c->state == STATE_READ) {
		oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
			  OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
	} else {
		oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
	}
}

static irqreturn_t ocores_isr(int irq, void *dev_id)
{
	struct ocores_i2c *i2c = dev_id;

	ocores_process(i2c);

	return IRQ_HANDLED;
}

static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
	struct ocores_i2c *i2c = i2c_get_adapdata(adap);

	i2c->msg = msgs;
	i2c->pos = 0;
	i2c->nmsgs = num;
	i2c->state = STATE_START;

	oc_setreg(i2c, OCI2C_DATA,
			(i2c->msg->addr << 1) |
			((i2c->msg->flags & I2C_M_RD) ? 1:0));

	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);

	if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
			       (i2c->state == STATE_DONE), HZ))
		return (i2c->state == STATE_DONE) ? num : -EIO;
	else
		return -ETIMEDOUT;
}

static void ocores_init(struct ocores_i2c *i2c)
{
	int prescale;
	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);

	/* make sure the device is disabled */
	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));

	prescale = (i2c->clock_khz / (5*100)) - 1;
	oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
	oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);

	/* Init the device */
	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
	oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);
}


static u32 ocores_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm ocores_algorithm = {
	.master_xfer	= ocores_xfer,
	.functionality	= ocores_func,
};

static struct i2c_adapter ocores_adapter = {
	.owner		= THIS_MODULE,
	.name		= "i2c-ocores",
	.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD,
	.algo		= &ocores_algorithm,
};

static struct of_device_id ocores_i2c_match[] = {
	{
		.compatible = "opencores,i2c-ocores",
		.data = (void *)TYPE_OCORES,
	},
	{
		.compatible = "aeroflexgaisler,i2cmst",
		.data = (void *)TYPE_GRLIB,
	},
	{},
};
MODULE_DEVICE_TABLE(of, ocores_i2c_match);

#ifdef CONFIG_OF
/* Read and write functions for the GRLIB port of the controller. Registers are
 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
 * register. The subsequent registers has their offset decreased accordingly. */
static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
{
	u32 rd;
	int rreg = reg;
	if (reg != OCI2C_PRELOW)
		rreg--;
	rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
	if (reg == OCI2C_PREHIGH)
		return (u8)(rd >> 8);
	else
		return (u8)rd;
}

static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
{
	u32 curr, wr;
	int rreg = reg;
	if (reg != OCI2C_PRELOW)
		rreg--;
	if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
		curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
		if (reg == OCI2C_PRELOW)
			wr = (curr & 0xff00) | value;
		else
			wr = (((u32)value) << 8) | (curr & 0xff);
	} else {
		wr = value;
	}
	iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
}

static int ocores_i2c_of_probe(struct platform_device *pdev,
				struct ocores_i2c *i2c)
{
	struct device_node *np = pdev->dev.of_node;
	const struct of_device_id *match;
	u32 val;

	if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
		/* no 'reg-shift', check for deprecated 'regstep' */
		if (!of_property_read_u32(np, "regstep", &val)) {
			if (!is_power_of_2(val)) {
				dev_err(&pdev->dev, "invalid regstep %d\n",
					val);
				return -EINVAL;
			}
			i2c->reg_shift = ilog2(val);
			dev_warn(&pdev->dev,
				"regstep property deprecated, use reg-shift\n");
		}
	}

	if (of_property_read_u32(np, "clock-frequency", &val)) {
		dev_err(&pdev->dev,
			"Missing required parameter 'clock-frequency'\n");
		return -ENODEV;
	}
	i2c->clock_khz = val / 1000;

	of_property_read_u32(pdev->dev.of_node, "reg-io-width",
				&i2c->reg_io_width);

	match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
	if (match && (long)match->data == TYPE_GRLIB) {
		dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
		i2c->setreg = oc_setreg_grlib;
		i2c->getreg = oc_getreg_grlib;
	}

	return 0;
}
#else
#define ocores_i2c_of_probe(pdev,i2c) -ENODEV
#endif

static int ocores_i2c_probe(struct platform_device *pdev)
{
	struct ocores_i2c *i2c;
	struct ocores_i2c_platform_data *pdata;
	struct resource *res;
	int irq;
	int ret;
	int i;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENODEV;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
	if (!i2c)
		return -ENOMEM;

	i2c->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(i2c->base))
		return PTR_ERR(i2c->base);

	pdata = pdev->dev.platform_data;
	if (pdata) {
		i2c->reg_shift = pdata->reg_shift;
		i2c->reg_io_width = pdata->reg_io_width;
		i2c->clock_khz = pdata->clock_khz;
	} else {
		ret = ocores_i2c_of_probe(pdev, i2c);
		if (ret)
			return ret;
	}

	if (i2c->reg_io_width == 0)
		i2c->reg_io_width = 1; /* Set to default value */

	if (!i2c->setreg || !i2c->getreg) {
		switch (i2c->reg_io_width) {
		case 1:
			i2c->setreg = oc_setreg_8;
			i2c->getreg = oc_getreg_8;
			break;

		case 2:
			i2c->setreg = oc_setreg_16;
			i2c->getreg = oc_getreg_16;
			break;

		case 4:
			i2c->setreg = oc_setreg_32;
			i2c->getreg = oc_getreg_32;
			break;

		default:
			dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
				i2c->reg_io_width);
			return -EINVAL;
		}
	}

	ocores_init(i2c);

	init_waitqueue_head(&i2c->wait);
	ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
			       pdev->name, i2c);
	if (ret) {
		dev_err(&pdev->dev, "Cannot claim IRQ\n");
		return ret;
	}

	/* hook up driver to tree */
	platform_set_drvdata(pdev, i2c);
	i2c->adap = ocores_adapter;
	i2c_set_adapdata(&i2c->adap, i2c);
	i2c->adap.dev.parent = &pdev->dev;
	i2c->adap.dev.of_node = pdev->dev.of_node;

	/* add i2c adapter to i2c tree */
	ret = i2c_add_adapter(&i2c->adap);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add adapter\n");
		return ret;
	}

	/* add in known devices to the bus */
	if (pdata) {
		for (i = 0; i < pdata->num_devices; i++)
			i2c_new_device(&i2c->adap, pdata->devices + i);
	} else {
		of_i2c_register_devices(&i2c->adap);
	}

	return 0;
}

static int ocores_i2c_remove(struct platform_device *pdev)
{
	struct ocores_i2c *i2c = platform_get_drvdata(pdev);

	/* disable i2c logic */
	oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
		  & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));

	/* remove adapter & data */
	i2c_del_adapter(&i2c->adap);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int ocores_i2c_suspend(struct device *dev)
{
	struct ocores_i2c *i2c = dev_get_drvdata(dev);
	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);

	/* make sure the device is disabled */
	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));

	return 0;
}

static int ocores_i2c_resume(struct device *dev)
{
	struct ocores_i2c *i2c = dev_get_drvdata(dev);

	ocores_init(i2c);

	return 0;
}

static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
#define OCORES_I2C_PM	(&ocores_i2c_pm)
#else
#define OCORES_I2C_PM	NULL
#endif

static struct platform_driver ocores_i2c_driver = {
	.probe   = ocores_i2c_probe,
	.remove  = ocores_i2c_remove,
	.driver  = {
		.owner = THIS_MODULE,
		.name = "ocores-i2c",
		.of_match_table = ocores_i2c_match,
		.pm = OCORES_I2C_PM,
	},
};

module_platform_driver(ocores_i2c_driver);

MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
MODULE_DESCRIPTION("OpenCores I2C bus driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ocores-i2c");
Commit	Line	Data
18f98b1e PK	1	/*
	2	* i2c-ocores.c: I2C bus driver for OpenCores I2C controller
	3	* (http://www.opencores.org/projects.cgi/web/i2c/overview).
	4	*
	5	* Peter Korsgaard <jacmet@sunsite.dk>
	6	*
a000b8c1 AL	7	* Support for the GRLIB port of the controller by
	8	* Andreas Larsson <andreas@gaisler.com>
	9	*
18f98b1e PK	10	* This file is licensed under the terms of the GNU General Public License
	11	* version 2. This program is licensed "as is" without any warranty of any
	12	* kind, whether express or implied.
	13	*/
	14
84dbf809	15	#include <linux/err.h>
18f98b1e PK	16	#include <linux/kernel.h>
18f98b1e PK	17	#include <linux/module.h>
18f98b1e PK	18	#include <linux/init.h>
	19	#include <linux/errno.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/i2c.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/wait.h>
	24	#include <linux/i2c-ocores.h>
5a0e3ad6	25	#include <linux/slab.h>
21782180	26	#include <linux/io.h>
a5063f16	27	#include <linux/of_i2c.h>
8bb986a8	28	#include <linux/log2.h>
18f98b1e PK	29
	30	struct ocores_i2c {
	31	void __iomem *base;
8bb986a8	32	u32 reg_shift;
7326e38f	33	u32 reg_io_width;
18f98b1e PK	34	wait_queue_head_t wait;
	35	struct i2c_adapter adap;
	36	struct i2c_msg *msg;
	37	int pos;
	38	int nmsgs;
	39	int state; /* see STATE_ */
2373c180	40	int clock_khz;
a000b8c1 AL	41	void (setreg)(struct ocores_i2c i2c, int reg, u8 value);
a000b8c1 AL	42	u8 (getreg)(struct ocores_i2c i2c, int reg);
18f98b1e PK	43	};
	44
	45	/* registers */
	46	#define OCI2C_PRELOW 0
	47	#define OCI2C_PREHIGH 1
	48	#define OCI2C_CONTROL 2
	49	#define OCI2C_DATA 3
1ded969f PK	50	#define OCI2C_CMD 4 /* write only */
1ded969f PK	51	#define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
18f98b1e PK	52
	53	#define OCI2C_CTRL_IEN 0x40
	54	#define OCI2C_CTRL_EN 0x80
	55
	56	#define OCI2C_CMD_START 0x91
	57	#define OCI2C_CMD_STOP 0x41
	58	#define OCI2C_CMD_READ 0x21
	59	#define OCI2C_CMD_WRITE 0x11
	60	#define OCI2C_CMD_READ_ACK 0x21
	61	#define OCI2C_CMD_READ_NACK 0x29
	62	#define OCI2C_CMD_IACK 0x01
	63
	64	#define OCI2C_STAT_IF 0x01
	65	#define OCI2C_STAT_TIP 0x02
	66	#define OCI2C_STAT_ARBLOST 0x20
	67	#define OCI2C_STAT_BUSY 0x40
	68	#define OCI2C_STAT_NACK 0x80
	69
	70	#define STATE_DONE 0
	71	#define STATE_START 1
	72	#define STATE_WRITE 2
	73	#define STATE_READ 3
	74	#define STATE_ERROR 4
	75
a000b8c1 AL	76	#define TYPE_OCORES 0
	77	#define TYPE_GRLIB 1
	78
	79	static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
18f98b1e	80	{
a000b8c1 AL	81	iowrite8(value, i2c->base + (reg << i2c->reg_shift));
	82	}
	83
	84	static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
	85	{
	86	iowrite16(value, i2c->base + (reg << i2c->reg_shift));
	87	}
	88
	89	static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
	90	{
	91	iowrite32(value, i2c->base + (reg << i2c->reg_shift));
	92	}
	93
	94	static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
	95	{
	96	return ioread8(i2c->base + (reg << i2c->reg_shift));
	97	}
	98
	99	static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
	100	{
	101	return ioread16(i2c->base + (reg << i2c->reg_shift));
	102	}
	103
	104	static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
	105	{
	106	return ioread32(i2c->base + (reg << i2c->reg_shift));
	107	}
	108
18f98b1e PK	109	static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
18f98b1e PK	110	{
a000b8c1	111	i2c->setreg(i2c, reg, value);
18f98b1e PK	112	}
	113
	114	static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
	115	{
a000b8c1	116	return i2c->getreg(i2c, reg);
18f98b1e PK	117	}
	118
	119	static void ocores_process(struct ocores_i2c *i2c)
	120	{
	121	struct i2c_msg *msg = i2c->msg;
	122	u8 stat = oc_getreg(i2c, OCI2C_STATUS);
	123
	124	if ((i2c->state == STATE_DONE) \|\| (i2c->state == STATE_ERROR)) {
	125	/* stop has been sent */
	126	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
	127	wake_up(&i2c->wait);
	128	return;
	129	}
	130
	131	/* error? */
	132	if (stat & OCI2C_STAT_ARBLOST) {
	133	i2c->state = STATE_ERROR;
	134	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
	135	return;
	136	}
	137
	138	if ((i2c->state == STATE_START) \|\| (i2c->state == STATE_WRITE)) {
	139	i2c->state =
	140	(msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
	141
	142	if (stat & OCI2C_STAT_NACK) {
	143	i2c->state = STATE_ERROR;
	144	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
	145	return;
	146	}
	147	} else
	148	msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
	149
	150	/* end of msg? */
	151	if (i2c->pos == msg->len) {
	152	i2c->nmsgs--;
	153	i2c->msg++;
	154	i2c->pos = 0;
	155	msg = i2c->msg;
	156
	157	if (i2c->nmsgs) { /* end? */
	158	/* send start? */
	159	if (!(msg->flags & I2C_M_NOSTART)) {
	160	u8 addr = (msg->addr << 1);
	161
	162	if (msg->flags & I2C_M_RD)
	163	addr \|= 1;
	164
	165	i2c->state = STATE_START;
	166
	167	oc_setreg(i2c, OCI2C_DATA, addr);
	168	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
	169	return;
	170	} else
	171	i2c->state = (msg->flags & I2C_M_RD)
	172	? STATE_READ : STATE_WRITE;
	173	} else {
	174	i2c->state = STATE_DONE;
	175	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
	176	return;
	177	}
	178	}
	179
	180	if (i2c->state == STATE_READ) {
181	oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
182	OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
183	} else {
184	oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
185	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
186	}
187	}
188
7d12e780	189	static irqreturn_t ocores_isr(int irq, void *dev_id)
18f98b1e PK	190	{
	191	struct ocores_i2c *i2c = dev_id;
	192
	193	ocores_process(i2c);
	194
	195	return IRQ_HANDLED;
	196	}
	197
	198	static int ocores_xfer(struct i2c_adapter adap, struct i2c_msg msgs, int num)
	199	{
	200	struct ocores_i2c *i2c = i2c_get_adapdata(adap);
	201
	202	i2c->msg = msgs;
	203	i2c->pos = 0;
	204	i2c->nmsgs = num;
	205	i2c->state = STATE_START;
	206
	207	oc_setreg(i2c, OCI2C_DATA,
	208	(i2c->msg->addr << 1) \|
	209	((i2c->msg->flags & I2C_M_RD) ? 1:0));
	210
	211	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
	212
	213	if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) \|\|
	214	(i2c->state == STATE_DONE), HZ))
	215	return (i2c->state == STATE_DONE) ? num : -EIO;
	216	else
	217	return -ETIMEDOUT;
	218	}
	219
2373c180	220	static void ocores_init(struct ocores_i2c *i2c)
18f98b1e PK	221	{
	222	int prescale;
	223	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
	224
	225	/* make sure the device is disabled */
	226	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN\|OCI2C_CTRL_IEN));
	227
2373c180	228	prescale = (i2c->clock_khz / (5*100)) - 1;
18f98b1e PK	229	oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
	230	oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
	231
	232	/* Init the device */
	233	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
	234	oc_setreg(i2c, OCI2C_CONTROL, ctrl \| OCI2C_CTRL_IEN \| OCI2C_CTRL_EN);
	235	}
	236
	237
	238	static u32 ocores_func(struct i2c_adapter *adap)
	239	{
	240	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	241	}
	242
8f9082c5	243	static const struct i2c_algorithm ocores_algorithm = {
18f98b1e PK	244	.master_xfer = ocores_xfer,
	245	.functionality = ocores_func,
	246	};
	247
	248	static struct i2c_adapter ocores_adapter = {
	249	.owner = THIS_MODULE,
	250	.name = "i2c-ocores",
3401b2ff	251	.class = I2C_CLASS_HWMON \| I2C_CLASS_SPD,
18f98b1e	252	.algo = &ocores_algorithm,
18f98b1e PK	253	};
18f98b1e PK	254
a000b8c1 AL	255	static struct of_device_id ocores_i2c_match[] = {
	256	{
	257	.compatible = "opencores,i2c-ocores",
	258	.data = (void *)TYPE_OCORES,
	259	},
	260	{
	261	.compatible = "aeroflexgaisler,i2cmst",
	262	.data = (void *)TYPE_GRLIB,
	263	},
	264	{},
	265	};
	266	MODULE_DEVICE_TABLE(of, ocores_i2c_match);
	267
049bb69d	268	#ifdef CONFIG_OF
c5d54744 AL	269	/* Read and write functions for the GRLIB port of the controller. Registers are
	270	* 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
	271	* register. The subsequent registers has their offset decreased accordingly. */
	272	static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
	273	{
	274	u32 rd;
	275	int rreg = reg;
	276	if (reg != OCI2C_PRELOW)
	277	rreg--;
	278	rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
	279	if (reg == OCI2C_PREHIGH)
	280	return (u8)(rd >> 8);
	281	else
	282	return (u8)rd;
	283	}
	284
	285	static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
	286	{
	287	u32 curr, wr;
	288	int rreg = reg;
	289	if (reg != OCI2C_PRELOW)
	290	rreg--;
	291	if (reg == OCI2C_PRELOW \|\| reg == OCI2C_PREHIGH) {
	292	curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
	293	if (reg == OCI2C_PRELOW)
	294	wr = (curr & 0xff00) \| value;
	295	else
	296	wr = (((u32)value) << 8) \| (curr & 0xff);
	297	} else {
	298	wr = value;
	299	}
	300	iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
	301	}
	302
9ae97a89 J	303	static int ocores_i2c_of_probe(struct platform_device *pdev,
9ae97a89 J	304	struct ocores_i2c *i2c)
049bb69d	305	{
8bb986a8	306	struct device_node *np = pdev->dev.of_node;
a000b8c1	307	const struct of_device_id *match;
8bb986a8 GR	308	u32 val;
	309
	310	if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
	311	/* no 'reg-shift', check for deprecated 'regstep' */
	312	if (!of_property_read_u32(np, "regstep", &val)) {
	313	if (!is_power_of_2(val)) {
	314	dev_err(&pdev->dev, "invalid regstep %d\n",
	315	val);
	316	return -EINVAL;
	317	}
	318	i2c->reg_shift = ilog2(val);
	319	dev_warn(&pdev->dev,
	320	"regstep property deprecated, use reg-shift\n");
	321	}
049bb69d	322	}
049bb69d	323
8bb986a8	324	if (of_property_read_u32(np, "clock-frequency", &val)) {
049bb69d	325	dev_err(&pdev->dev,
9ae97a89	326	"Missing required parameter 'clock-frequency'\n");
049bb69d JB	327	return -ENODEV;
049bb69d JB	328	}
8bb986a8	329	i2c->clock_khz = val / 1000;
049bb69d	330
7326e38f GR	331	of_property_read_u32(pdev->dev.of_node, "reg-io-width",
7326e38f GR	332	&i2c->reg_io_width);
a000b8c1 AL	333
a000b8c1 AL	334	match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
6beaddf2	335	if (match && (long)match->data == TYPE_GRLIB) {
a000b8c1 AL	336	dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
	337	i2c->setreg = oc_setreg_grlib;
	338	i2c->getreg = oc_getreg_grlib;
	339	}
	340
049bb69d JB	341	return 0;
	342	}
	343	#else
	344	#define ocores_i2c_of_probe(pdev,i2c) -ENODEV
	345	#endif
18f98b1e	346
0b255e92	347	static int ocores_i2c_probe(struct platform_device *pdev)
18f98b1e PK	348	{
	349	struct ocores_i2c *i2c;
	350	struct ocores_i2c_platform_data *pdata;
f5f35a92 AL	351	struct resource *res;
f5f35a92 AL	352	int irq;
18f98b1e	353	int ret;
dd14be4c	354	int i;
18f98b1e PK	355
	356	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	357	if (!res)
	358	return -ENODEV;
	359
f5f35a92 AL	360	irq = platform_get_irq(pdev, 0);
	361	if (irq < 0)
	362	return irq;
18f98b1e	363
47def5b8	364	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
18f98b1e PK	365	if (!i2c)
	366	return -ENOMEM;
	367
84dbf809 TR	368	i2c->base = devm_ioremap_resource(&pdev->dev, res);
	369	if (IS_ERR(i2c->base))
	370	return PTR_ERR(i2c->base);
18f98b1e	371
3271d382	372	pdata = pdev->dev.platform_data;
049bb69d	373	if (pdata) {
8bb986a8	374	i2c->reg_shift = pdata->reg_shift;
7326e38f	375	i2c->reg_io_width = pdata->reg_io_width;
049bb69d JB	376	i2c->clock_khz = pdata->clock_khz;
	377	} else {
	378	ret = ocores_i2c_of_probe(pdev, i2c);
	379	if (ret)
	380	return ret;
	381	}
	382
7326e38f GR	383	if (i2c->reg_io_width == 0)
	384	i2c->reg_io_width = 1; /* Set to default value */
	385
a000b8c1 AL	386	if (!i2c->setreg \|\| !i2c->getreg) {
	387	switch (i2c->reg_io_width) {
	388	case 1:
	389	i2c->setreg = oc_setreg_8;
	390	i2c->getreg = oc_getreg_8;
	391	break;
	392
	393	case 2:
	394	i2c->setreg = oc_setreg_16;
	395	i2c->getreg = oc_getreg_16;
	396	break;
	397
	398	case 4:
	399	i2c->setreg = oc_setreg_32;
	400	i2c->getreg = oc_getreg_32;
	401	break;
	402
	403	default:
	404	dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
	405	i2c->reg_io_width);
	406	return -EINVAL;
	407	}
	408	}
	409
2373c180	410	ocores_init(i2c);
18f98b1e PK	411
18f98b1e PK	412	init_waitqueue_head(&i2c->wait);
f5f35a92	413	ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
47def5b8	414	pdev->name, i2c);
18f98b1e PK	415	if (ret) {
18f98b1e PK	416	dev_err(&pdev->dev, "Cannot claim IRQ\n");
47def5b8	417	return ret;
18f98b1e PK	418	}
	419
	420	/* hook up driver to tree */
	421	platform_set_drvdata(pdev, i2c);
	422	i2c->adap = ocores_adapter;
	423	i2c_set_adapdata(&i2c->adap, i2c);
	424	i2c->adap.dev.parent = &pdev->dev;
049bb69d	425	i2c->adap.dev.of_node = pdev->dev.of_node;
18f98b1e PK	426
	427	/* add i2c adapter to i2c tree */
	428	ret = i2c_add_adapter(&i2c->adap);
	429	if (ret) {
	430	dev_err(&pdev->dev, "Failed to add adapter\n");
47def5b8	431	return ret;
18f98b1e PK	432	}
18f98b1e PK	433
dd14be4c	434	/* add in known devices to the bus */
049bb69d JB	435	if (pdata) {
	436	for (i = 0; i < pdata->num_devices; i++)
	437	i2c_new_device(&i2c->adap, pdata->devices + i);
a5063f16 GR	438	} else {
a5063f16 GR	439	of_i2c_register_devices(&i2c->adap);
049bb69d	440	}
dd14be4c	441
18f98b1e	442	return 0;
18f98b1e PK	443	}
18f98b1e PK	444
0b255e92	445	static int ocores_i2c_remove(struct platform_device *pdev)
18f98b1e PK	446	{
18f98b1e PK	447	struct ocores_i2c *i2c = platform_get_drvdata(pdev);
18f98b1e PK	448
	449	/* disable i2c logic */
	450	oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
	451	& ~(OCI2C_CTRL_EN\|OCI2C_CTRL_IEN));
	452
	453	/* remove adapter & data */
	454	i2c_del_adapter(&i2c->adap);
18f98b1e	455
18f98b1e PK	456	return 0;
	457	}
	458
f076e916	459	#ifdef CONFIG_PM_SLEEP
84603c7c	460	static int ocores_i2c_suspend(struct device *dev)
2373c180	461	{
84603c7c	462	struct ocores_i2c *i2c = dev_get_drvdata(dev);
2373c180 ML	463	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
	464
	465	/* make sure the device is disabled */
	466	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN\|OCI2C_CTRL_IEN));
	467
	468	return 0;
	469	}
	470
84603c7c	471	static int ocores_i2c_resume(struct device *dev)
2373c180	472	{
84603c7c	473	struct ocores_i2c *i2c = dev_get_drvdata(dev);
2373c180 ML	474
	475	ocores_init(i2c);
	476
	477	return 0;
	478	}
84603c7c RW	479
	480	static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
	481	#define OCORES_I2C_PM (&ocores_i2c_pm)
2373c180	482	#else
84603c7c	483	#define OCORES_I2C_PM NULL
2373c180 ML	484	#endif
2373c180 ML	485
18f98b1e	486	static struct platform_driver ocores_i2c_driver = {
2373c180	487	.probe = ocores_i2c_probe,
0b255e92	488	.remove = ocores_i2c_remove,
2373c180	489	.driver = {
18f98b1e PK	490	.owner = THIS_MODULE,
18f98b1e PK	491	.name = "ocores-i2c",
c9e358df	492	.of_match_table = ocores_i2c_match,
84603c7c	493	.pm = OCORES_I2C_PM,
18f98b1e PK	494	},
	495	};
	496
a3664b51	497	module_platform_driver(ocores_i2c_driver);
18f98b1e PK	498
	499	MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
	500	MODULE_DESCRIPTION("OpenCores I2C bus driver");
	501	MODULE_LICENSE("GPL");
a3664b51	502	MODULE_ALIAS("platform:ocores-i2c");