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18f98b1e PK |
1 | /* |
2 | * i2c-ocores.c: I2C bus driver for OpenCores I2C controller | |
3 | * (http://www.opencores.org/projects.cgi/web/i2c/overview). | |
4 | * | |
5 | * Peter Korsgaard <jacmet@sunsite.dk> | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public License | |
8 | * version 2. This program is licensed "as is" without any warranty of any | |
9 | * kind, whether express or implied. | |
10 | */ | |
11 | ||
18f98b1e PK |
12 | #include <linux/kernel.h> |
13 | #include <linux/module.h> | |
18f98b1e PK |
14 | #include <linux/init.h> |
15 | #include <linux/errno.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/wait.h> | |
20 | #include <linux/i2c-ocores.h> | |
21 | #include <asm/io.h> | |
22 | ||
23 | struct ocores_i2c { | |
24 | void __iomem *base; | |
25 | int regstep; | |
26 | wait_queue_head_t wait; | |
27 | struct i2c_adapter adap; | |
28 | struct i2c_msg *msg; | |
29 | int pos; | |
30 | int nmsgs; | |
31 | int state; /* see STATE_ */ | |
2373c180 | 32 | int clock_khz; |
18f98b1e PK |
33 | }; |
34 | ||
35 | /* registers */ | |
36 | #define OCI2C_PRELOW 0 | |
37 | #define OCI2C_PREHIGH 1 | |
38 | #define OCI2C_CONTROL 2 | |
39 | #define OCI2C_DATA 3 | |
1ded969f PK |
40 | #define OCI2C_CMD 4 /* write only */ |
41 | #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */ | |
18f98b1e PK |
42 | |
43 | #define OCI2C_CTRL_IEN 0x40 | |
44 | #define OCI2C_CTRL_EN 0x80 | |
45 | ||
46 | #define OCI2C_CMD_START 0x91 | |
47 | #define OCI2C_CMD_STOP 0x41 | |
48 | #define OCI2C_CMD_READ 0x21 | |
49 | #define OCI2C_CMD_WRITE 0x11 | |
50 | #define OCI2C_CMD_READ_ACK 0x21 | |
51 | #define OCI2C_CMD_READ_NACK 0x29 | |
52 | #define OCI2C_CMD_IACK 0x01 | |
53 | ||
54 | #define OCI2C_STAT_IF 0x01 | |
55 | #define OCI2C_STAT_TIP 0x02 | |
56 | #define OCI2C_STAT_ARBLOST 0x20 | |
57 | #define OCI2C_STAT_BUSY 0x40 | |
58 | #define OCI2C_STAT_NACK 0x80 | |
59 | ||
60 | #define STATE_DONE 0 | |
61 | #define STATE_START 1 | |
62 | #define STATE_WRITE 2 | |
63 | #define STATE_READ 3 | |
64 | #define STATE_ERROR 4 | |
65 | ||
66 | static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value) | |
67 | { | |
68 | iowrite8(value, i2c->base + reg * i2c->regstep); | |
69 | } | |
70 | ||
71 | static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg) | |
72 | { | |
73 | return ioread8(i2c->base + reg * i2c->regstep); | |
74 | } | |
75 | ||
76 | static void ocores_process(struct ocores_i2c *i2c) | |
77 | { | |
78 | struct i2c_msg *msg = i2c->msg; | |
79 | u8 stat = oc_getreg(i2c, OCI2C_STATUS); | |
80 | ||
81 | if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) { | |
82 | /* stop has been sent */ | |
83 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); | |
84 | wake_up(&i2c->wait); | |
85 | return; | |
86 | } | |
87 | ||
88 | /* error? */ | |
89 | if (stat & OCI2C_STAT_ARBLOST) { | |
90 | i2c->state = STATE_ERROR; | |
91 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); | |
92 | return; | |
93 | } | |
94 | ||
95 | if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) { | |
96 | i2c->state = | |
97 | (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; | |
98 | ||
99 | if (stat & OCI2C_STAT_NACK) { | |
100 | i2c->state = STATE_ERROR; | |
101 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); | |
102 | return; | |
103 | } | |
104 | } else | |
105 | msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA); | |
106 | ||
107 | /* end of msg? */ | |
108 | if (i2c->pos == msg->len) { | |
109 | i2c->nmsgs--; | |
110 | i2c->msg++; | |
111 | i2c->pos = 0; | |
112 | msg = i2c->msg; | |
113 | ||
114 | if (i2c->nmsgs) { /* end? */ | |
115 | /* send start? */ | |
116 | if (!(msg->flags & I2C_M_NOSTART)) { | |
117 | u8 addr = (msg->addr << 1); | |
118 | ||
119 | if (msg->flags & I2C_M_RD) | |
120 | addr |= 1; | |
121 | ||
122 | i2c->state = STATE_START; | |
123 | ||
124 | oc_setreg(i2c, OCI2C_DATA, addr); | |
125 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); | |
126 | return; | |
127 | } else | |
128 | i2c->state = (msg->flags & I2C_M_RD) | |
129 | ? STATE_READ : STATE_WRITE; | |
130 | } else { | |
131 | i2c->state = STATE_DONE; | |
132 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); | |
133 | return; | |
134 | } | |
135 | } | |
136 | ||
137 | if (i2c->state == STATE_READ) { | |
138 | oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ? | |
139 | OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK); | |
140 | } else { | |
141 | oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]); | |
142 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE); | |
143 | } | |
144 | } | |
145 | ||
7d12e780 | 146 | static irqreturn_t ocores_isr(int irq, void *dev_id) |
18f98b1e PK |
147 | { |
148 | struct ocores_i2c *i2c = dev_id; | |
149 | ||
150 | ocores_process(i2c); | |
151 | ||
152 | return IRQ_HANDLED; | |
153 | } | |
154 | ||
155 | static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) | |
156 | { | |
157 | struct ocores_i2c *i2c = i2c_get_adapdata(adap); | |
158 | ||
159 | i2c->msg = msgs; | |
160 | i2c->pos = 0; | |
161 | i2c->nmsgs = num; | |
162 | i2c->state = STATE_START; | |
163 | ||
164 | oc_setreg(i2c, OCI2C_DATA, | |
165 | (i2c->msg->addr << 1) | | |
166 | ((i2c->msg->flags & I2C_M_RD) ? 1:0)); | |
167 | ||
168 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); | |
169 | ||
170 | if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || | |
171 | (i2c->state == STATE_DONE), HZ)) | |
172 | return (i2c->state == STATE_DONE) ? num : -EIO; | |
173 | else | |
174 | return -ETIMEDOUT; | |
175 | } | |
176 | ||
2373c180 | 177 | static void ocores_init(struct ocores_i2c *i2c) |
18f98b1e PK |
178 | { |
179 | int prescale; | |
180 | u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); | |
181 | ||
182 | /* make sure the device is disabled */ | |
183 | oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); | |
184 | ||
2373c180 | 185 | prescale = (i2c->clock_khz / (5*100)) - 1; |
18f98b1e PK |
186 | oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff); |
187 | oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8); | |
188 | ||
189 | /* Init the device */ | |
190 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); | |
191 | oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN); | |
192 | } | |
193 | ||
194 | ||
195 | static u32 ocores_func(struct i2c_adapter *adap) | |
196 | { | |
197 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
198 | } | |
199 | ||
8f9082c5 | 200 | static const struct i2c_algorithm ocores_algorithm = { |
18f98b1e PK |
201 | .master_xfer = ocores_xfer, |
202 | .functionality = ocores_func, | |
203 | }; | |
204 | ||
205 | static struct i2c_adapter ocores_adapter = { | |
206 | .owner = THIS_MODULE, | |
207 | .name = "i2c-ocores", | |
3401b2ff | 208 | .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, |
18f98b1e | 209 | .algo = &ocores_algorithm, |
18f98b1e PK |
210 | }; |
211 | ||
212 | ||
213 | static int __devinit ocores_i2c_probe(struct platform_device *pdev) | |
214 | { | |
215 | struct ocores_i2c *i2c; | |
216 | struct ocores_i2c_platform_data *pdata; | |
217 | struct resource *res, *res2; | |
218 | int ret; | |
dd14be4c | 219 | int i; |
18f98b1e PK |
220 | |
221 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
222 | if (!res) | |
223 | return -ENODEV; | |
224 | ||
225 | res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
226 | if (!res2) | |
227 | return -ENODEV; | |
228 | ||
229 | pdata = (struct ocores_i2c_platform_data*) pdev->dev.platform_data; | |
230 | if (!pdata) | |
231 | return -ENODEV; | |
232 | ||
233 | i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); | |
234 | if (!i2c) | |
235 | return -ENOMEM; | |
236 | ||
c6ffddea | 237 | if (!request_mem_region(res->start, resource_size(res), |
18f98b1e PK |
238 | pdev->name)) { |
239 | dev_err(&pdev->dev, "Memory region busy\n"); | |
240 | ret = -EBUSY; | |
241 | goto request_mem_failed; | |
242 | } | |
243 | ||
c6ffddea | 244 | i2c->base = ioremap(res->start, resource_size(res)); |
18f98b1e PK |
245 | if (!i2c->base) { |
246 | dev_err(&pdev->dev, "Unable to map registers\n"); | |
247 | ret = -EIO; | |
248 | goto map_failed; | |
249 | } | |
250 | ||
251 | i2c->regstep = pdata->regstep; | |
2373c180 ML |
252 | i2c->clock_khz = pdata->clock_khz; |
253 | ocores_init(i2c); | |
18f98b1e PK |
254 | |
255 | init_waitqueue_head(&i2c->wait); | |
256 | ret = request_irq(res2->start, ocores_isr, 0, pdev->name, i2c); | |
257 | if (ret) { | |
258 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); | |
259 | goto request_irq_failed; | |
260 | } | |
261 | ||
262 | /* hook up driver to tree */ | |
263 | platform_set_drvdata(pdev, i2c); | |
264 | i2c->adap = ocores_adapter; | |
265 | i2c_set_adapdata(&i2c->adap, i2c); | |
266 | i2c->adap.dev.parent = &pdev->dev; | |
267 | ||
268 | /* add i2c adapter to i2c tree */ | |
269 | ret = i2c_add_adapter(&i2c->adap); | |
270 | if (ret) { | |
271 | dev_err(&pdev->dev, "Failed to add adapter\n"); | |
272 | goto add_adapter_failed; | |
273 | } | |
274 | ||
dd14be4c RR |
275 | /* add in known devices to the bus */ |
276 | for (i = 0; i < pdata->num_devices; i++) | |
277 | i2c_new_device(&i2c->adap, pdata->devices + i); | |
278 | ||
18f98b1e PK |
279 | return 0; |
280 | ||
281 | add_adapter_failed: | |
282 | free_irq(res2->start, i2c); | |
283 | request_irq_failed: | |
284 | iounmap(i2c->base); | |
285 | map_failed: | |
c6ffddea | 286 | release_mem_region(res->start, resource_size(res)); |
18f98b1e PK |
287 | request_mem_failed: |
288 | kfree(i2c); | |
289 | ||
290 | return ret; | |
291 | } | |
292 | ||
293 | static int __devexit ocores_i2c_remove(struct platform_device* pdev) | |
294 | { | |
295 | struct ocores_i2c *i2c = platform_get_drvdata(pdev); | |
296 | struct resource *res; | |
297 | ||
298 | /* disable i2c logic */ | |
299 | oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL) | |
300 | & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); | |
301 | ||
302 | /* remove adapter & data */ | |
303 | i2c_del_adapter(&i2c->adap); | |
304 | platform_set_drvdata(pdev, NULL); | |
305 | ||
306 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
307 | if (res) | |
308 | free_irq(res->start, i2c); | |
309 | ||
310 | iounmap(i2c->base); | |
311 | ||
312 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
313 | if (res) | |
c6ffddea | 314 | release_mem_region(res->start, resource_size(res)); |
18f98b1e PK |
315 | |
316 | kfree(i2c); | |
317 | ||
318 | return 0; | |
319 | } | |
320 | ||
2373c180 ML |
321 | #ifdef CONFIG_PM |
322 | static int ocores_i2c_suspend(struct platform_device *pdev, pm_message_t state) | |
323 | { | |
324 | struct ocores_i2c *i2c = platform_get_drvdata(pdev); | |
325 | u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); | |
326 | ||
327 | /* make sure the device is disabled */ | |
328 | oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); | |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
333 | static int ocores_i2c_resume(struct platform_device *pdev) | |
334 | { | |
335 | struct ocores_i2c *i2c = platform_get_drvdata(pdev); | |
336 | ||
337 | ocores_init(i2c); | |
338 | ||
339 | return 0; | |
340 | } | |
341 | #else | |
342 | #define ocores_i2c_suspend NULL | |
343 | #define ocores_i2c_resume NULL | |
344 | #endif | |
345 | ||
add8eda7 KS |
346 | /* work with hotplug and coldplug */ |
347 | MODULE_ALIAS("platform:ocores-i2c"); | |
348 | ||
18f98b1e | 349 | static struct platform_driver ocores_i2c_driver = { |
2373c180 ML |
350 | .probe = ocores_i2c_probe, |
351 | .remove = __devexit_p(ocores_i2c_remove), | |
352 | .suspend = ocores_i2c_suspend, | |
353 | .resume = ocores_i2c_resume, | |
354 | .driver = { | |
18f98b1e PK |
355 | .owner = THIS_MODULE, |
356 | .name = "ocores-i2c", | |
357 | }, | |
358 | }; | |
359 | ||
360 | static int __init ocores_i2c_init(void) | |
361 | { | |
362 | return platform_driver_register(&ocores_i2c_driver); | |
363 | } | |
364 | ||
365 | static void __exit ocores_i2c_exit(void) | |
366 | { | |
367 | platform_driver_unregister(&ocores_i2c_driver); | |
368 | } | |
369 | ||
370 | module_init(ocores_i2c_init); | |
371 | module_exit(ocores_i2c_exit); | |
372 | ||
373 | MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>"); | |
374 | MODULE_DESCRIPTION("OpenCores I2C bus driver"); | |
375 | MODULE_LICENSE("GPL"); |